id.c 15 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/id.c
  3. *
  4. * OMAP2 CPU identification code
  5. *
  6. * Copyright (C) 2005 Nokia Corporation
  7. * Written by Tony Lindgren <tony@atomide.com>
  8. *
  9. * Copyright (C) 2009-11 Texas Instruments
  10. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/io.h>
  20. #include <linux/slab.h>
  21. #ifdef CONFIG_SOC_BUS
  22. #include <linux/sys_soc.h>
  23. #endif
  24. #include <asm/cputype.h>
  25. #include "common.h"
  26. #include "id.h"
  27. #include "soc.h"
  28. #include "control.h"
  29. #define OMAP4_SILICON_TYPE_STANDARD 0x01
  30. #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
  31. #define OMAP_SOC_MAX_NAME_LENGTH 16
  32. static unsigned int omap_revision;
  33. static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
  34. static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
  35. u32 omap_features;
  36. unsigned int omap_rev(void)
  37. {
  38. return omap_revision;
  39. }
  40. EXPORT_SYMBOL(omap_rev);
  41. int omap_type(void)
  42. {
  43. u32 val = 0;
  44. if (cpu_is_omap24xx()) {
  45. val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  46. } else if (soc_is_am33xx()) {
  47. val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
  48. } else if (cpu_is_omap34xx()) {
  49. val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  50. } else if (cpu_is_omap44xx()) {
  51. val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  52. } else if (soc_is_omap54xx()) {
  53. val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
  54. val &= OMAP5_DEVICETYPE_MASK;
  55. val >>= 6;
  56. goto out;
  57. } else {
  58. pr_err("Cannot detect omap type!\n");
  59. goto out;
  60. }
  61. val &= OMAP2_DEVICETYPE_MASK;
  62. val >>= 8;
  63. out:
  64. return val;
  65. }
  66. EXPORT_SYMBOL(omap_type);
  67. /*----------------------------------------------------------------------------*/
  68. #define OMAP_TAP_IDCODE 0x0204
  69. #define OMAP_TAP_DIE_ID_0 0x0218
  70. #define OMAP_TAP_DIE_ID_1 0x021C
  71. #define OMAP_TAP_DIE_ID_2 0x0220
  72. #define OMAP_TAP_DIE_ID_3 0x0224
  73. #define OMAP_TAP_DIE_ID_44XX_0 0x0200
  74. #define OMAP_TAP_DIE_ID_44XX_1 0x0208
  75. #define OMAP_TAP_DIE_ID_44XX_2 0x020c
  76. #define OMAP_TAP_DIE_ID_44XX_3 0x0210
  77. #define read_tap_reg(reg) __raw_readl(tap_base + (reg))
  78. struct omap_id {
  79. u16 hawkeye; /* Silicon type (Hawkeye id) */
  80. u8 dev; /* Device type from production_id reg */
  81. u32 type; /* Combined type id copied to omap_revision */
  82. };
  83. /* Register values to detect the OMAP version */
  84. static struct omap_id omap_ids[] __initdata = {
  85. { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
  86. { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
  87. { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
  88. { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
  89. { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
  90. { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
  91. };
  92. static void __iomem *tap_base;
  93. static u16 tap_prod_id;
  94. void omap_get_die_id(struct omap_die_id *odi)
  95. {
  96. if (cpu_is_omap44xx() || soc_is_omap54xx()) {
  97. odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
  98. odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
  99. odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
  100. odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
  101. return;
  102. }
  103. odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
  104. odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
  105. odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
  106. odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
  107. }
  108. void __init omap2xxx_check_revision(void)
  109. {
  110. int i, j;
  111. u32 idcode, prod_id;
  112. u16 hawkeye;
  113. u8 dev_type, rev;
  114. struct omap_die_id odi;
  115. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  116. prod_id = read_tap_reg(tap_prod_id);
  117. hawkeye = (idcode >> 12) & 0xffff;
  118. rev = (idcode >> 28) & 0x0f;
  119. dev_type = (prod_id >> 16) & 0x0f;
  120. omap_get_die_id(&odi);
  121. pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
  122. idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
  123. pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
  124. pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
  125. odi.id_1, (odi.id_1 >> 28) & 0xf);
  126. pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
  127. pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
  128. pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
  129. prod_id, dev_type);
  130. /* Check hawkeye ids */
  131. for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
  132. if (hawkeye == omap_ids[i].hawkeye)
  133. break;
  134. }
  135. if (i == ARRAY_SIZE(omap_ids)) {
  136. printk(KERN_ERR "Unknown OMAP CPU id\n");
  137. return;
  138. }
  139. for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
  140. if (dev_type == omap_ids[j].dev)
  141. break;
  142. }
  143. if (j == ARRAY_SIZE(omap_ids)) {
  144. pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
  145. omap_ids[i].type >> 16);
  146. j = i;
  147. }
  148. sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
  149. sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
  150. pr_info("%s", soc_name);
  151. if ((omap_rev() >> 8) & 0x0f)
  152. pr_info("%s", soc_rev);
  153. pr_info("\n");
  154. }
  155. #define OMAP3_SHOW_FEATURE(feat) \
  156. if (omap3_has_ ##feat()) \
  157. printk(#feat" ");
  158. static void __init omap3_cpuinfo(void)
  159. {
  160. const char *cpu_name;
  161. /*
  162. * OMAP3430 and OMAP3530 are assumed to be same.
  163. *
  164. * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
  165. * on available features. Upon detection, update the CPU id
  166. * and CPU class bits.
  167. */
  168. if (cpu_is_omap3630()) {
  169. cpu_name = "OMAP3630";
  170. } else if (soc_is_am35xx()) {
  171. cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
  172. } else if (cpu_is_ti816x()) {
  173. cpu_name = "TI816X";
  174. } else if (soc_is_am335x()) {
  175. cpu_name = "AM335X";
  176. } else if (cpu_is_ti814x()) {
  177. cpu_name = "TI814X";
  178. } else if (omap3_has_iva() && omap3_has_sgx()) {
  179. /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
  180. cpu_name = "OMAP3430/3530";
  181. } else if (omap3_has_iva()) {
  182. cpu_name = "OMAP3525";
  183. } else if (omap3_has_sgx()) {
  184. cpu_name = "OMAP3515";
  185. } else {
  186. cpu_name = "OMAP3503";
  187. }
  188. sprintf(soc_name, "%s", cpu_name);
  189. /* Print verbose information */
  190. pr_info("%s %s (", soc_name, soc_rev);
  191. OMAP3_SHOW_FEATURE(l2cache);
  192. OMAP3_SHOW_FEATURE(iva);
  193. OMAP3_SHOW_FEATURE(sgx);
  194. OMAP3_SHOW_FEATURE(neon);
  195. OMAP3_SHOW_FEATURE(isp);
  196. OMAP3_SHOW_FEATURE(192mhz_clk);
  197. printk(")\n");
  198. }
  199. #define OMAP3_CHECK_FEATURE(status,feat) \
  200. if (((status & OMAP3_ ##feat## _MASK) \
  201. >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
  202. omap_features |= OMAP3_HAS_ ##feat; \
  203. }
  204. void __init omap3xxx_check_features(void)
  205. {
  206. u32 status;
  207. omap_features = 0;
  208. status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
  209. OMAP3_CHECK_FEATURE(status, L2CACHE);
  210. OMAP3_CHECK_FEATURE(status, IVA);
  211. OMAP3_CHECK_FEATURE(status, SGX);
  212. OMAP3_CHECK_FEATURE(status, NEON);
  213. OMAP3_CHECK_FEATURE(status, ISP);
  214. if (cpu_is_omap3630())
  215. omap_features |= OMAP3_HAS_192MHZ_CLK;
  216. if (cpu_is_omap3430() || cpu_is_omap3630())
  217. omap_features |= OMAP3_HAS_IO_WAKEUP;
  218. if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
  219. omap_rev() == OMAP3430_REV_ES3_1_2)
  220. omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
  221. omap_features |= OMAP3_HAS_SDRC;
  222. /*
  223. * am35x fixups:
  224. * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
  225. * reserved and therefore return 0 when read. Unfortunately,
  226. * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
  227. * mean that a feature is present even though it isn't so clear
  228. * the incorrectly set feature bits.
  229. */
  230. if (soc_is_am35xx())
  231. omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
  232. /*
  233. * TODO: Get additional info (where applicable)
  234. * e.g. Size of L2 cache.
  235. */
  236. omap3_cpuinfo();
  237. }
  238. void __init omap4xxx_check_features(void)
  239. {
  240. u32 si_type;
  241. si_type =
  242. (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
  243. if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
  244. omap_features = OMAP4_HAS_PERF_SILICON;
  245. }
  246. void __init ti81xx_check_features(void)
  247. {
  248. omap_features = OMAP3_HAS_NEON;
  249. omap3_cpuinfo();
  250. }
  251. void __init omap3xxx_check_revision(void)
  252. {
  253. const char *cpu_rev;
  254. u32 cpuid, idcode;
  255. u16 hawkeye;
  256. u8 rev;
  257. /*
  258. * We cannot access revision registers on ES1.0.
  259. * If the processor type is Cortex-A8 and the revision is 0x0
  260. * it means its Cortex r0p0 which is 3430 ES1.0.
  261. */
  262. cpuid = read_cpuid_id();
  263. if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
  264. omap_revision = OMAP3430_REV_ES1_0;
  265. cpu_rev = "1.0";
  266. return;
  267. }
  268. /*
  269. * Detection for 34xx ES2.0 and above can be done with just
  270. * hawkeye and rev. See TRM 1.5.2 Device Identification.
  271. * Note that rev does not map directly to our defined processor
  272. * revision numbers as ES1.0 uses value 0.
  273. */
  274. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  275. hawkeye = (idcode >> 12) & 0xffff;
  276. rev = (idcode >> 28) & 0xff;
  277. switch (hawkeye) {
  278. case 0xb7ae:
  279. /* Handle 34xx/35xx devices */
  280. switch (rev) {
  281. case 0: /* Take care of early samples */
  282. case 1:
  283. omap_revision = OMAP3430_REV_ES2_0;
  284. cpu_rev = "2.0";
  285. break;
  286. case 2:
  287. omap_revision = OMAP3430_REV_ES2_1;
  288. cpu_rev = "2.1";
  289. break;
  290. case 3:
  291. omap_revision = OMAP3430_REV_ES3_0;
  292. cpu_rev = "3.0";
  293. break;
  294. case 4:
  295. omap_revision = OMAP3430_REV_ES3_1;
  296. cpu_rev = "3.1";
  297. break;
  298. case 7:
  299. /* FALLTHROUGH */
  300. default:
  301. /* Use the latest known revision as default */
  302. omap_revision = OMAP3430_REV_ES3_1_2;
  303. cpu_rev = "3.1.2";
  304. }
  305. break;
  306. case 0xb868:
  307. /*
  308. * Handle OMAP/AM 3505/3517 devices
  309. *
  310. * Set the device to be OMAP3517 here. Actual device
  311. * is identified later based on the features.
  312. */
  313. switch (rev) {
  314. case 0:
  315. omap_revision = AM35XX_REV_ES1_0;
  316. cpu_rev = "1.0";
  317. break;
  318. case 1:
  319. /* FALLTHROUGH */
  320. default:
  321. omap_revision = AM35XX_REV_ES1_1;
  322. cpu_rev = "1.1";
  323. }
  324. break;
  325. case 0xb891:
  326. /* Handle 36xx devices */
  327. switch(rev) {
  328. case 0: /* Take care of early samples */
  329. omap_revision = OMAP3630_REV_ES1_0;
  330. cpu_rev = "1.0";
  331. break;
  332. case 1:
  333. omap_revision = OMAP3630_REV_ES1_1;
  334. cpu_rev = "1.1";
  335. break;
  336. case 2:
  337. /* FALLTHROUGH */
  338. default:
  339. omap_revision = OMAP3630_REV_ES1_2;
  340. cpu_rev = "1.2";
  341. }
  342. break;
  343. case 0xb81e:
  344. switch (rev) {
  345. case 0:
  346. omap_revision = TI8168_REV_ES1_0;
  347. cpu_rev = "1.0";
  348. break;
  349. case 1:
  350. /* FALLTHROUGH */
  351. default:
  352. omap_revision = TI8168_REV_ES1_1;
  353. cpu_rev = "1.1";
  354. break;
  355. }
  356. break;
  357. case 0xb944:
  358. switch (rev) {
  359. case 0:
  360. omap_revision = AM335X_REV_ES1_0;
  361. cpu_rev = "1.0";
  362. break;
  363. case 1:
  364. omap_revision = AM335X_REV_ES2_0;
  365. cpu_rev = "2.0";
  366. break;
  367. case 2:
  368. /* FALLTHROUGH */
  369. default:
  370. omap_revision = AM335X_REV_ES2_1;
  371. cpu_rev = "2.1";
  372. break;
  373. }
  374. break;
  375. case 0xb8f2:
  376. switch (rev) {
  377. case 0:
  378. /* FALLTHROUGH */
  379. case 1:
  380. omap_revision = TI8148_REV_ES1_0;
  381. cpu_rev = "1.0";
  382. break;
  383. case 2:
  384. omap_revision = TI8148_REV_ES2_0;
  385. cpu_rev = "2.0";
  386. break;
  387. case 3:
  388. /* FALLTHROUGH */
  389. default:
  390. omap_revision = TI8148_REV_ES2_1;
  391. cpu_rev = "2.1";
  392. break;
  393. }
  394. break;
  395. default:
  396. /* Unknown default to latest silicon rev as default */
  397. omap_revision = OMAP3630_REV_ES1_2;
  398. cpu_rev = "1.2";
  399. pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
  400. }
  401. sprintf(soc_rev, "ES%s", cpu_rev);
  402. }
  403. void __init omap4xxx_check_revision(void)
  404. {
  405. u32 idcode;
  406. u16 hawkeye;
  407. u8 rev;
  408. /*
  409. * The IC rev detection is done with hawkeye and rev.
  410. * Note that rev does not map directly to defined processor
  411. * revision numbers as ES1.0 uses value 0.
  412. */
  413. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  414. hawkeye = (idcode >> 12) & 0xffff;
  415. rev = (idcode >> 28) & 0xf;
  416. /*
  417. * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
  418. * Use ARM register to detect the correct ES version
  419. */
  420. if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
  421. idcode = read_cpuid_id();
  422. rev = (idcode & 0xf) - 1;
  423. }
  424. switch (hawkeye) {
  425. case 0xb852:
  426. switch (rev) {
  427. case 0:
  428. omap_revision = OMAP4430_REV_ES1_0;
  429. break;
  430. case 1:
  431. default:
  432. omap_revision = OMAP4430_REV_ES2_0;
  433. }
  434. break;
  435. case 0xb95c:
  436. switch (rev) {
  437. case 3:
  438. omap_revision = OMAP4430_REV_ES2_1;
  439. break;
  440. case 4:
  441. omap_revision = OMAP4430_REV_ES2_2;
  442. break;
  443. case 6:
  444. default:
  445. omap_revision = OMAP4430_REV_ES2_3;
  446. }
  447. break;
  448. case 0xb94e:
  449. switch (rev) {
  450. case 0:
  451. omap_revision = OMAP4460_REV_ES1_0;
  452. break;
  453. case 2:
  454. default:
  455. omap_revision = OMAP4460_REV_ES1_1;
  456. break;
  457. }
  458. break;
  459. case 0xb975:
  460. switch (rev) {
  461. case 0:
  462. default:
  463. omap_revision = OMAP4470_REV_ES1_0;
  464. break;
  465. }
  466. break;
  467. default:
  468. /* Unknown default to latest silicon rev as default */
  469. omap_revision = OMAP4430_REV_ES2_3;
  470. }
  471. sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
  472. sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
  473. (omap_rev() >> 8) & 0xf);
  474. pr_info("%s %s\n", soc_name, soc_rev);
  475. }
  476. void __init omap5xxx_check_revision(void)
  477. {
  478. u32 idcode;
  479. u16 hawkeye;
  480. u8 rev;
  481. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  482. hawkeye = (idcode >> 12) & 0xffff;
  483. rev = (idcode >> 28) & 0xff;
  484. switch (hawkeye) {
  485. case 0xb942:
  486. switch (rev) {
  487. case 0:
  488. omap_revision = OMAP5430_REV_ES1_0;
  489. break;
  490. case 1:
  491. default:
  492. omap_revision = OMAP5430_REV_ES2_0;
  493. }
  494. break;
  495. case 0xb998:
  496. switch (rev) {
  497. case 0:
  498. omap_revision = OMAP5432_REV_ES1_0;
  499. break;
  500. case 1:
  501. default:
  502. omap_revision = OMAP5432_REV_ES2_0;
  503. }
  504. break;
  505. default:
  506. /* Unknown default to latest silicon rev as default*/
  507. omap_revision = OMAP5430_REV_ES2_0;
  508. }
  509. sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
  510. sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
  511. pr_info("%s %s\n", soc_name, soc_rev);
  512. }
  513. /*
  514. * Set up things for map_io and processor detection later on. Gets called
  515. * pretty much first thing from board init. For multi-omap, this gets
  516. * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
  517. * detect the exact revision later on in omap2_detect_revision() once map_io
  518. * is done.
  519. */
  520. void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
  521. {
  522. omap_revision = class;
  523. tap_base = tap;
  524. /* XXX What is this intended to do? */
  525. if (cpu_is_omap34xx())
  526. tap_prod_id = 0x0210;
  527. else
  528. tap_prod_id = 0x0208;
  529. }
  530. #ifdef CONFIG_SOC_BUS
  531. static const char const *omap_types[] = {
  532. [OMAP2_DEVICE_TYPE_TEST] = "TST",
  533. [OMAP2_DEVICE_TYPE_EMU] = "EMU",
  534. [OMAP2_DEVICE_TYPE_SEC] = "HS",
  535. [OMAP2_DEVICE_TYPE_GP] = "GP",
  536. [OMAP2_DEVICE_TYPE_BAD] = "BAD",
  537. };
  538. static const char * __init omap_get_family(void)
  539. {
  540. if (cpu_is_omap24xx())
  541. return kasprintf(GFP_KERNEL, "OMAP2");
  542. else if (cpu_is_omap34xx())
  543. return kasprintf(GFP_KERNEL, "OMAP3");
  544. else if (cpu_is_omap44xx())
  545. return kasprintf(GFP_KERNEL, "OMAP4");
  546. else if (soc_is_omap54xx())
  547. return kasprintf(GFP_KERNEL, "OMAP5");
  548. else
  549. return kasprintf(GFP_KERNEL, "Unknown");
  550. }
  551. static ssize_t omap_get_type(struct device *dev,
  552. struct device_attribute *attr,
  553. char *buf)
  554. {
  555. return sprintf(buf, "%s\n", omap_types[omap_type()]);
  556. }
  557. static struct device_attribute omap_soc_attr =
  558. __ATTR(type, S_IRUGO, omap_get_type, NULL);
  559. void __init omap_soc_device_init(void)
  560. {
  561. struct device *parent;
  562. struct soc_device *soc_dev;
  563. struct soc_device_attribute *soc_dev_attr;
  564. soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
  565. if (!soc_dev_attr)
  566. return;
  567. soc_dev_attr->machine = soc_name;
  568. soc_dev_attr->family = omap_get_family();
  569. soc_dev_attr->revision = soc_rev;
  570. soc_dev = soc_device_register(soc_dev_attr);
  571. if (IS_ERR(soc_dev)) {
  572. kfree(soc_dev_attr);
  573. return;
  574. }
  575. parent = soc_device_to_device(soc_dev);
  576. device_create_file(parent, &omap_soc_attr);
  577. }
  578. #endif /* CONFIG_SOC_BUS */