gpmc.c 46 KB

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  1. /*
  2. * GPMC support functions
  3. *
  4. * Copyright (C) 2005-2006 Nokia Corporation
  5. *
  6. * Author: Juha Yrjola
  7. *
  8. * Copyright (C) 2009 Texas Instruments
  9. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #undef DEBUG
  16. #include <linux/irq.h>
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/err.h>
  20. #include <linux/clk.h>
  21. #include <linux/ioport.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/io.h>
  24. #include <linux/module.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/of.h>
  28. #include <linux/of_address.h>
  29. #include <linux/of_mtd.h>
  30. #include <linux/of_device.h>
  31. #include <linux/mtd/nand.h>
  32. #include <linux/platform_data/mtd-nand-omap2.h>
  33. #include <asm/mach-types.h>
  34. #include "soc.h"
  35. #include "common.h"
  36. #include "omap_device.h"
  37. #include "gpmc.h"
  38. #include "gpmc-nand.h"
  39. #include "gpmc-onenand.h"
  40. #define DEVICE_NAME "omap-gpmc"
  41. /* GPMC register offsets */
  42. #define GPMC_REVISION 0x00
  43. #define GPMC_SYSCONFIG 0x10
  44. #define GPMC_SYSSTATUS 0x14
  45. #define GPMC_IRQSTATUS 0x18
  46. #define GPMC_IRQENABLE 0x1c
  47. #define GPMC_TIMEOUT_CONTROL 0x40
  48. #define GPMC_ERR_ADDRESS 0x44
  49. #define GPMC_ERR_TYPE 0x48
  50. #define GPMC_CONFIG 0x50
  51. #define GPMC_STATUS 0x54
  52. #define GPMC_PREFETCH_CONFIG1 0x1e0
  53. #define GPMC_PREFETCH_CONFIG2 0x1e4
  54. #define GPMC_PREFETCH_CONTROL 0x1ec
  55. #define GPMC_PREFETCH_STATUS 0x1f0
  56. #define GPMC_ECC_CONFIG 0x1f4
  57. #define GPMC_ECC_CONTROL 0x1f8
  58. #define GPMC_ECC_SIZE_CONFIG 0x1fc
  59. #define GPMC_ECC1_RESULT 0x200
  60. #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
  61. #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
  62. #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
  63. #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
  64. /* GPMC ECC control settings */
  65. #define GPMC_ECC_CTRL_ECCCLEAR 0x100
  66. #define GPMC_ECC_CTRL_ECCDISABLE 0x000
  67. #define GPMC_ECC_CTRL_ECCREG1 0x001
  68. #define GPMC_ECC_CTRL_ECCREG2 0x002
  69. #define GPMC_ECC_CTRL_ECCREG3 0x003
  70. #define GPMC_ECC_CTRL_ECCREG4 0x004
  71. #define GPMC_ECC_CTRL_ECCREG5 0x005
  72. #define GPMC_ECC_CTRL_ECCREG6 0x006
  73. #define GPMC_ECC_CTRL_ECCREG7 0x007
  74. #define GPMC_ECC_CTRL_ECCREG8 0x008
  75. #define GPMC_ECC_CTRL_ECCREG9 0x009
  76. #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
  77. #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
  78. #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
  79. #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
  80. #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
  81. #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
  82. #define GPMC_CS0_OFFSET 0x60
  83. #define GPMC_CS_SIZE 0x30
  84. #define GPMC_BCH_SIZE 0x10
  85. #define GPMC_MEM_END 0x3FFFFFFF
  86. #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
  87. #define GPMC_SECTION_SHIFT 28 /* 128 MB */
  88. #define CS_NUM_SHIFT 24
  89. #define ENABLE_PREFETCH (0x1 << 7)
  90. #define DMA_MPU_MODE 2
  91. #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
  92. #define GPMC_REVISION_MINOR(l) (l & 0xf)
  93. #define GPMC_HAS_WR_ACCESS 0x1
  94. #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
  95. #define GPMC_HAS_MUX_AAD 0x4
  96. #define GPMC_NR_WAITPINS 4
  97. /* XXX: Only NAND irq has been considered,currently these are the only ones used
  98. */
  99. #define GPMC_NR_IRQ 2
  100. struct gpmc_client_irq {
  101. unsigned irq;
  102. u32 bitmask;
  103. };
  104. /* Structure to save gpmc cs context */
  105. struct gpmc_cs_config {
  106. u32 config1;
  107. u32 config2;
  108. u32 config3;
  109. u32 config4;
  110. u32 config5;
  111. u32 config6;
  112. u32 config7;
  113. int is_valid;
  114. };
  115. /*
  116. * Structure to save/restore gpmc context
  117. * to support core off on OMAP3
  118. */
  119. struct omap3_gpmc_regs {
  120. u32 sysconfig;
  121. u32 irqenable;
  122. u32 timeout_ctrl;
  123. u32 config;
  124. u32 prefetch_config1;
  125. u32 prefetch_config2;
  126. u32 prefetch_control;
  127. struct gpmc_cs_config cs_context[GPMC_CS_NUM];
  128. };
  129. static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
  130. static struct irq_chip gpmc_irq_chip;
  131. static unsigned gpmc_irq_start;
  132. static struct resource gpmc_mem_root;
  133. static struct resource gpmc_cs_mem[GPMC_CS_NUM];
  134. static DEFINE_SPINLOCK(gpmc_mem_lock);
  135. /* Define chip-selects as reserved by default until probe completes */
  136. static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
  137. static unsigned int gpmc_nr_waitpins;
  138. static struct device *gpmc_dev;
  139. static int gpmc_irq;
  140. static resource_size_t phys_base, mem_size;
  141. static unsigned gpmc_capability;
  142. static void __iomem *gpmc_base;
  143. static struct clk *gpmc_l3_clk;
  144. static irqreturn_t gpmc_handle_irq(int irq, void *dev);
  145. static void gpmc_write_reg(int idx, u32 val)
  146. {
  147. __raw_writel(val, gpmc_base + idx);
  148. }
  149. static u32 gpmc_read_reg(int idx)
  150. {
  151. return __raw_readl(gpmc_base + idx);
  152. }
  153. void gpmc_cs_write_reg(int cs, int idx, u32 val)
  154. {
  155. void __iomem *reg_addr;
  156. reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  157. __raw_writel(val, reg_addr);
  158. }
  159. static u32 gpmc_cs_read_reg(int cs, int idx)
  160. {
  161. void __iomem *reg_addr;
  162. reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
  163. return __raw_readl(reg_addr);
  164. }
  165. /* TODO: Add support for gpmc_fck to clock framework and use it */
  166. static unsigned long gpmc_get_fclk_period(void)
  167. {
  168. unsigned long rate = clk_get_rate(gpmc_l3_clk);
  169. if (rate == 0) {
  170. printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
  171. return 0;
  172. }
  173. rate /= 1000;
  174. rate = 1000000000 / rate; /* In picoseconds */
  175. return rate;
  176. }
  177. static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
  178. {
  179. unsigned long tick_ps;
  180. /* Calculate in picosecs to yield more exact results */
  181. tick_ps = gpmc_get_fclk_period();
  182. return (time_ns * 1000 + tick_ps - 1) / tick_ps;
  183. }
  184. static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
  185. {
  186. unsigned long tick_ps;
  187. /* Calculate in picosecs to yield more exact results */
  188. tick_ps = gpmc_get_fclk_period();
  189. return (time_ps + tick_ps - 1) / tick_ps;
  190. }
  191. unsigned int gpmc_ticks_to_ns(unsigned int ticks)
  192. {
  193. return ticks * gpmc_get_fclk_period() / 1000;
  194. }
  195. static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
  196. {
  197. return ticks * gpmc_get_fclk_period();
  198. }
  199. static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
  200. {
  201. unsigned long ticks = gpmc_ps_to_ticks(time_ps);
  202. return ticks * gpmc_get_fclk_period();
  203. }
  204. static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
  205. {
  206. u32 l;
  207. l = gpmc_cs_read_reg(cs, reg);
  208. if (value)
  209. l |= mask;
  210. else
  211. l &= ~mask;
  212. gpmc_cs_write_reg(cs, reg, l);
  213. }
  214. static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
  215. {
  216. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
  217. GPMC_CONFIG1_TIME_PARA_GRAN,
  218. p->time_para_granularity);
  219. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
  220. GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
  221. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
  222. GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
  223. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
  224. GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
  225. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
  226. GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
  227. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
  228. GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
  229. p->cycle2cyclesamecsen);
  230. gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
  231. GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
  232. p->cycle2cyclediffcsen);
  233. }
  234. #ifdef DEBUG
  235. static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
  236. int time, const char *name)
  237. #else
  238. static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
  239. int time)
  240. #endif
  241. {
  242. u32 l;
  243. int ticks, mask, nr_bits;
  244. if (time == 0)
  245. ticks = 0;
  246. else
  247. ticks = gpmc_ns_to_ticks(time);
  248. nr_bits = end_bit - st_bit + 1;
  249. if (ticks >= 1 << nr_bits) {
  250. #ifdef DEBUG
  251. printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
  252. cs, name, time, ticks, 1 << nr_bits);
  253. #endif
  254. return -1;
  255. }
  256. mask = (1 << nr_bits) - 1;
  257. l = gpmc_cs_read_reg(cs, reg);
  258. #ifdef DEBUG
  259. printk(KERN_INFO
  260. "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
  261. cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
  262. (l >> st_bit) & mask, time);
  263. #endif
  264. l &= ~(mask << st_bit);
  265. l |= ticks << st_bit;
  266. gpmc_cs_write_reg(cs, reg, l);
  267. return 0;
  268. }
  269. #ifdef DEBUG
  270. #define GPMC_SET_ONE(reg, st, end, field) \
  271. if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
  272. t->field, #field) < 0) \
  273. return -1
  274. #else
  275. #define GPMC_SET_ONE(reg, st, end, field) \
  276. if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
  277. return -1
  278. #endif
  279. int gpmc_calc_divider(unsigned int sync_clk)
  280. {
  281. int div;
  282. u32 l;
  283. l = sync_clk + (gpmc_get_fclk_period() - 1);
  284. div = l / gpmc_get_fclk_period();
  285. if (div > 4)
  286. return -1;
  287. if (div <= 0)
  288. div = 1;
  289. return div;
  290. }
  291. int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
  292. {
  293. int div;
  294. u32 l;
  295. div = gpmc_calc_divider(t->sync_clk);
  296. if (div < 0)
  297. return div;
  298. GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
  299. GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
  300. GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
  301. GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
  302. GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
  303. GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
  304. GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
  305. GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
  306. GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
  307. GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
  308. GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
  309. GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
  310. GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
  311. GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
  312. GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
  313. GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
  314. GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
  315. GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
  316. if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
  317. GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
  318. if (gpmc_capability & GPMC_HAS_WR_ACCESS)
  319. GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
  320. /* caller is expected to have initialized CONFIG1 to cover
  321. * at least sync vs async
  322. */
  323. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
  324. if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
  325. #ifdef DEBUG
  326. printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
  327. cs, (div * gpmc_get_fclk_period()) / 1000, div);
  328. #endif
  329. l &= ~0x03;
  330. l |= (div - 1);
  331. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
  332. }
  333. gpmc_cs_bool_timings(cs, &t->bool_timings);
  334. return 0;
  335. }
  336. static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
  337. {
  338. u32 l;
  339. u32 mask;
  340. /*
  341. * Ensure that base address is aligned on a
  342. * boundary equal to or greater than size.
  343. */
  344. if (base & (size - 1))
  345. return -EINVAL;
  346. mask = (1 << GPMC_SECTION_SHIFT) - size;
  347. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  348. l &= ~0x3f;
  349. l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
  350. l &= ~(0x0f << 8);
  351. l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
  352. l |= GPMC_CONFIG7_CSVALID;
  353. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  354. return 0;
  355. }
  356. static void gpmc_cs_disable_mem(int cs)
  357. {
  358. u32 l;
  359. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  360. l &= ~GPMC_CONFIG7_CSVALID;
  361. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
  362. }
  363. static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
  364. {
  365. u32 l;
  366. u32 mask;
  367. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  368. *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
  369. mask = (l >> 8) & 0x0f;
  370. *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
  371. }
  372. static int gpmc_cs_mem_enabled(int cs)
  373. {
  374. u32 l;
  375. l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
  376. return l & GPMC_CONFIG7_CSVALID;
  377. }
  378. static void gpmc_cs_set_reserved(int cs, int reserved)
  379. {
  380. gpmc_cs_map &= ~(1 << cs);
  381. gpmc_cs_map |= (reserved ? 1 : 0) << cs;
  382. }
  383. static bool gpmc_cs_reserved(int cs)
  384. {
  385. return gpmc_cs_map & (1 << cs);
  386. }
  387. static unsigned long gpmc_mem_align(unsigned long size)
  388. {
  389. int order;
  390. size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
  391. order = GPMC_CHUNK_SHIFT - 1;
  392. do {
  393. size >>= 1;
  394. order++;
  395. } while (size);
  396. size = 1 << order;
  397. return size;
  398. }
  399. static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
  400. {
  401. struct resource *res = &gpmc_cs_mem[cs];
  402. int r;
  403. size = gpmc_mem_align(size);
  404. spin_lock(&gpmc_mem_lock);
  405. res->start = base;
  406. res->end = base + size - 1;
  407. r = request_resource(&gpmc_mem_root, res);
  408. spin_unlock(&gpmc_mem_lock);
  409. return r;
  410. }
  411. static int gpmc_cs_delete_mem(int cs)
  412. {
  413. struct resource *res = &gpmc_cs_mem[cs];
  414. int r;
  415. spin_lock(&gpmc_mem_lock);
  416. r = release_resource(&gpmc_cs_mem[cs]);
  417. res->start = 0;
  418. res->end = 0;
  419. spin_unlock(&gpmc_mem_lock);
  420. return r;
  421. }
  422. /**
  423. * gpmc_cs_remap - remaps a chip-select physical base address
  424. * @cs: chip-select to remap
  425. * @base: physical base address to re-map chip-select to
  426. *
  427. * Re-maps a chip-select to a new physical base address specified by
  428. * "base". Returns 0 on success and appropriate negative error code
  429. * on failure.
  430. */
  431. static int gpmc_cs_remap(int cs, u32 base)
  432. {
  433. int ret;
  434. u32 old_base, size;
  435. if (cs > GPMC_CS_NUM)
  436. return -ENODEV;
  437. gpmc_cs_get_memconf(cs, &old_base, &size);
  438. if (base == old_base)
  439. return 0;
  440. gpmc_cs_disable_mem(cs);
  441. ret = gpmc_cs_delete_mem(cs);
  442. if (ret < 0)
  443. return ret;
  444. ret = gpmc_cs_insert_mem(cs, base, size);
  445. if (ret < 0)
  446. return ret;
  447. ret = gpmc_cs_enable_mem(cs, base, size);
  448. if (ret < 0)
  449. return ret;
  450. return 0;
  451. }
  452. int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
  453. {
  454. struct resource *res = &gpmc_cs_mem[cs];
  455. int r = -1;
  456. if (cs > GPMC_CS_NUM)
  457. return -ENODEV;
  458. size = gpmc_mem_align(size);
  459. if (size > (1 << GPMC_SECTION_SHIFT))
  460. return -ENOMEM;
  461. spin_lock(&gpmc_mem_lock);
  462. if (gpmc_cs_reserved(cs)) {
  463. r = -EBUSY;
  464. goto out;
  465. }
  466. if (gpmc_cs_mem_enabled(cs))
  467. r = adjust_resource(res, res->start & ~(size - 1), size);
  468. if (r < 0)
  469. r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
  470. size, NULL, NULL);
  471. if (r < 0)
  472. goto out;
  473. r = gpmc_cs_enable_mem(cs, res->start, resource_size(res));
  474. if (r < 0) {
  475. release_resource(res);
  476. goto out;
  477. }
  478. *base = res->start;
  479. gpmc_cs_set_reserved(cs, 1);
  480. out:
  481. spin_unlock(&gpmc_mem_lock);
  482. return r;
  483. }
  484. EXPORT_SYMBOL(gpmc_cs_request);
  485. void gpmc_cs_free(int cs)
  486. {
  487. spin_lock(&gpmc_mem_lock);
  488. if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
  489. printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
  490. BUG();
  491. spin_unlock(&gpmc_mem_lock);
  492. return;
  493. }
  494. gpmc_cs_disable_mem(cs);
  495. release_resource(&gpmc_cs_mem[cs]);
  496. gpmc_cs_set_reserved(cs, 0);
  497. spin_unlock(&gpmc_mem_lock);
  498. }
  499. EXPORT_SYMBOL(gpmc_cs_free);
  500. /**
  501. * gpmc_configure - write request to configure gpmc
  502. * @cmd: command type
  503. * @wval: value to write
  504. * @return status of the operation
  505. */
  506. int gpmc_configure(int cmd, int wval)
  507. {
  508. u32 regval;
  509. switch (cmd) {
  510. case GPMC_ENABLE_IRQ:
  511. gpmc_write_reg(GPMC_IRQENABLE, wval);
  512. break;
  513. case GPMC_SET_IRQ_STATUS:
  514. gpmc_write_reg(GPMC_IRQSTATUS, wval);
  515. break;
  516. case GPMC_CONFIG_WP:
  517. regval = gpmc_read_reg(GPMC_CONFIG);
  518. if (wval)
  519. regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
  520. else
  521. regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
  522. gpmc_write_reg(GPMC_CONFIG, regval);
  523. break;
  524. default:
  525. pr_err("%s: command not supported\n", __func__);
  526. return -EINVAL;
  527. }
  528. return 0;
  529. }
  530. EXPORT_SYMBOL(gpmc_configure);
  531. void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
  532. {
  533. int i;
  534. reg->gpmc_status = gpmc_base + GPMC_STATUS;
  535. reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
  536. GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
  537. reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
  538. GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
  539. reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
  540. GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
  541. reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
  542. reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
  543. reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
  544. reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
  545. reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
  546. reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
  547. reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
  548. reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
  549. for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
  550. reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
  551. GPMC_BCH_SIZE * i;
  552. reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
  553. GPMC_BCH_SIZE * i;
  554. reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
  555. GPMC_BCH_SIZE * i;
  556. reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
  557. GPMC_BCH_SIZE * i;
  558. }
  559. }
  560. int gpmc_get_client_irq(unsigned irq_config)
  561. {
  562. int i;
  563. if (hweight32(irq_config) > 1)
  564. return 0;
  565. for (i = 0; i < GPMC_NR_IRQ; i++)
  566. if (gpmc_client_irq[i].bitmask & irq_config)
  567. return gpmc_client_irq[i].irq;
  568. return 0;
  569. }
  570. static int gpmc_irq_endis(unsigned irq, bool endis)
  571. {
  572. int i;
  573. u32 regval;
  574. for (i = 0; i < GPMC_NR_IRQ; i++)
  575. if (irq == gpmc_client_irq[i].irq) {
  576. regval = gpmc_read_reg(GPMC_IRQENABLE);
  577. if (endis)
  578. regval |= gpmc_client_irq[i].bitmask;
  579. else
  580. regval &= ~gpmc_client_irq[i].bitmask;
  581. gpmc_write_reg(GPMC_IRQENABLE, regval);
  582. break;
  583. }
  584. return 0;
  585. }
  586. static void gpmc_irq_disable(struct irq_data *p)
  587. {
  588. gpmc_irq_endis(p->irq, false);
  589. }
  590. static void gpmc_irq_enable(struct irq_data *p)
  591. {
  592. gpmc_irq_endis(p->irq, true);
  593. }
  594. static void gpmc_irq_noop(struct irq_data *data) { }
  595. static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
  596. static int gpmc_setup_irq(void)
  597. {
  598. int i;
  599. u32 regval;
  600. if (!gpmc_irq)
  601. return -EINVAL;
  602. gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
  603. if (gpmc_irq_start < 0) {
  604. pr_err("irq_alloc_descs failed\n");
  605. return gpmc_irq_start;
  606. }
  607. gpmc_irq_chip.name = "gpmc";
  608. gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
  609. gpmc_irq_chip.irq_enable = gpmc_irq_enable;
  610. gpmc_irq_chip.irq_disable = gpmc_irq_disable;
  611. gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
  612. gpmc_irq_chip.irq_ack = gpmc_irq_noop;
  613. gpmc_irq_chip.irq_mask = gpmc_irq_noop;
  614. gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
  615. gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
  616. gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
  617. for (i = 0; i < GPMC_NR_IRQ; i++) {
  618. gpmc_client_irq[i].irq = gpmc_irq_start + i;
  619. irq_set_chip_and_handler(gpmc_client_irq[i].irq,
  620. &gpmc_irq_chip, handle_simple_irq);
  621. set_irq_flags(gpmc_client_irq[i].irq,
  622. IRQF_VALID | IRQF_NOAUTOEN);
  623. }
  624. /* Disable interrupts */
  625. gpmc_write_reg(GPMC_IRQENABLE, 0);
  626. /* clear interrupts */
  627. regval = gpmc_read_reg(GPMC_IRQSTATUS);
  628. gpmc_write_reg(GPMC_IRQSTATUS, regval);
  629. return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
  630. }
  631. static int gpmc_free_irq(void)
  632. {
  633. int i;
  634. if (gpmc_irq)
  635. free_irq(gpmc_irq, NULL);
  636. for (i = 0; i < GPMC_NR_IRQ; i++) {
  637. irq_set_handler(gpmc_client_irq[i].irq, NULL);
  638. irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
  639. irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
  640. }
  641. irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
  642. return 0;
  643. }
  644. static void gpmc_mem_exit(void)
  645. {
  646. int cs;
  647. for (cs = 0; cs < GPMC_CS_NUM; cs++) {
  648. if (!gpmc_cs_mem_enabled(cs))
  649. continue;
  650. gpmc_cs_delete_mem(cs);
  651. }
  652. }
  653. static void gpmc_mem_init(void)
  654. {
  655. int cs;
  656. /*
  657. * The first 1MB of GPMC address space is typically mapped to
  658. * the internal ROM. Never allocate the first page, to
  659. * facilitate bug detection; even if we didn't boot from ROM.
  660. */
  661. gpmc_mem_root.start = SZ_1M;
  662. gpmc_mem_root.end = GPMC_MEM_END;
  663. /* Reserve all regions that has been set up by bootloader */
  664. for (cs = 0; cs < GPMC_CS_NUM; cs++) {
  665. u32 base, size;
  666. if (!gpmc_cs_mem_enabled(cs))
  667. continue;
  668. gpmc_cs_get_memconf(cs, &base, &size);
  669. if (gpmc_cs_insert_mem(cs, base, size)) {
  670. pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
  671. __func__, cs, base, base + size);
  672. gpmc_cs_disable_mem(cs);
  673. }
  674. }
  675. }
  676. static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
  677. {
  678. u32 temp;
  679. int div;
  680. div = gpmc_calc_divider(sync_clk);
  681. temp = gpmc_ps_to_ticks(time_ps);
  682. temp = (temp + div - 1) / div;
  683. return gpmc_ticks_to_ps(temp * div);
  684. }
  685. /* XXX: can the cycles be avoided ? */
  686. static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
  687. struct gpmc_device_timings *dev_t,
  688. bool mux)
  689. {
  690. u32 temp;
  691. /* adv_rd_off */
  692. temp = dev_t->t_avdp_r;
  693. /* XXX: mux check required ? */
  694. if (mux) {
  695. /* XXX: t_avdp not to be required for sync, only added for tusb
  696. * this indirectly necessitates requirement of t_avdp_r and
  697. * t_avdp_w instead of having a single t_avdp
  698. */
  699. temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
  700. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  701. }
  702. gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
  703. /* oe_on */
  704. temp = dev_t->t_oeasu; /* XXX: remove this ? */
  705. if (mux) {
  706. temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
  707. temp = max_t(u32, temp, gpmc_t->adv_rd_off +
  708. gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
  709. }
  710. gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
  711. /* access */
  712. /* XXX: any scope for improvement ?, by combining oe_on
  713. * and clk_activation, need to check whether
  714. * access = clk_activation + round to sync clk ?
  715. */
  716. temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
  717. temp += gpmc_t->clk_activation;
  718. if (dev_t->cyc_oe)
  719. temp = max_t(u32, temp, gpmc_t->oe_on +
  720. gpmc_ticks_to_ps(dev_t->cyc_oe));
  721. gpmc_t->access = gpmc_round_ps_to_ticks(temp);
  722. gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
  723. gpmc_t->cs_rd_off = gpmc_t->oe_off;
  724. /* rd_cycle */
  725. temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
  726. temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
  727. gpmc_t->access;
  728. /* XXX: barter t_ce_rdyz with t_cez_r ? */
  729. if (dev_t->t_ce_rdyz)
  730. temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
  731. gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
  732. return 0;
  733. }
  734. static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
  735. struct gpmc_device_timings *dev_t,
  736. bool mux)
  737. {
  738. u32 temp;
  739. /* adv_wr_off */
  740. temp = dev_t->t_avdp_w;
  741. if (mux) {
  742. temp = max_t(u32, temp,
  743. gpmc_t->clk_activation + dev_t->t_avdh);
  744. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  745. }
  746. gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
  747. /* wr_data_mux_bus */
  748. temp = max_t(u32, dev_t->t_weasu,
  749. gpmc_t->clk_activation + dev_t->t_rdyo);
  750. /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
  751. * and in that case remember to handle we_on properly
  752. */
  753. if (mux) {
  754. temp = max_t(u32, temp,
  755. gpmc_t->adv_wr_off + dev_t->t_aavdh);
  756. temp = max_t(u32, temp, gpmc_t->adv_wr_off +
  757. gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
  758. }
  759. gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
  760. /* we_on */
  761. if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
  762. gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
  763. else
  764. gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
  765. /* wr_access */
  766. /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
  767. gpmc_t->wr_access = gpmc_t->access;
  768. /* we_off */
  769. temp = gpmc_t->we_on + dev_t->t_wpl;
  770. temp = max_t(u32, temp,
  771. gpmc_t->wr_access + gpmc_ticks_to_ps(1));
  772. temp = max_t(u32, temp,
  773. gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
  774. gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
  775. gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
  776. dev_t->t_wph);
  777. /* wr_cycle */
  778. temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
  779. temp += gpmc_t->wr_access;
  780. /* XXX: barter t_ce_rdyz with t_cez_w ? */
  781. if (dev_t->t_ce_rdyz)
  782. temp = max_t(u32, temp,
  783. gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
  784. gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
  785. return 0;
  786. }
  787. static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
  788. struct gpmc_device_timings *dev_t,
  789. bool mux)
  790. {
  791. u32 temp;
  792. /* adv_rd_off */
  793. temp = dev_t->t_avdp_r;
  794. if (mux)
  795. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  796. gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
  797. /* oe_on */
  798. temp = dev_t->t_oeasu;
  799. if (mux)
  800. temp = max_t(u32, temp,
  801. gpmc_t->adv_rd_off + dev_t->t_aavdh);
  802. gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
  803. /* access */
  804. temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
  805. gpmc_t->oe_on + dev_t->t_oe);
  806. temp = max_t(u32, temp,
  807. gpmc_t->cs_on + dev_t->t_ce);
  808. temp = max_t(u32, temp,
  809. gpmc_t->adv_on + dev_t->t_aa);
  810. gpmc_t->access = gpmc_round_ps_to_ticks(temp);
  811. gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
  812. gpmc_t->cs_rd_off = gpmc_t->oe_off;
  813. /* rd_cycle */
  814. temp = max_t(u32, dev_t->t_rd_cycle,
  815. gpmc_t->cs_rd_off + dev_t->t_cez_r);
  816. temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
  817. gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
  818. return 0;
  819. }
  820. static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
  821. struct gpmc_device_timings *dev_t,
  822. bool mux)
  823. {
  824. u32 temp;
  825. /* adv_wr_off */
  826. temp = dev_t->t_avdp_w;
  827. if (mux)
  828. temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
  829. gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
  830. /* wr_data_mux_bus */
  831. temp = dev_t->t_weasu;
  832. if (mux) {
  833. temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
  834. temp = max_t(u32, temp, gpmc_t->adv_wr_off +
  835. gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
  836. }
  837. gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
  838. /* we_on */
  839. if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
  840. gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
  841. else
  842. gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
  843. /* we_off */
  844. temp = gpmc_t->we_on + dev_t->t_wpl;
  845. gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
  846. gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
  847. dev_t->t_wph);
  848. /* wr_cycle */
  849. temp = max_t(u32, dev_t->t_wr_cycle,
  850. gpmc_t->cs_wr_off + dev_t->t_cez_w);
  851. gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
  852. return 0;
  853. }
  854. static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
  855. struct gpmc_device_timings *dev_t)
  856. {
  857. u32 temp;
  858. gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
  859. gpmc_get_fclk_period();
  860. gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
  861. dev_t->t_bacc,
  862. gpmc_t->sync_clk);
  863. temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
  864. gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
  865. if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
  866. return 0;
  867. if (dev_t->ce_xdelay)
  868. gpmc_t->bool_timings.cs_extra_delay = true;
  869. if (dev_t->avd_xdelay)
  870. gpmc_t->bool_timings.adv_extra_delay = true;
  871. if (dev_t->oe_xdelay)
  872. gpmc_t->bool_timings.oe_extra_delay = true;
  873. if (dev_t->we_xdelay)
  874. gpmc_t->bool_timings.we_extra_delay = true;
  875. return 0;
  876. }
  877. static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
  878. struct gpmc_device_timings *dev_t,
  879. bool sync)
  880. {
  881. u32 temp;
  882. /* cs_on */
  883. gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
  884. /* adv_on */
  885. temp = dev_t->t_avdasu;
  886. if (dev_t->t_ce_avd)
  887. temp = max_t(u32, temp,
  888. gpmc_t->cs_on + dev_t->t_ce_avd);
  889. gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
  890. if (sync)
  891. gpmc_calc_sync_common_timings(gpmc_t, dev_t);
  892. return 0;
  893. }
  894. /* TODO: remove this function once all peripherals are confirmed to
  895. * work with generic timing. Simultaneously gpmc_cs_set_timings()
  896. * has to be modified to handle timings in ps instead of ns
  897. */
  898. static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
  899. {
  900. t->cs_on /= 1000;
  901. t->cs_rd_off /= 1000;
  902. t->cs_wr_off /= 1000;
  903. t->adv_on /= 1000;
  904. t->adv_rd_off /= 1000;
  905. t->adv_wr_off /= 1000;
  906. t->we_on /= 1000;
  907. t->we_off /= 1000;
  908. t->oe_on /= 1000;
  909. t->oe_off /= 1000;
  910. t->page_burst_access /= 1000;
  911. t->access /= 1000;
  912. t->rd_cycle /= 1000;
  913. t->wr_cycle /= 1000;
  914. t->bus_turnaround /= 1000;
  915. t->cycle2cycle_delay /= 1000;
  916. t->wait_monitoring /= 1000;
  917. t->clk_activation /= 1000;
  918. t->wr_access /= 1000;
  919. t->wr_data_mux_bus /= 1000;
  920. }
  921. int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
  922. struct gpmc_settings *gpmc_s,
  923. struct gpmc_device_timings *dev_t)
  924. {
  925. bool mux = false, sync = false;
  926. if (gpmc_s) {
  927. mux = gpmc_s->mux_add_data ? true : false;
  928. sync = (gpmc_s->sync_read || gpmc_s->sync_write);
  929. }
  930. memset(gpmc_t, 0, sizeof(*gpmc_t));
  931. gpmc_calc_common_timings(gpmc_t, dev_t, sync);
  932. if (gpmc_s && gpmc_s->sync_read)
  933. gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
  934. else
  935. gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
  936. if (gpmc_s && gpmc_s->sync_write)
  937. gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
  938. else
  939. gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
  940. /* TODO: remove, see function definition */
  941. gpmc_convert_ps_to_ns(gpmc_t);
  942. return 0;
  943. }
  944. /**
  945. * gpmc_cs_program_settings - programs non-timing related settings
  946. * @cs: GPMC chip-select to program
  947. * @p: pointer to GPMC settings structure
  948. *
  949. * Programs non-timing related settings for a GPMC chip-select, such as
  950. * bus-width, burst configuration, etc. Function should be called once
  951. * for each chip-select that is being used and must be called before
  952. * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
  953. * register will be initialised to zero by this function. Returns 0 on
  954. * success and appropriate negative error code on failure.
  955. */
  956. int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
  957. {
  958. u32 config1;
  959. if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
  960. pr_err("%s: invalid width %d!", __func__, p->device_width);
  961. return -EINVAL;
  962. }
  963. /* Address-data multiplexing not supported for NAND devices */
  964. if (p->device_nand && p->mux_add_data) {
  965. pr_err("%s: invalid configuration!\n", __func__);
  966. return -EINVAL;
  967. }
  968. if ((p->mux_add_data > GPMC_MUX_AD) ||
  969. ((p->mux_add_data == GPMC_MUX_AAD) &&
  970. !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
  971. pr_err("%s: invalid multiplex configuration!\n", __func__);
  972. return -EINVAL;
  973. }
  974. /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
  975. if (p->burst_read || p->burst_write) {
  976. switch (p->burst_len) {
  977. case GPMC_BURST_4:
  978. case GPMC_BURST_8:
  979. case GPMC_BURST_16:
  980. break;
  981. default:
  982. pr_err("%s: invalid page/burst-length (%d)\n",
  983. __func__, p->burst_len);
  984. return -EINVAL;
  985. }
  986. }
  987. if ((p->wait_on_read || p->wait_on_write) &&
  988. (p->wait_pin > gpmc_nr_waitpins)) {
  989. pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
  990. return -EINVAL;
  991. }
  992. config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
  993. if (p->sync_read)
  994. config1 |= GPMC_CONFIG1_READTYPE_SYNC;
  995. if (p->sync_write)
  996. config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
  997. if (p->wait_on_read)
  998. config1 |= GPMC_CONFIG1_WAIT_READ_MON;
  999. if (p->wait_on_write)
  1000. config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
  1001. if (p->wait_on_read || p->wait_on_write)
  1002. config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
  1003. if (p->device_nand)
  1004. config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
  1005. if (p->mux_add_data)
  1006. config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
  1007. if (p->burst_read)
  1008. config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
  1009. if (p->burst_write)
  1010. config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
  1011. if (p->burst_read || p->burst_write) {
  1012. config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
  1013. config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
  1014. }
  1015. gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
  1016. return 0;
  1017. }
  1018. #ifdef CONFIG_OF
  1019. static struct of_device_id gpmc_dt_ids[] = {
  1020. { .compatible = "ti,omap2420-gpmc" },
  1021. { .compatible = "ti,omap2430-gpmc" },
  1022. { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
  1023. { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
  1024. { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
  1025. { }
  1026. };
  1027. MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
  1028. /**
  1029. * gpmc_read_settings_dt - read gpmc settings from device-tree
  1030. * @np: pointer to device-tree node for a gpmc child device
  1031. * @p: pointer to gpmc settings structure
  1032. *
  1033. * Reads the GPMC settings for a GPMC child device from device-tree and
  1034. * stores them in the GPMC settings structure passed. The GPMC settings
  1035. * structure is initialised to zero by this function and so any
  1036. * previously stored settings will be cleared.
  1037. */
  1038. void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
  1039. {
  1040. memset(p, 0, sizeof(struct gpmc_settings));
  1041. p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
  1042. p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
  1043. p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
  1044. of_property_read_u32(np, "gpmc,device-width", &p->device_width);
  1045. of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
  1046. if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
  1047. p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
  1048. p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
  1049. p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
  1050. if (!p->burst_read && !p->burst_write)
  1051. pr_warn("%s: page/burst-length set but not used!\n",
  1052. __func__);
  1053. }
  1054. if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
  1055. p->wait_on_read = of_property_read_bool(np,
  1056. "gpmc,wait-on-read");
  1057. p->wait_on_write = of_property_read_bool(np,
  1058. "gpmc,wait-on-write");
  1059. if (!p->wait_on_read && !p->wait_on_write)
  1060. pr_warn("%s: read/write wait monitoring not enabled!\n",
  1061. __func__);
  1062. }
  1063. }
  1064. static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
  1065. struct gpmc_timings *gpmc_t)
  1066. {
  1067. struct gpmc_bool_timings *p;
  1068. if (!np || !gpmc_t)
  1069. return;
  1070. memset(gpmc_t, 0, sizeof(*gpmc_t));
  1071. /* minimum clock period for syncronous mode */
  1072. of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
  1073. /* chip select timtings */
  1074. of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
  1075. of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
  1076. of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
  1077. /* ADV signal timings */
  1078. of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
  1079. of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
  1080. of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
  1081. /* WE signal timings */
  1082. of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
  1083. of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
  1084. /* OE signal timings */
  1085. of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
  1086. of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
  1087. /* access and cycle timings */
  1088. of_property_read_u32(np, "gpmc,page-burst-access-ns",
  1089. &gpmc_t->page_burst_access);
  1090. of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
  1091. of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
  1092. of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
  1093. of_property_read_u32(np, "gpmc,bus-turnaround-ns",
  1094. &gpmc_t->bus_turnaround);
  1095. of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
  1096. &gpmc_t->cycle2cycle_delay);
  1097. of_property_read_u32(np, "gpmc,wait-monitoring-ns",
  1098. &gpmc_t->wait_monitoring);
  1099. of_property_read_u32(np, "gpmc,clk-activation-ns",
  1100. &gpmc_t->clk_activation);
  1101. /* only applicable to OMAP3+ */
  1102. of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
  1103. of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
  1104. &gpmc_t->wr_data_mux_bus);
  1105. /* bool timing parameters */
  1106. p = &gpmc_t->bool_timings;
  1107. p->cycle2cyclediffcsen =
  1108. of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
  1109. p->cycle2cyclesamecsen =
  1110. of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
  1111. p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
  1112. p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
  1113. p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
  1114. p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
  1115. p->time_para_granularity =
  1116. of_property_read_bool(np, "gpmc,time-para-granularity");
  1117. }
  1118. #ifdef CONFIG_MTD_NAND
  1119. static const char * const nand_ecc_opts[] = {
  1120. [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw",
  1121. [OMAP_ECC_HAMMING_CODE_HW] = "hw",
  1122. [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode",
  1123. [OMAP_ECC_BCH4_CODE_HW] = "bch4",
  1124. [OMAP_ECC_BCH8_CODE_HW] = "bch8",
  1125. };
  1126. static int gpmc_probe_nand_child(struct platform_device *pdev,
  1127. struct device_node *child)
  1128. {
  1129. u32 val;
  1130. const char *s;
  1131. struct gpmc_timings gpmc_t;
  1132. struct omap_nand_platform_data *gpmc_nand_data;
  1133. if (of_property_read_u32(child, "reg", &val) < 0) {
  1134. dev_err(&pdev->dev, "%s has no 'reg' property\n",
  1135. child->full_name);
  1136. return -ENODEV;
  1137. }
  1138. gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
  1139. GFP_KERNEL);
  1140. if (!gpmc_nand_data)
  1141. return -ENOMEM;
  1142. gpmc_nand_data->cs = val;
  1143. gpmc_nand_data->of_node = child;
  1144. if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
  1145. for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
  1146. if (!strcasecmp(s, nand_ecc_opts[val])) {
  1147. gpmc_nand_data->ecc_opt = val;
  1148. break;
  1149. }
  1150. val = of_get_nand_bus_width(child);
  1151. if (val == 16)
  1152. gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
  1153. gpmc_read_timings_dt(child, &gpmc_t);
  1154. gpmc_nand_init(gpmc_nand_data, &gpmc_t);
  1155. return 0;
  1156. }
  1157. #else
  1158. static int gpmc_probe_nand_child(struct platform_device *pdev,
  1159. struct device_node *child)
  1160. {
  1161. return 0;
  1162. }
  1163. #endif
  1164. #ifdef CONFIG_MTD_ONENAND
  1165. static int gpmc_probe_onenand_child(struct platform_device *pdev,
  1166. struct device_node *child)
  1167. {
  1168. u32 val;
  1169. struct omap_onenand_platform_data *gpmc_onenand_data;
  1170. if (of_property_read_u32(child, "reg", &val) < 0) {
  1171. dev_err(&pdev->dev, "%s has no 'reg' property\n",
  1172. child->full_name);
  1173. return -ENODEV;
  1174. }
  1175. gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
  1176. GFP_KERNEL);
  1177. if (!gpmc_onenand_data)
  1178. return -ENOMEM;
  1179. gpmc_onenand_data->cs = val;
  1180. gpmc_onenand_data->of_node = child;
  1181. gpmc_onenand_data->dma_channel = -1;
  1182. if (!of_property_read_u32(child, "dma-channel", &val))
  1183. gpmc_onenand_data->dma_channel = val;
  1184. gpmc_onenand_init(gpmc_onenand_data);
  1185. return 0;
  1186. }
  1187. #else
  1188. static int gpmc_probe_onenand_child(struct platform_device *pdev,
  1189. struct device_node *child)
  1190. {
  1191. return 0;
  1192. }
  1193. #endif
  1194. /**
  1195. * gpmc_probe_generic_child - configures the gpmc for a child device
  1196. * @pdev: pointer to gpmc platform device
  1197. * @child: pointer to device-tree node for child device
  1198. *
  1199. * Allocates and configures a GPMC chip-select for a child device.
  1200. * Returns 0 on success and appropriate negative error code on failure.
  1201. */
  1202. static int gpmc_probe_generic_child(struct platform_device *pdev,
  1203. struct device_node *child)
  1204. {
  1205. struct gpmc_settings gpmc_s;
  1206. struct gpmc_timings gpmc_t;
  1207. struct resource res;
  1208. unsigned long base;
  1209. int ret, cs;
  1210. if (of_property_read_u32(child, "reg", &cs) < 0) {
  1211. dev_err(&pdev->dev, "%s has no 'reg' property\n",
  1212. child->full_name);
  1213. return -ENODEV;
  1214. }
  1215. if (of_address_to_resource(child, 0, &res) < 0) {
  1216. dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
  1217. child->full_name);
  1218. return -ENODEV;
  1219. }
  1220. ret = gpmc_cs_request(cs, resource_size(&res), &base);
  1221. if (ret < 0) {
  1222. dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
  1223. return ret;
  1224. }
  1225. /*
  1226. * FIXME: gpmc_cs_request() will map the CS to an arbitary
  1227. * location in the gpmc address space. When booting with
  1228. * device-tree we want the NOR flash to be mapped to the
  1229. * location specified in the device-tree blob. So remap the
  1230. * CS to this location. Once DT migration is complete should
  1231. * just make gpmc_cs_request() map a specific address.
  1232. */
  1233. ret = gpmc_cs_remap(cs, res.start);
  1234. if (ret < 0) {
  1235. dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n",
  1236. cs, res.start);
  1237. goto err;
  1238. }
  1239. gpmc_read_settings_dt(child, &gpmc_s);
  1240. ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
  1241. if (ret < 0)
  1242. goto err;
  1243. ret = gpmc_cs_program_settings(cs, &gpmc_s);
  1244. if (ret < 0)
  1245. goto err;
  1246. gpmc_read_timings_dt(child, &gpmc_t);
  1247. gpmc_cs_set_timings(cs, &gpmc_t);
  1248. if (of_platform_device_create(child, NULL, &pdev->dev))
  1249. return 0;
  1250. dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
  1251. ret = -ENODEV;
  1252. err:
  1253. gpmc_cs_free(cs);
  1254. return ret;
  1255. }
  1256. static int gpmc_probe_dt(struct platform_device *pdev)
  1257. {
  1258. int ret;
  1259. struct device_node *child;
  1260. const struct of_device_id *of_id =
  1261. of_match_device(gpmc_dt_ids, &pdev->dev);
  1262. if (!of_id)
  1263. return 0;
  1264. ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
  1265. &gpmc_nr_waitpins);
  1266. if (ret < 0) {
  1267. pr_err("%s: number of wait pins not found!\n", __func__);
  1268. return ret;
  1269. }
  1270. for_each_child_of_node(pdev->dev.of_node, child) {
  1271. if (!child->name)
  1272. continue;
  1273. if (of_node_cmp(child->name, "nand") == 0)
  1274. ret = gpmc_probe_nand_child(pdev, child);
  1275. else if (of_node_cmp(child->name, "onenand") == 0)
  1276. ret = gpmc_probe_onenand_child(pdev, child);
  1277. else if (of_node_cmp(child->name, "ethernet") == 0 ||
  1278. of_node_cmp(child->name, "nor") == 0)
  1279. ret = gpmc_probe_generic_child(pdev, child);
  1280. if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
  1281. __func__, child->full_name))
  1282. of_node_put(child);
  1283. }
  1284. return 0;
  1285. }
  1286. #else
  1287. static int gpmc_probe_dt(struct platform_device *pdev)
  1288. {
  1289. return 0;
  1290. }
  1291. #endif
  1292. static int gpmc_probe(struct platform_device *pdev)
  1293. {
  1294. int rc;
  1295. u32 l;
  1296. struct resource *res;
  1297. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1298. if (res == NULL)
  1299. return -ENOENT;
  1300. phys_base = res->start;
  1301. mem_size = resource_size(res);
  1302. gpmc_base = devm_ioremap_resource(&pdev->dev, res);
  1303. if (IS_ERR(gpmc_base))
  1304. return PTR_ERR(gpmc_base);
  1305. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1306. if (res == NULL)
  1307. dev_warn(&pdev->dev, "Failed to get resource: irq\n");
  1308. else
  1309. gpmc_irq = res->start;
  1310. gpmc_l3_clk = clk_get(&pdev->dev, "fck");
  1311. if (IS_ERR(gpmc_l3_clk)) {
  1312. dev_err(&pdev->dev, "error: clk_get\n");
  1313. gpmc_irq = 0;
  1314. return PTR_ERR(gpmc_l3_clk);
  1315. }
  1316. clk_prepare_enable(gpmc_l3_clk);
  1317. gpmc_dev = &pdev->dev;
  1318. l = gpmc_read_reg(GPMC_REVISION);
  1319. /*
  1320. * FIXME: Once device-tree migration is complete the below flags
  1321. * should be populated based upon the device-tree compatible
  1322. * string. For now just use the IP revision. OMAP3+ devices have
  1323. * the wr_access and wr_data_mux_bus register fields. OMAP4+
  1324. * devices support the addr-addr-data multiplex protocol.
  1325. *
  1326. * GPMC IP revisions:
  1327. * - OMAP24xx = 2.0
  1328. * - OMAP3xxx = 5.0
  1329. * - OMAP44xx/54xx/AM335x = 6.0
  1330. */
  1331. if (GPMC_REVISION_MAJOR(l) > 0x4)
  1332. gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
  1333. if (GPMC_REVISION_MAJOR(l) > 0x5)
  1334. gpmc_capability |= GPMC_HAS_MUX_AAD;
  1335. dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
  1336. GPMC_REVISION_MINOR(l));
  1337. gpmc_mem_init();
  1338. if (gpmc_setup_irq() < 0)
  1339. dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
  1340. /* Now the GPMC is initialised, unreserve the chip-selects */
  1341. gpmc_cs_map = 0;
  1342. if (!pdev->dev.of_node)
  1343. gpmc_nr_waitpins = GPMC_NR_WAITPINS;
  1344. rc = gpmc_probe_dt(pdev);
  1345. if (rc < 0) {
  1346. clk_disable_unprepare(gpmc_l3_clk);
  1347. clk_put(gpmc_l3_clk);
  1348. dev_err(gpmc_dev, "failed to probe DT parameters\n");
  1349. return rc;
  1350. }
  1351. return 0;
  1352. }
  1353. static int gpmc_remove(struct platform_device *pdev)
  1354. {
  1355. gpmc_free_irq();
  1356. gpmc_mem_exit();
  1357. gpmc_dev = NULL;
  1358. return 0;
  1359. }
  1360. static struct platform_driver gpmc_driver = {
  1361. .probe = gpmc_probe,
  1362. .remove = gpmc_remove,
  1363. .driver = {
  1364. .name = DEVICE_NAME,
  1365. .owner = THIS_MODULE,
  1366. .of_match_table = of_match_ptr(gpmc_dt_ids),
  1367. },
  1368. };
  1369. static __init int gpmc_init(void)
  1370. {
  1371. return platform_driver_register(&gpmc_driver);
  1372. }
  1373. static __exit void gpmc_exit(void)
  1374. {
  1375. platform_driver_unregister(&gpmc_driver);
  1376. }
  1377. omap_postcore_initcall(gpmc_init);
  1378. module_exit(gpmc_exit);
  1379. static int __init omap_gpmc_init(void)
  1380. {
  1381. struct omap_hwmod *oh;
  1382. struct platform_device *pdev;
  1383. char *oh_name = "gpmc";
  1384. /*
  1385. * if the board boots up with a populated DT, do not
  1386. * manually add the device from this initcall
  1387. */
  1388. if (of_have_populated_dt())
  1389. return -ENODEV;
  1390. oh = omap_hwmod_lookup(oh_name);
  1391. if (!oh) {
  1392. pr_err("Could not look up %s\n", oh_name);
  1393. return -ENODEV;
  1394. }
  1395. pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
  1396. WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
  1397. return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
  1398. }
  1399. omap_postcore_initcall(omap_gpmc_init);
  1400. static irqreturn_t gpmc_handle_irq(int irq, void *dev)
  1401. {
  1402. int i;
  1403. u32 regval;
  1404. regval = gpmc_read_reg(GPMC_IRQSTATUS);
  1405. if (!regval)
  1406. return IRQ_NONE;
  1407. for (i = 0; i < GPMC_NR_IRQ; i++)
  1408. if (regval & gpmc_client_irq[i].bitmask)
  1409. generic_handle_irq(gpmc_client_irq[i].irq);
  1410. gpmc_write_reg(GPMC_IRQSTATUS, regval);
  1411. return IRQ_HANDLED;
  1412. }
  1413. #ifdef CONFIG_ARCH_OMAP3
  1414. static struct omap3_gpmc_regs gpmc_context;
  1415. void omap3_gpmc_save_context(void)
  1416. {
  1417. int i;
  1418. gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
  1419. gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
  1420. gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
  1421. gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
  1422. gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
  1423. gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
  1424. gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
  1425. for (i = 0; i < GPMC_CS_NUM; i++) {
  1426. gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
  1427. if (gpmc_context.cs_context[i].is_valid) {
  1428. gpmc_context.cs_context[i].config1 =
  1429. gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
  1430. gpmc_context.cs_context[i].config2 =
  1431. gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
  1432. gpmc_context.cs_context[i].config3 =
  1433. gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
  1434. gpmc_context.cs_context[i].config4 =
  1435. gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
  1436. gpmc_context.cs_context[i].config5 =
  1437. gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
  1438. gpmc_context.cs_context[i].config6 =
  1439. gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
  1440. gpmc_context.cs_context[i].config7 =
  1441. gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
  1442. }
  1443. }
  1444. }
  1445. void omap3_gpmc_restore_context(void)
  1446. {
  1447. int i;
  1448. gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
  1449. gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
  1450. gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
  1451. gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
  1452. gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
  1453. gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
  1454. gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
  1455. for (i = 0; i < GPMC_CS_NUM; i++) {
  1456. if (gpmc_context.cs_context[i].is_valid) {
  1457. gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
  1458. gpmc_context.cs_context[i].config1);
  1459. gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
  1460. gpmc_context.cs_context[i].config2);
  1461. gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
  1462. gpmc_context.cs_context[i].config3);
  1463. gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
  1464. gpmc_context.cs_context[i].config4);
  1465. gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
  1466. gpmc_context.cs_context[i].config5);
  1467. gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
  1468. gpmc_context.cs_context[i].config6);
  1469. gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
  1470. gpmc_context.cs_context[i].config7);
  1471. }
  1472. }
  1473. }
  1474. #endif /* CONFIG_ARCH_OMAP3 */