gpmc-nand.c 4.1 KB

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  1. /*
  2. * gpmc-nand.c
  3. *
  4. * Copyright (C) 2009 Texas Instruments
  5. * Vimal Singh <vimalsingh@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/io.h>
  14. #include <linux/mtd/nand.h>
  15. #include <linux/platform_data/mtd-nand-omap2.h>
  16. #include <asm/mach/flash.h>
  17. #include "gpmc.h"
  18. #include "soc.h"
  19. #include "gpmc-nand.h"
  20. /* minimum size for IO mapping */
  21. #define NAND_IO_SIZE 4
  22. static struct resource gpmc_nand_resource[] = {
  23. {
  24. .flags = IORESOURCE_MEM,
  25. },
  26. {
  27. .flags = IORESOURCE_IRQ,
  28. },
  29. {
  30. .flags = IORESOURCE_IRQ,
  31. },
  32. };
  33. static struct platform_device gpmc_nand_device = {
  34. .name = "omap2-nand",
  35. .id = 0,
  36. .num_resources = ARRAY_SIZE(gpmc_nand_resource),
  37. .resource = gpmc_nand_resource,
  38. };
  39. static int omap2_nand_gpmc_retime(
  40. struct omap_nand_platform_data *gpmc_nand_data,
  41. struct gpmc_timings *gpmc_t)
  42. {
  43. struct gpmc_timings t;
  44. int err;
  45. memset(&t, 0, sizeof(t));
  46. t.sync_clk = gpmc_t->sync_clk;
  47. t.cs_on = gpmc_t->cs_on;
  48. t.adv_on = gpmc_t->adv_on;
  49. /* Read */
  50. t.adv_rd_off = gpmc_t->adv_rd_off;
  51. t.oe_on = t.adv_on;
  52. t.access = gpmc_t->access;
  53. t.oe_off = gpmc_t->oe_off;
  54. t.cs_rd_off = gpmc_t->cs_rd_off;
  55. t.rd_cycle = gpmc_t->rd_cycle;
  56. /* Write */
  57. t.adv_wr_off = gpmc_t->adv_wr_off;
  58. t.we_on = t.oe_on;
  59. if (cpu_is_omap34xx()) {
  60. t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
  61. t.wr_access = gpmc_t->wr_access;
  62. }
  63. t.we_off = gpmc_t->we_off;
  64. t.cs_wr_off = gpmc_t->cs_wr_off;
  65. t.wr_cycle = gpmc_t->wr_cycle;
  66. err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
  67. if (err)
  68. return err;
  69. return 0;
  70. }
  71. static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
  72. {
  73. /* support only OMAP3 class */
  74. if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
  75. pr_err("BCH ecc is not supported on this CPU\n");
  76. return 0;
  77. }
  78. /*
  79. * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
  80. * and AM33xx derivates. Other chips may be added if confirmed to work.
  81. */
  82. if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
  83. (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
  84. (!soc_is_am33xx())) {
  85. pr_err("BCH 4-bit mode is not supported on this CPU\n");
  86. return 0;
  87. }
  88. return 1;
  89. }
  90. int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
  91. struct gpmc_timings *gpmc_t)
  92. {
  93. int err = 0;
  94. struct gpmc_settings s;
  95. struct device *dev = &gpmc_nand_device.dev;
  96. memset(&s, 0, sizeof(struct gpmc_settings));
  97. gpmc_nand_device.dev.platform_data = gpmc_nand_data;
  98. err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
  99. (unsigned long *)&gpmc_nand_resource[0].start);
  100. if (err < 0) {
  101. dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
  102. gpmc_nand_data->cs, err);
  103. return err;
  104. }
  105. gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
  106. NAND_IO_SIZE - 1;
  107. gpmc_nand_resource[1].start =
  108. gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
  109. gpmc_nand_resource[2].start =
  110. gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
  111. if (gpmc_t) {
  112. err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t);
  113. if (err < 0) {
  114. dev_err(dev, "Unable to set gpmc timings: %d\n", err);
  115. return err;
  116. }
  117. if (gpmc_nand_data->of_node) {
  118. gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
  119. } else {
  120. s.device_nand = true;
  121. /* Enable RD PIN Monitoring Reg */
  122. if (gpmc_nand_data->dev_ready) {
  123. s.wait_on_read = true;
  124. s.wait_on_write = true;
  125. }
  126. }
  127. if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
  128. s.device_width = GPMC_DEVWIDTH_16BIT;
  129. else
  130. s.device_width = GPMC_DEVWIDTH_8BIT;
  131. err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
  132. if (err < 0)
  133. goto out_free_cs;
  134. err = gpmc_configure(GPMC_CONFIG_WP, 0);
  135. if (err < 0)
  136. goto out_free_cs;
  137. }
  138. gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
  139. if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
  140. return -EINVAL;
  141. err = platform_device_register(&gpmc_nand_device);
  142. if (err < 0) {
  143. dev_err(dev, "Unable to register NAND device\n");
  144. goto out_free_cs;
  145. }
  146. return 0;
  147. out_free_cs:
  148. gpmc_cs_free(gpmc_nand_data->cs);
  149. return err;
  150. }