cclock3xxx_data.c 101 KB

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  1. /*
  2. * OMAP3 clock data
  3. *
  4. * Copyright (C) 2007-2012 Texas Instruments, Inc.
  5. * Copyright (C) 2007-2011 Nokia Corporation
  6. *
  7. * Written by Paul Walmsley
  8. * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
  9. * With many device clock fixes by Kevin Hilman and Jouni Högander
  10. * DPLL bypass clock support added by Roman Tereshonkov
  11. *
  12. */
  13. /*
  14. * Virtual clocks are introduced as convenient tools.
  15. * They are sources for other clocks and not supposed
  16. * to be requested from drivers directly.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/clk.h>
  20. #include <linux/clk-private.h>
  21. #include <linux/list.h>
  22. #include <linux/io.h>
  23. #include "soc.h"
  24. #include "iomap.h"
  25. #include "clock.h"
  26. #include "clock3xxx.h"
  27. #include "clock34xx.h"
  28. #include "clock36xx.h"
  29. #include "clock3517.h"
  30. #include "cm3xxx.h"
  31. #include "cm-regbits-34xx.h"
  32. #include "prm3xxx.h"
  33. #include "prm-regbits-34xx.h"
  34. #include "control.h"
  35. /*
  36. * clocks
  37. */
  38. #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
  39. /* Maximum DPLL multiplier, divider values for OMAP3 */
  40. #define OMAP3_MAX_DPLL_MULT 2047
  41. #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
  42. #define OMAP3_MAX_DPLL_DIV 128
  43. DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
  44. DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
  45. DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
  46. DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
  47. DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
  48. DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
  49. DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
  50. DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
  51. DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
  52. DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
  53. DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
  54. DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
  55. DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
  56. static const char *osc_sys_ck_parent_names[] = {
  57. "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
  58. "virt_38_4m_ck", "virt_16_8m_ck",
  59. };
  60. DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
  61. OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
  62. OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
  63. DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
  64. OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
  65. OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
  66. static struct dpll_data dpll3_dd = {
  67. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  68. .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
  69. .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
  70. .clk_bypass = &sys_ck,
  71. .clk_ref = &sys_ck,
  72. .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
  73. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  74. .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
  75. .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
  76. .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
  77. .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
  78. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  79. .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
  80. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  81. .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
  82. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  83. .min_divider = 1,
  84. .max_divider = OMAP3_MAX_DPLL_DIV,
  85. };
  86. static struct clk dpll3_ck;
  87. static const char *dpll3_ck_parent_names[] = {
  88. "sys_ck",
  89. };
  90. static const struct clk_ops dpll3_ck_ops = {
  91. .init = &omap2_init_clk_clkdm,
  92. .get_parent = &omap2_init_dpll_parent,
  93. .recalc_rate = &omap3_dpll_recalc,
  94. .round_rate = &omap2_dpll_round_rate,
  95. };
  96. static struct clk_hw_omap dpll3_ck_hw = {
  97. .hw = {
  98. .clk = &dpll3_ck,
  99. },
  100. .ops = &clkhwops_omap3_dpll,
  101. .dpll_data = &dpll3_dd,
  102. .clkdm_name = "dpll3_clkdm",
  103. };
  104. DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
  105. DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
  106. OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  107. OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
  108. OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
  109. CLK_DIVIDER_ONE_BASED, NULL);
  110. static struct clk core_ck;
  111. static const char *core_ck_parent_names[] = {
  112. "dpll3_m2_ck",
  113. };
  114. static const struct clk_ops core_ck_ops = {};
  115. DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
  116. DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
  117. DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
  118. OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  119. OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
  120. CLK_DIVIDER_ONE_BASED, NULL);
  121. DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
  122. OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  123. OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
  124. CLK_DIVIDER_ONE_BASED, NULL);
  125. static struct clk security_l4_ick2;
  126. static const char *security_l4_ick2_parent_names[] = {
  127. "l4_ick",
  128. };
  129. DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
  130. DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
  131. static struct clk aes1_ick;
  132. static const char *aes1_ick_parent_names[] = {
  133. "security_l4_ick2",
  134. };
  135. static const struct clk_ops aes1_ick_ops = {
  136. .enable = &omap2_dflt_clk_enable,
  137. .disable = &omap2_dflt_clk_disable,
  138. .is_enabled = &omap2_dflt_clk_is_enabled,
  139. };
  140. static struct clk_hw_omap aes1_ick_hw = {
  141. .hw = {
  142. .clk = &aes1_ick,
  143. },
  144. .ops = &clkhwops_iclk_wait,
  145. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  146. .enable_bit = OMAP3430_EN_AES1_SHIFT,
  147. };
  148. DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
  149. static struct clk core_l4_ick;
  150. static const struct clk_ops core_l4_ick_ops = {
  151. .init = &omap2_init_clk_clkdm,
  152. };
  153. DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
  154. DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
  155. static struct clk aes2_ick;
  156. static const char *aes2_ick_parent_names[] = {
  157. "core_l4_ick",
  158. };
  159. static const struct clk_ops aes2_ick_ops = {
  160. .init = &omap2_init_clk_clkdm,
  161. .enable = &omap2_dflt_clk_enable,
  162. .disable = &omap2_dflt_clk_disable,
  163. .is_enabled = &omap2_dflt_clk_is_enabled,
  164. };
  165. static struct clk_hw_omap aes2_ick_hw = {
  166. .hw = {
  167. .clk = &aes2_ick,
  168. },
  169. .ops = &clkhwops_iclk_wait,
  170. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  171. .enable_bit = OMAP3430_EN_AES2_SHIFT,
  172. .clkdm_name = "core_l4_clkdm",
  173. };
  174. DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
  175. static struct clk dpll1_fck;
  176. static struct dpll_data dpll1_dd = {
  177. .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
  178. .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
  179. .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
  180. .clk_bypass = &dpll1_fck,
  181. .clk_ref = &sys_ck,
  182. .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
  183. .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
  184. .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
  185. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  186. .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
  187. .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
  188. .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
  189. .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
  190. .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
  191. .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
  192. .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
  193. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  194. .min_divider = 1,
  195. .max_divider = OMAP3_MAX_DPLL_DIV,
  196. };
  197. static struct clk dpll1_ck;
  198. static const struct clk_ops dpll1_ck_ops = {
  199. .init = &omap2_init_clk_clkdm,
  200. .enable = &omap3_noncore_dpll_enable,
  201. .disable = &omap3_noncore_dpll_disable,
  202. .get_parent = &omap2_init_dpll_parent,
  203. .recalc_rate = &omap3_dpll_recalc,
  204. .set_rate = &omap3_noncore_dpll_set_rate,
  205. .round_rate = &omap2_dpll_round_rate,
  206. };
  207. static struct clk_hw_omap dpll1_ck_hw = {
  208. .hw = {
  209. .clk = &dpll1_ck,
  210. },
  211. .ops = &clkhwops_omap3_dpll,
  212. .dpll_data = &dpll1_dd,
  213. .clkdm_name = "dpll1_clkdm",
  214. };
  215. DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
  216. DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
  217. DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
  218. OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
  219. OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
  220. OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
  221. CLK_DIVIDER_ONE_BASED, NULL);
  222. static struct clk mpu_ck;
  223. static const char *mpu_ck_parent_names[] = {
  224. "dpll1_x2m2_ck",
  225. };
  226. DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
  227. DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
  228. DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
  229. OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
  230. OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
  231. 0x0, NULL);
  232. static struct clk cam_ick;
  233. static struct clk_hw_omap cam_ick_hw = {
  234. .hw = {
  235. .clk = &cam_ick,
  236. },
  237. .ops = &clkhwops_iclk,
  238. .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
  239. .enable_bit = OMAP3430_EN_CAM_SHIFT,
  240. .clkdm_name = "cam_clkdm",
  241. };
  242. DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
  243. /* DPLL4 */
  244. /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
  245. /* Type: DPLL */
  246. static struct dpll_data dpll4_dd;
  247. static struct dpll_data dpll4_dd_34xx __initdata = {
  248. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
  249. .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
  250. .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
  251. .clk_bypass = &sys_ck,
  252. .clk_ref = &sys_ck,
  253. .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
  254. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  255. .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
  256. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  257. .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
  258. .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
  259. .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
  260. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  261. .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
  262. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  263. .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
  264. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  265. .min_divider = 1,
  266. .max_divider = OMAP3_MAX_DPLL_DIV,
  267. };
  268. static struct dpll_data dpll4_dd_3630 __initdata = {
  269. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
  270. .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
  271. .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
  272. .clk_bypass = &sys_ck,
  273. .clk_ref = &sys_ck,
  274. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  275. .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
  276. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  277. .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
  278. .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
  279. .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
  280. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  281. .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
  282. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  283. .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
  284. .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
  285. .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
  286. .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
  287. .min_divider = 1,
  288. .max_divider = OMAP3_MAX_DPLL_DIV,
  289. .flags = DPLL_J_TYPE
  290. };
  291. static struct clk dpll4_ck;
  292. static const struct clk_ops dpll4_ck_ops = {
  293. .init = &omap2_init_clk_clkdm,
  294. .enable = &omap3_noncore_dpll_enable,
  295. .disable = &omap3_noncore_dpll_disable,
  296. .get_parent = &omap2_init_dpll_parent,
  297. .recalc_rate = &omap3_dpll_recalc,
  298. .set_rate = &omap3_dpll4_set_rate,
  299. .round_rate = &omap2_dpll_round_rate,
  300. };
  301. static struct clk_hw_omap dpll4_ck_hw = {
  302. .hw = {
  303. .clk = &dpll4_ck,
  304. },
  305. .dpll_data = &dpll4_dd,
  306. .ops = &clkhwops_omap3_dpll,
  307. .clkdm_name = "dpll4_clkdm",
  308. };
  309. DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
  310. DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
  311. OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
  312. OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
  313. CLK_DIVIDER_ONE_BASED, NULL);
  314. static struct clk dpll4_m5x2_ck;
  315. static const char *dpll4_m5x2_ck_parent_names[] = {
  316. "dpll4_m5_ck",
  317. };
  318. static const struct clk_ops dpll4_m5x2_ck_ops = {
  319. .init = &omap2_init_clk_clkdm,
  320. .enable = &omap2_dflt_clk_enable,
  321. .disable = &omap2_dflt_clk_disable,
  322. .is_enabled = &omap2_dflt_clk_is_enabled,
  323. .recalc_rate = &omap3_clkoutx2_recalc,
  324. };
  325. static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
  326. .init = &omap2_init_clk_clkdm,
  327. .enable = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
  328. .disable = &omap2_dflt_clk_disable,
  329. .recalc_rate = &omap3_clkoutx2_recalc,
  330. };
  331. static struct clk_hw_omap dpll4_m5x2_ck_hw = {
  332. .hw = {
  333. .clk = &dpll4_m5x2_ck,
  334. },
  335. .ops = &clkhwops_wait,
  336. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  337. .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
  338. .flags = INVERT_ENABLE,
  339. .clkdm_name = "dpll4_clkdm",
  340. };
  341. DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops);
  342. static struct clk dpll4_m5x2_ck_3630 = {
  343. .name = "dpll4_m5x2_ck",
  344. .hw = &dpll4_m5x2_ck_hw.hw,
  345. .parent_names = dpll4_m5x2_ck_parent_names,
  346. .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
  347. .ops = &dpll4_m5x2_ck_3630_ops,
  348. .flags = CLK_SET_RATE_PARENT,
  349. };
  350. static struct clk cam_mclk;
  351. static const char *cam_mclk_parent_names[] = {
  352. "dpll4_m5x2_ck",
  353. };
  354. static struct clk_hw_omap cam_mclk_hw = {
  355. .hw = {
  356. .clk = &cam_mclk,
  357. },
  358. .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
  359. .enable_bit = OMAP3430_EN_CAM_SHIFT,
  360. .clkdm_name = "cam_clkdm",
  361. };
  362. static struct clk cam_mclk = {
  363. .name = "cam_mclk",
  364. .hw = &cam_mclk_hw.hw,
  365. .parent_names = cam_mclk_parent_names,
  366. .num_parents = ARRAY_SIZE(cam_mclk_parent_names),
  367. .ops = &aes2_ick_ops,
  368. .flags = CLK_SET_RATE_PARENT,
  369. };
  370. static const struct clksel_rate clkout2_src_core_rates[] = {
  371. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  372. { .div = 0 }
  373. };
  374. static const struct clksel_rate clkout2_src_sys_rates[] = {
  375. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  376. { .div = 0 }
  377. };
  378. static const struct clksel_rate clkout2_src_96m_rates[] = {
  379. { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
  380. { .div = 0 }
  381. };
  382. DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
  383. OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
  384. OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
  385. CLK_DIVIDER_ONE_BASED, NULL);
  386. static struct clk dpll4_m2x2_ck;
  387. static const char *dpll4_m2x2_ck_parent_names[] = {
  388. "dpll4_m2_ck",
  389. };
  390. static struct clk_hw_omap dpll4_m2x2_ck_hw = {
  391. .hw = {
  392. .clk = &dpll4_m2x2_ck,
  393. },
  394. .ops = &clkhwops_wait,
  395. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  396. .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
  397. .flags = INVERT_ENABLE,
  398. .clkdm_name = "dpll4_clkdm",
  399. };
  400. DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
  401. static struct clk dpll4_m2x2_ck_3630 = {
  402. .name = "dpll4_m2x2_ck",
  403. .hw = &dpll4_m2x2_ck_hw.hw,
  404. .parent_names = dpll4_m2x2_ck_parent_names,
  405. .num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
  406. .ops = &dpll4_m5x2_ck_3630_ops,
  407. };
  408. static struct clk omap_96m_alwon_fck;
  409. static const char *omap_96m_alwon_fck_parent_names[] = {
  410. "dpll4_m2x2_ck",
  411. };
  412. DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
  413. DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
  414. core_ck_ops);
  415. static struct clk cm_96m_fck;
  416. static const char *cm_96m_fck_parent_names[] = {
  417. "omap_96m_alwon_fck",
  418. };
  419. DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
  420. DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
  421. static const struct clksel_rate clkout2_src_54m_rates[] = {
  422. { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
  423. { .div = 0 }
  424. };
  425. DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
  426. OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
  427. OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
  428. CLK_DIVIDER_ONE_BASED, NULL);
  429. static struct clk dpll4_m3x2_ck;
  430. static const char *dpll4_m3x2_ck_parent_names[] = {
  431. "dpll4_m3_ck",
  432. };
  433. static struct clk_hw_omap dpll4_m3x2_ck_hw = {
  434. .hw = {
  435. .clk = &dpll4_m3x2_ck,
  436. },
  437. .ops = &clkhwops_wait,
  438. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  439. .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
  440. .flags = INVERT_ENABLE,
  441. .clkdm_name = "dpll4_clkdm",
  442. };
  443. DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
  444. static struct clk dpll4_m3x2_ck_3630 = {
  445. .name = "dpll4_m3x2_ck",
  446. .hw = &dpll4_m3x2_ck_hw.hw,
  447. .parent_names = dpll4_m3x2_ck_parent_names,
  448. .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
  449. .ops = &dpll4_m5x2_ck_3630_ops,
  450. };
  451. static const char *omap_54m_fck_parent_names[] = {
  452. "dpll4_m3x2_ck", "sys_altclk",
  453. };
  454. DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
  455. OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
  456. OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
  457. static const struct clksel clkout2_src_clksel[] = {
  458. { .parent = &core_ck, .rates = clkout2_src_core_rates },
  459. { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
  460. { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
  461. { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
  462. { .parent = NULL },
  463. };
  464. static const char *clkout2_src_ck_parent_names[] = {
  465. "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
  466. };
  467. static const struct clk_ops clkout2_src_ck_ops = {
  468. .init = &omap2_init_clk_clkdm,
  469. .enable = &omap2_dflt_clk_enable,
  470. .disable = &omap2_dflt_clk_disable,
  471. .is_enabled = &omap2_dflt_clk_is_enabled,
  472. .recalc_rate = &omap2_clksel_recalc,
  473. .get_parent = &omap2_clksel_find_parent_index,
  474. .set_parent = &omap2_clksel_set_parent,
  475. };
  476. DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
  477. clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
  478. OMAP3430_CLKOUT2SOURCE_MASK,
  479. OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
  480. NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
  481. static const struct clksel_rate omap_48m_cm96m_rates[] = {
  482. { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
  483. { .div = 0 }
  484. };
  485. static const struct clksel_rate omap_48m_alt_rates[] = {
  486. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  487. { .div = 0 }
  488. };
  489. static const struct clksel omap_48m_clksel[] = {
  490. { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
  491. { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
  492. { .parent = NULL },
  493. };
  494. static const char *omap_48m_fck_parent_names[] = {
  495. "cm_96m_fck", "sys_altclk",
  496. };
  497. static struct clk omap_48m_fck;
  498. static const struct clk_ops omap_48m_fck_ops = {
  499. .recalc_rate = &omap2_clksel_recalc,
  500. .get_parent = &omap2_clksel_find_parent_index,
  501. .set_parent = &omap2_clksel_set_parent,
  502. };
  503. static struct clk_hw_omap omap_48m_fck_hw = {
  504. .hw = {
  505. .clk = &omap_48m_fck,
  506. },
  507. .clksel = omap_48m_clksel,
  508. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  509. .clksel_mask = OMAP3430_SOURCE_48M_MASK,
  510. };
  511. DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
  512. DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
  513. static struct clk core_12m_fck;
  514. static const char *core_12m_fck_parent_names[] = {
  515. "omap_12m_fck",
  516. };
  517. DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
  518. DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
  519. static struct clk core_48m_fck;
  520. static const char *core_48m_fck_parent_names[] = {
  521. "omap_48m_fck",
  522. };
  523. DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
  524. DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
  525. static const char *omap_96m_fck_parent_names[] = {
  526. "cm_96m_fck", "sys_ck",
  527. };
  528. DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
  529. OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  530. OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
  531. static struct clk core_96m_fck;
  532. static const char *core_96m_fck_parent_names[] = {
  533. "omap_96m_fck",
  534. };
  535. DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
  536. DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
  537. static struct clk core_l3_ick;
  538. static const char *core_l3_ick_parent_names[] = {
  539. "l3_ick",
  540. };
  541. DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
  542. DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
  543. DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
  544. static struct clk corex2_fck;
  545. static const char *corex2_fck_parent_names[] = {
  546. "dpll3_m2x2_ck",
  547. };
  548. DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
  549. DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
  550. static struct clk cpefuse_fck;
  551. static struct clk_hw_omap cpefuse_fck_hw = {
  552. .hw = {
  553. .clk = &cpefuse_fck,
  554. },
  555. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  556. .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
  557. .clkdm_name = "core_l4_clkdm",
  558. };
  559. DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
  560. static struct clk csi2_96m_fck;
  561. static const char *csi2_96m_fck_parent_names[] = {
  562. "core_96m_fck",
  563. };
  564. static struct clk_hw_omap csi2_96m_fck_hw = {
  565. .hw = {
  566. .clk = &csi2_96m_fck,
  567. },
  568. .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
  569. .enable_bit = OMAP3430_EN_CSI2_SHIFT,
  570. .clkdm_name = "cam_clkdm",
  571. };
  572. DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
  573. static struct clk d2d_26m_fck;
  574. static struct clk_hw_omap d2d_26m_fck_hw = {
  575. .hw = {
  576. .clk = &d2d_26m_fck,
  577. },
  578. .ops = &clkhwops_wait,
  579. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  580. .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
  581. .clkdm_name = "d2d_clkdm",
  582. };
  583. DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
  584. static struct clk des1_ick;
  585. static struct clk_hw_omap des1_ick_hw = {
  586. .hw = {
  587. .clk = &des1_ick,
  588. },
  589. .ops = &clkhwops_iclk_wait,
  590. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  591. .enable_bit = OMAP3430_EN_DES1_SHIFT,
  592. };
  593. DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
  594. static struct clk des2_ick;
  595. static struct clk_hw_omap des2_ick_hw = {
  596. .hw = {
  597. .clk = &des2_ick,
  598. },
  599. .ops = &clkhwops_iclk_wait,
  600. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  601. .enable_bit = OMAP3430_EN_DES2_SHIFT,
  602. .clkdm_name = "core_l4_clkdm",
  603. };
  604. DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
  605. DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
  606. OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
  607. OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
  608. CLK_DIVIDER_ONE_BASED, NULL);
  609. static struct clk dpll2_fck;
  610. static struct dpll_data dpll2_dd = {
  611. .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
  612. .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
  613. .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
  614. .clk_bypass = &dpll2_fck,
  615. .clk_ref = &sys_ck,
  616. .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
  617. .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
  618. .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
  619. .modes = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
  620. (1 << DPLL_LOW_POWER_BYPASS)),
  621. .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
  622. .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
  623. .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
  624. .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
  625. .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
  626. .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
  627. .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
  628. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  629. .min_divider = 1,
  630. .max_divider = OMAP3_MAX_DPLL_DIV,
  631. };
  632. static struct clk dpll2_ck;
  633. static struct clk_hw_omap dpll2_ck_hw = {
  634. .hw = {
  635. .clk = &dpll2_ck,
  636. },
  637. .ops = &clkhwops_omap3_dpll,
  638. .dpll_data = &dpll2_dd,
  639. .clkdm_name = "dpll2_clkdm",
  640. };
  641. DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
  642. DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
  643. OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
  644. OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
  645. CLK_DIVIDER_ONE_BASED, NULL);
  646. DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
  647. OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
  648. OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
  649. OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
  650. CLK_DIVIDER_ONE_BASED, NULL);
  651. DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
  652. OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  653. OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
  654. CLK_DIVIDER_ONE_BASED, NULL);
  655. static struct clk dpll3_m3x2_ck;
  656. static const char *dpll3_m3x2_ck_parent_names[] = {
  657. "dpll3_m3_ck",
  658. };
  659. static struct clk_hw_omap dpll3_m3x2_ck_hw = {
  660. .hw = {
  661. .clk = &dpll3_m3x2_ck,
  662. },
  663. .ops = &clkhwops_wait,
  664. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  665. .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
  666. .flags = INVERT_ENABLE,
  667. .clkdm_name = "dpll3_clkdm",
  668. };
  669. DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
  670. static struct clk dpll3_m3x2_ck_3630 = {
  671. .name = "dpll3_m3x2_ck",
  672. .hw = &dpll3_m3x2_ck_hw.hw,
  673. .parent_names = dpll3_m3x2_ck_parent_names,
  674. .num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
  675. .ops = &dpll4_m5x2_ck_3630_ops,
  676. };
  677. DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
  678. DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
  679. OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
  680. OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
  681. CLK_DIVIDER_ONE_BASED, NULL);
  682. static struct clk dpll4_m4x2_ck;
  683. static const char *dpll4_m4x2_ck_parent_names[] = {
  684. "dpll4_m4_ck",
  685. };
  686. static struct clk_hw_omap dpll4_m4x2_ck_hw = {
  687. .hw = {
  688. .clk = &dpll4_m4x2_ck,
  689. },
  690. .ops = &clkhwops_wait,
  691. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  692. .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
  693. .flags = INVERT_ENABLE,
  694. .clkdm_name = "dpll4_clkdm",
  695. };
  696. DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops);
  697. static struct clk dpll4_m4x2_ck_3630 = {
  698. .name = "dpll4_m4x2_ck",
  699. .hw = &dpll4_m4x2_ck_hw.hw,
  700. .parent_names = dpll4_m4x2_ck_parent_names,
  701. .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
  702. .ops = &dpll4_m5x2_ck_3630_ops,
  703. };
  704. DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
  705. OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  706. OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
  707. CLK_DIVIDER_ONE_BASED, NULL);
  708. static struct clk dpll4_m6x2_ck;
  709. static const char *dpll4_m6x2_ck_parent_names[] = {
  710. "dpll4_m6_ck",
  711. };
  712. static struct clk_hw_omap dpll4_m6x2_ck_hw = {
  713. .hw = {
  714. .clk = &dpll4_m6x2_ck,
  715. },
  716. .ops = &clkhwops_wait,
  717. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  718. .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
  719. .flags = INVERT_ENABLE,
  720. .clkdm_name = "dpll4_clkdm",
  721. };
  722. DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
  723. static struct clk dpll4_m6x2_ck_3630 = {
  724. .name = "dpll4_m6x2_ck",
  725. .hw = &dpll4_m6x2_ck_hw.hw,
  726. .parent_names = dpll4_m6x2_ck_parent_names,
  727. .num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
  728. .ops = &dpll4_m5x2_ck_3630_ops,
  729. };
  730. DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
  731. static struct dpll_data dpll5_dd = {
  732. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
  733. .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
  734. .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
  735. .clk_bypass = &sys_ck,
  736. .clk_ref = &sys_ck,
  737. .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
  738. .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
  739. .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
  740. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  741. .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
  742. .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
  743. .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
  744. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
  745. .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
  746. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
  747. .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
  748. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  749. .min_divider = 1,
  750. .max_divider = OMAP3_MAX_DPLL_DIV,
  751. };
  752. static struct clk dpll5_ck;
  753. static struct clk_hw_omap dpll5_ck_hw = {
  754. .hw = {
  755. .clk = &dpll5_ck,
  756. },
  757. .ops = &clkhwops_omap3_dpll,
  758. .dpll_data = &dpll5_dd,
  759. .clkdm_name = "dpll5_clkdm",
  760. };
  761. DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
  762. DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
  763. OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
  764. OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
  765. CLK_DIVIDER_ONE_BASED, NULL);
  766. static struct clk dss1_alwon_fck_3430es1;
  767. static const char *dss1_alwon_fck_3430es1_parent_names[] = {
  768. "dpll4_m4x2_ck",
  769. };
  770. static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
  771. .hw = {
  772. .clk = &dss1_alwon_fck_3430es1,
  773. },
  774. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  775. .enable_bit = OMAP3430_EN_DSS1_SHIFT,
  776. .clkdm_name = "dss_clkdm",
  777. };
  778. DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names,
  779. aes2_ick_ops);
  780. static struct clk dss1_alwon_fck_3430es2;
  781. static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
  782. .hw = {
  783. .clk = &dss1_alwon_fck_3430es2,
  784. },
  785. .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
  786. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  787. .enable_bit = OMAP3430_EN_DSS1_SHIFT,
  788. .clkdm_name = "dss_clkdm",
  789. };
  790. DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names,
  791. aes2_ick_ops);
  792. static struct clk dss2_alwon_fck;
  793. static struct clk_hw_omap dss2_alwon_fck_hw = {
  794. .hw = {
  795. .clk = &dss2_alwon_fck,
  796. },
  797. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  798. .enable_bit = OMAP3430_EN_DSS2_SHIFT,
  799. .clkdm_name = "dss_clkdm",
  800. };
  801. DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
  802. static struct clk dss_96m_fck;
  803. static struct clk_hw_omap dss_96m_fck_hw = {
  804. .hw = {
  805. .clk = &dss_96m_fck,
  806. },
  807. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  808. .enable_bit = OMAP3430_EN_TV_SHIFT,
  809. .clkdm_name = "dss_clkdm",
  810. };
  811. DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
  812. static struct clk dss_ick_3430es1;
  813. static struct clk_hw_omap dss_ick_3430es1_hw = {
  814. .hw = {
  815. .clk = &dss_ick_3430es1,
  816. },
  817. .ops = &clkhwops_iclk,
  818. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
  819. .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
  820. .clkdm_name = "dss_clkdm",
  821. };
  822. DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
  823. static struct clk dss_ick_3430es2;
  824. static struct clk_hw_omap dss_ick_3430es2_hw = {
  825. .hw = {
  826. .clk = &dss_ick_3430es2,
  827. },
  828. .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
  829. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
  830. .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
  831. .clkdm_name = "dss_clkdm",
  832. };
  833. DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
  834. static struct clk dss_tv_fck;
  835. static const char *dss_tv_fck_parent_names[] = {
  836. "omap_54m_fck",
  837. };
  838. static struct clk_hw_omap dss_tv_fck_hw = {
  839. .hw = {
  840. .clk = &dss_tv_fck,
  841. },
  842. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  843. .enable_bit = OMAP3430_EN_TV_SHIFT,
  844. .clkdm_name = "dss_clkdm",
  845. };
  846. DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
  847. static struct clk emac_fck;
  848. static const char *emac_fck_parent_names[] = {
  849. "rmii_ck",
  850. };
  851. static struct clk_hw_omap emac_fck_hw = {
  852. .hw = {
  853. .clk = &emac_fck,
  854. },
  855. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  856. .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
  857. };
  858. DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
  859. static struct clk ipss_ick;
  860. static const char *ipss_ick_parent_names[] = {
  861. "core_l3_ick",
  862. };
  863. static struct clk_hw_omap ipss_ick_hw = {
  864. .hw = {
  865. .clk = &ipss_ick,
  866. },
  867. .ops = &clkhwops_am35xx_ipss_wait,
  868. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  869. .enable_bit = AM35XX_EN_IPSS_SHIFT,
  870. .clkdm_name = "core_l3_clkdm",
  871. };
  872. DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
  873. static struct clk emac_ick;
  874. static const char *emac_ick_parent_names[] = {
  875. "ipss_ick",
  876. };
  877. static struct clk_hw_omap emac_ick_hw = {
  878. .hw = {
  879. .clk = &emac_ick,
  880. },
  881. .ops = &clkhwops_am35xx_ipss_module_wait,
  882. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  883. .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
  884. .clkdm_name = "core_l3_clkdm",
  885. };
  886. DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
  887. static struct clk emu_core_alwon_ck;
  888. static const char *emu_core_alwon_ck_parent_names[] = {
  889. "dpll3_m3x2_ck",
  890. };
  891. DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
  892. DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
  893. core_l4_ick_ops);
  894. static struct clk emu_mpu_alwon_ck;
  895. static const char *emu_mpu_alwon_ck_parent_names[] = {
  896. "mpu_ck",
  897. };
  898. DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
  899. DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
  900. static struct clk emu_per_alwon_ck;
  901. static const char *emu_per_alwon_ck_parent_names[] = {
  902. "dpll4_m6x2_ck",
  903. };
  904. DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
  905. DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
  906. core_l4_ick_ops);
  907. static const char *emu_src_ck_parent_names[] = {
  908. "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
  909. };
  910. static const struct clksel_rate emu_src_sys_rates[] = {
  911. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  912. { .div = 0 },
  913. };
  914. static const struct clksel_rate emu_src_core_rates[] = {
  915. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  916. { .div = 0 },
  917. };
  918. static const struct clksel_rate emu_src_per_rates[] = {
  919. { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
  920. { .div = 0 },
  921. };
  922. static const struct clksel_rate emu_src_mpu_rates[] = {
  923. { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
  924. { .div = 0 },
  925. };
  926. static const struct clksel emu_src_clksel[] = {
  927. { .parent = &sys_ck, .rates = emu_src_sys_rates },
  928. { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
  929. { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
  930. { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
  931. { .parent = NULL },
  932. };
  933. static const struct clk_ops emu_src_ck_ops = {
  934. .init = &omap2_init_clk_clkdm,
  935. .recalc_rate = &omap2_clksel_recalc,
  936. .get_parent = &omap2_clksel_find_parent_index,
  937. .set_parent = &omap2_clksel_set_parent,
  938. .enable = &omap2_clkops_enable_clkdm,
  939. .disable = &omap2_clkops_disable_clkdm,
  940. };
  941. static struct clk emu_src_ck;
  942. static struct clk_hw_omap emu_src_ck_hw = {
  943. .hw = {
  944. .clk = &emu_src_ck,
  945. },
  946. .clksel = emu_src_clksel,
  947. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  948. .clksel_mask = OMAP3430_MUX_CTRL_MASK,
  949. .clkdm_name = "emu_clkdm",
  950. };
  951. DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
  952. DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
  953. OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  954. OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
  955. CLK_DIVIDER_ONE_BASED, NULL);
  956. static struct clk fac_ick;
  957. static struct clk_hw_omap fac_ick_hw = {
  958. .hw = {
  959. .clk = &fac_ick,
  960. },
  961. .ops = &clkhwops_iclk_wait,
  962. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  963. .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
  964. .clkdm_name = "core_l4_clkdm",
  965. };
  966. DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
  967. static struct clk fshostusb_fck;
  968. static const char *fshostusb_fck_parent_names[] = {
  969. "core_48m_fck",
  970. };
  971. static struct clk_hw_omap fshostusb_fck_hw = {
  972. .hw = {
  973. .clk = &fshostusb_fck,
  974. },
  975. .ops = &clkhwops_wait,
  976. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  977. .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
  978. .clkdm_name = "core_l4_clkdm",
  979. };
  980. DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
  981. static struct clk gfx_l3_ck;
  982. static struct clk_hw_omap gfx_l3_ck_hw = {
  983. .hw = {
  984. .clk = &gfx_l3_ck,
  985. },
  986. .ops = &clkhwops_wait,
  987. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
  988. .enable_bit = OMAP_EN_GFX_SHIFT,
  989. .clkdm_name = "gfx_3430es1_clkdm",
  990. };
  991. DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
  992. DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
  993. OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
  994. OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
  995. CLK_DIVIDER_ONE_BASED, NULL);
  996. static struct clk gfx_cg1_ck;
  997. static const char *gfx_cg1_ck_parent_names[] = {
  998. "gfx_l3_fck",
  999. };
  1000. static struct clk_hw_omap gfx_cg1_ck_hw = {
  1001. .hw = {
  1002. .clk = &gfx_cg1_ck,
  1003. },
  1004. .ops = &clkhwops_wait,
  1005. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
  1006. .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
  1007. .clkdm_name = "gfx_3430es1_clkdm",
  1008. };
  1009. DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
  1010. static struct clk gfx_cg2_ck;
  1011. static struct clk_hw_omap gfx_cg2_ck_hw = {
  1012. .hw = {
  1013. .clk = &gfx_cg2_ck,
  1014. },
  1015. .ops = &clkhwops_wait,
  1016. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
  1017. .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
  1018. .clkdm_name = "gfx_3430es1_clkdm",
  1019. };
  1020. DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
  1021. static struct clk gfx_l3_ick;
  1022. static const char *gfx_l3_ick_parent_names[] = {
  1023. "gfx_l3_ck",
  1024. };
  1025. DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
  1026. DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
  1027. static struct clk wkup_32k_fck;
  1028. static const char *wkup_32k_fck_parent_names[] = {
  1029. "omap_32k_fck",
  1030. };
  1031. DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
  1032. DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
  1033. static struct clk gpio1_dbck;
  1034. static const char *gpio1_dbck_parent_names[] = {
  1035. "wkup_32k_fck",
  1036. };
  1037. static struct clk_hw_omap gpio1_dbck_hw = {
  1038. .hw = {
  1039. .clk = &gpio1_dbck,
  1040. },
  1041. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  1042. .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
  1043. .clkdm_name = "wkup_clkdm",
  1044. };
  1045. DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
  1046. static struct clk wkup_l4_ick;
  1047. DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
  1048. DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
  1049. static struct clk gpio1_ick;
  1050. static const char *gpio1_ick_parent_names[] = {
  1051. "wkup_l4_ick",
  1052. };
  1053. static struct clk_hw_omap gpio1_ick_hw = {
  1054. .hw = {
  1055. .clk = &gpio1_ick,
  1056. },
  1057. .ops = &clkhwops_iclk_wait,
  1058. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  1059. .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
  1060. .clkdm_name = "wkup_clkdm",
  1061. };
  1062. DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
  1063. static struct clk per_32k_alwon_fck;
  1064. DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
  1065. DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
  1066. core_l4_ick_ops);
  1067. static struct clk gpio2_dbck;
  1068. static const char *gpio2_dbck_parent_names[] = {
  1069. "per_32k_alwon_fck",
  1070. };
  1071. static struct clk_hw_omap gpio2_dbck_hw = {
  1072. .hw = {
  1073. .clk = &gpio2_dbck,
  1074. },
  1075. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1076. .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
  1077. .clkdm_name = "per_clkdm",
  1078. };
  1079. DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
  1080. static struct clk per_l4_ick;
  1081. DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
  1082. DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
  1083. static struct clk gpio2_ick;
  1084. static const char *gpio2_ick_parent_names[] = {
  1085. "per_l4_ick",
  1086. };
  1087. static struct clk_hw_omap gpio2_ick_hw = {
  1088. .hw = {
  1089. .clk = &gpio2_ick,
  1090. },
  1091. .ops = &clkhwops_iclk_wait,
  1092. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1093. .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
  1094. .clkdm_name = "per_clkdm",
  1095. };
  1096. DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1097. static struct clk gpio3_dbck;
  1098. static struct clk_hw_omap gpio3_dbck_hw = {
  1099. .hw = {
  1100. .clk = &gpio3_dbck,
  1101. },
  1102. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1103. .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
  1104. .clkdm_name = "per_clkdm",
  1105. };
  1106. DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
  1107. static struct clk gpio3_ick;
  1108. static struct clk_hw_omap gpio3_ick_hw = {
  1109. .hw = {
  1110. .clk = &gpio3_ick,
  1111. },
  1112. .ops = &clkhwops_iclk_wait,
  1113. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1114. .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
  1115. .clkdm_name = "per_clkdm",
  1116. };
  1117. DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1118. static struct clk gpio4_dbck;
  1119. static struct clk_hw_omap gpio4_dbck_hw = {
  1120. .hw = {
  1121. .clk = &gpio4_dbck,
  1122. },
  1123. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1124. .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
  1125. .clkdm_name = "per_clkdm",
  1126. };
  1127. DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
  1128. static struct clk gpio4_ick;
  1129. static struct clk_hw_omap gpio4_ick_hw = {
  1130. .hw = {
  1131. .clk = &gpio4_ick,
  1132. },
  1133. .ops = &clkhwops_iclk_wait,
  1134. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1135. .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
  1136. .clkdm_name = "per_clkdm",
  1137. };
  1138. DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1139. static struct clk gpio5_dbck;
  1140. static struct clk_hw_omap gpio5_dbck_hw = {
  1141. .hw = {
  1142. .clk = &gpio5_dbck,
  1143. },
  1144. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1145. .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
  1146. .clkdm_name = "per_clkdm",
  1147. };
  1148. DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
  1149. static struct clk gpio5_ick;
  1150. static struct clk_hw_omap gpio5_ick_hw = {
  1151. .hw = {
  1152. .clk = &gpio5_ick,
  1153. },
  1154. .ops = &clkhwops_iclk_wait,
  1155. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1156. .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
  1157. .clkdm_name = "per_clkdm",
  1158. };
  1159. DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1160. static struct clk gpio6_dbck;
  1161. static struct clk_hw_omap gpio6_dbck_hw = {
  1162. .hw = {
  1163. .clk = &gpio6_dbck,
  1164. },
  1165. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1166. .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
  1167. .clkdm_name = "per_clkdm",
  1168. };
  1169. DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
  1170. static struct clk gpio6_ick;
  1171. static struct clk_hw_omap gpio6_ick_hw = {
  1172. .hw = {
  1173. .clk = &gpio6_ick,
  1174. },
  1175. .ops = &clkhwops_iclk_wait,
  1176. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1177. .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
  1178. .clkdm_name = "per_clkdm",
  1179. };
  1180. DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1181. static struct clk gpmc_fck;
  1182. static struct clk_hw_omap gpmc_fck_hw = {
  1183. .hw = {
  1184. .clk = &gpmc_fck,
  1185. },
  1186. .flags = ENABLE_ON_INIT,
  1187. .clkdm_name = "core_l3_clkdm",
  1188. };
  1189. DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
  1190. static const struct clksel omap343x_gpt_clksel[] = {
  1191. { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
  1192. { .parent = &sys_ck, .rates = gpt_sys_rates },
  1193. { .parent = NULL },
  1194. };
  1195. static const char *gpt10_fck_parent_names[] = {
  1196. "omap_32k_fck", "sys_ck",
  1197. };
  1198. DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
  1199. OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1200. OMAP3430_CLKSEL_GPT10_MASK,
  1201. OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1202. OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
  1203. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1204. static struct clk gpt10_ick;
  1205. static struct clk_hw_omap gpt10_ick_hw = {
  1206. .hw = {
  1207. .clk = &gpt10_ick,
  1208. },
  1209. .ops = &clkhwops_iclk_wait,
  1210. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1211. .enable_bit = OMAP3430_EN_GPT10_SHIFT,
  1212. .clkdm_name = "core_l4_clkdm",
  1213. };
  1214. DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
  1215. DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
  1216. OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1217. OMAP3430_CLKSEL_GPT11_MASK,
  1218. OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1219. OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
  1220. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1221. static struct clk gpt11_ick;
  1222. static struct clk_hw_omap gpt11_ick_hw = {
  1223. .hw = {
  1224. .clk = &gpt11_ick,
  1225. },
  1226. .ops = &clkhwops_iclk_wait,
  1227. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1228. .enable_bit = OMAP3430_EN_GPT11_SHIFT,
  1229. .clkdm_name = "core_l4_clkdm",
  1230. };
  1231. DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
  1232. static struct clk gpt12_fck;
  1233. static const char *gpt12_fck_parent_names[] = {
  1234. "secure_32k_fck",
  1235. };
  1236. DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
  1237. DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
  1238. static struct clk gpt12_ick;
  1239. static struct clk_hw_omap gpt12_ick_hw = {
  1240. .hw = {
  1241. .clk = &gpt12_ick,
  1242. },
  1243. .ops = &clkhwops_iclk_wait,
  1244. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  1245. .enable_bit = OMAP3430_EN_GPT12_SHIFT,
  1246. .clkdm_name = "wkup_clkdm",
  1247. };
  1248. DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
  1249. DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
  1250. OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
  1251. OMAP3430_CLKSEL_GPT1_MASK,
  1252. OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  1253. OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
  1254. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1255. static struct clk gpt1_ick;
  1256. static struct clk_hw_omap gpt1_ick_hw = {
  1257. .hw = {
  1258. .clk = &gpt1_ick,
  1259. },
  1260. .ops = &clkhwops_iclk_wait,
  1261. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  1262. .enable_bit = OMAP3430_EN_GPT1_SHIFT,
  1263. .clkdm_name = "wkup_clkdm",
  1264. };
  1265. DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
  1266. DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
  1267. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  1268. OMAP3430_CLKSEL_GPT2_MASK,
  1269. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1270. OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
  1271. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1272. static struct clk gpt2_ick;
  1273. static struct clk_hw_omap gpt2_ick_hw = {
  1274. .hw = {
  1275. .clk = &gpt2_ick,
  1276. },
  1277. .ops = &clkhwops_iclk_wait,
  1278. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1279. .enable_bit = OMAP3430_EN_GPT2_SHIFT,
  1280. .clkdm_name = "per_clkdm",
  1281. };
  1282. DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1283. DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
  1284. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  1285. OMAP3430_CLKSEL_GPT3_MASK,
  1286. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1287. OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
  1288. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1289. static struct clk gpt3_ick;
  1290. static struct clk_hw_omap gpt3_ick_hw = {
  1291. .hw = {
  1292. .clk = &gpt3_ick,
  1293. },
  1294. .ops = &clkhwops_iclk_wait,
  1295. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1296. .enable_bit = OMAP3430_EN_GPT3_SHIFT,
  1297. .clkdm_name = "per_clkdm",
  1298. };
  1299. DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1300. DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
  1301. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  1302. OMAP3430_CLKSEL_GPT4_MASK,
  1303. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1304. OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
  1305. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1306. static struct clk gpt4_ick;
  1307. static struct clk_hw_omap gpt4_ick_hw = {
  1308. .hw = {
  1309. .clk = &gpt4_ick,
  1310. },
  1311. .ops = &clkhwops_iclk_wait,
  1312. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1313. .enable_bit = OMAP3430_EN_GPT4_SHIFT,
  1314. .clkdm_name = "per_clkdm",
  1315. };
  1316. DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1317. DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
  1318. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  1319. OMAP3430_CLKSEL_GPT5_MASK,
  1320. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1321. OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
  1322. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1323. static struct clk gpt5_ick;
  1324. static struct clk_hw_omap gpt5_ick_hw = {
  1325. .hw = {
  1326. .clk = &gpt5_ick,
  1327. },
  1328. .ops = &clkhwops_iclk_wait,
  1329. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1330. .enable_bit = OMAP3430_EN_GPT5_SHIFT,
  1331. .clkdm_name = "per_clkdm",
  1332. };
  1333. DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1334. DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
  1335. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  1336. OMAP3430_CLKSEL_GPT6_MASK,
  1337. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1338. OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
  1339. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1340. static struct clk gpt6_ick;
  1341. static struct clk_hw_omap gpt6_ick_hw = {
  1342. .hw = {
  1343. .clk = &gpt6_ick,
  1344. },
  1345. .ops = &clkhwops_iclk_wait,
  1346. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1347. .enable_bit = OMAP3430_EN_GPT6_SHIFT,
  1348. .clkdm_name = "per_clkdm",
  1349. };
  1350. DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1351. DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
  1352. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  1353. OMAP3430_CLKSEL_GPT7_MASK,
  1354. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1355. OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
  1356. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1357. static struct clk gpt7_ick;
  1358. static struct clk_hw_omap gpt7_ick_hw = {
  1359. .hw = {
  1360. .clk = &gpt7_ick,
  1361. },
  1362. .ops = &clkhwops_iclk_wait,
  1363. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1364. .enable_bit = OMAP3430_EN_GPT7_SHIFT,
  1365. .clkdm_name = "per_clkdm",
  1366. };
  1367. DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1368. DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
  1369. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  1370. OMAP3430_CLKSEL_GPT8_MASK,
  1371. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1372. OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
  1373. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1374. static struct clk gpt8_ick;
  1375. static struct clk_hw_omap gpt8_ick_hw = {
  1376. .hw = {
  1377. .clk = &gpt8_ick,
  1378. },
  1379. .ops = &clkhwops_iclk_wait,
  1380. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1381. .enable_bit = OMAP3430_EN_GPT8_SHIFT,
  1382. .clkdm_name = "per_clkdm",
  1383. };
  1384. DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1385. DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
  1386. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  1387. OMAP3430_CLKSEL_GPT9_MASK,
  1388. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1389. OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
  1390. gpt10_fck_parent_names, clkout2_src_ck_ops);
  1391. static struct clk gpt9_ick;
  1392. static struct clk_hw_omap gpt9_ick_hw = {
  1393. .hw = {
  1394. .clk = &gpt9_ick,
  1395. },
  1396. .ops = &clkhwops_iclk_wait,
  1397. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1398. .enable_bit = OMAP3430_EN_GPT9_SHIFT,
  1399. .clkdm_name = "per_clkdm",
  1400. };
  1401. DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1402. static struct clk hdq_fck;
  1403. static const char *hdq_fck_parent_names[] = {
  1404. "core_12m_fck",
  1405. };
  1406. static struct clk_hw_omap hdq_fck_hw = {
  1407. .hw = {
  1408. .clk = &hdq_fck,
  1409. },
  1410. .ops = &clkhwops_wait,
  1411. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1412. .enable_bit = OMAP3430_EN_HDQ_SHIFT,
  1413. .clkdm_name = "core_l4_clkdm",
  1414. };
  1415. DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
  1416. static struct clk hdq_ick;
  1417. static struct clk_hw_omap hdq_ick_hw = {
  1418. .hw = {
  1419. .clk = &hdq_ick,
  1420. },
  1421. .ops = &clkhwops_iclk_wait,
  1422. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1423. .enable_bit = OMAP3430_EN_HDQ_SHIFT,
  1424. .clkdm_name = "core_l4_clkdm",
  1425. };
  1426. DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
  1427. static struct clk hecc_ck;
  1428. static struct clk_hw_omap hecc_ck_hw = {
  1429. .hw = {
  1430. .clk = &hecc_ck,
  1431. },
  1432. .ops = &clkhwops_am35xx_ipss_module_wait,
  1433. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  1434. .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
  1435. .clkdm_name = "core_l3_clkdm",
  1436. };
  1437. DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
  1438. static struct clk hsotgusb_fck_am35xx;
  1439. static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
  1440. .hw = {
  1441. .clk = &hsotgusb_fck_am35xx,
  1442. },
  1443. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  1444. .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
  1445. .clkdm_name = "core_l3_clkdm",
  1446. };
  1447. DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
  1448. static struct clk hsotgusb_ick_3430es1;
  1449. static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
  1450. .hw = {
  1451. .clk = &hsotgusb_ick_3430es1,
  1452. },
  1453. .ops = &clkhwops_iclk,
  1454. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1455. .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
  1456. .clkdm_name = "core_l3_clkdm",
  1457. };
  1458. DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
  1459. static struct clk hsotgusb_ick_3430es2;
  1460. static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
  1461. .hw = {
  1462. .clk = &hsotgusb_ick_3430es2,
  1463. },
  1464. .ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
  1465. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1466. .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
  1467. .clkdm_name = "core_l3_clkdm",
  1468. };
  1469. DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
  1470. static struct clk hsotgusb_ick_am35xx;
  1471. static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
  1472. .hw = {
  1473. .clk = &hsotgusb_ick_am35xx,
  1474. },
  1475. .ops = &clkhwops_am35xx_ipss_module_wait,
  1476. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  1477. .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
  1478. .clkdm_name = "core_l3_clkdm",
  1479. };
  1480. DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
  1481. static struct clk i2c1_fck;
  1482. static struct clk_hw_omap i2c1_fck_hw = {
  1483. .hw = {
  1484. .clk = &i2c1_fck,
  1485. },
  1486. .ops = &clkhwops_wait,
  1487. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1488. .enable_bit = OMAP3430_EN_I2C1_SHIFT,
  1489. .clkdm_name = "core_l4_clkdm",
  1490. };
  1491. DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
  1492. static struct clk i2c1_ick;
  1493. static struct clk_hw_omap i2c1_ick_hw = {
  1494. .hw = {
  1495. .clk = &i2c1_ick,
  1496. },
  1497. .ops = &clkhwops_iclk_wait,
  1498. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1499. .enable_bit = OMAP3430_EN_I2C1_SHIFT,
  1500. .clkdm_name = "core_l4_clkdm",
  1501. };
  1502. DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
  1503. static struct clk i2c2_fck;
  1504. static struct clk_hw_omap i2c2_fck_hw = {
  1505. .hw = {
  1506. .clk = &i2c2_fck,
  1507. },
  1508. .ops = &clkhwops_wait,
  1509. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1510. .enable_bit = OMAP3430_EN_I2C2_SHIFT,
  1511. .clkdm_name = "core_l4_clkdm",
  1512. };
  1513. DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
  1514. static struct clk i2c2_ick;
  1515. static struct clk_hw_omap i2c2_ick_hw = {
  1516. .hw = {
  1517. .clk = &i2c2_ick,
  1518. },
  1519. .ops = &clkhwops_iclk_wait,
  1520. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1521. .enable_bit = OMAP3430_EN_I2C2_SHIFT,
  1522. .clkdm_name = "core_l4_clkdm",
  1523. };
  1524. DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
  1525. static struct clk i2c3_fck;
  1526. static struct clk_hw_omap i2c3_fck_hw = {
  1527. .hw = {
  1528. .clk = &i2c3_fck,
  1529. },
  1530. .ops = &clkhwops_wait,
  1531. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1532. .enable_bit = OMAP3430_EN_I2C3_SHIFT,
  1533. .clkdm_name = "core_l4_clkdm",
  1534. };
  1535. DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
  1536. static struct clk i2c3_ick;
  1537. static struct clk_hw_omap i2c3_ick_hw = {
  1538. .hw = {
  1539. .clk = &i2c3_ick,
  1540. },
  1541. .ops = &clkhwops_iclk_wait,
  1542. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1543. .enable_bit = OMAP3430_EN_I2C3_SHIFT,
  1544. .clkdm_name = "core_l4_clkdm",
  1545. };
  1546. DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
  1547. static struct clk icr_ick;
  1548. static struct clk_hw_omap icr_ick_hw = {
  1549. .hw = {
  1550. .clk = &icr_ick,
  1551. },
  1552. .ops = &clkhwops_iclk_wait,
  1553. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1554. .enable_bit = OMAP3430_EN_ICR_SHIFT,
  1555. .clkdm_name = "core_l4_clkdm",
  1556. };
  1557. DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
  1558. static struct clk iva2_ck;
  1559. static const char *iva2_ck_parent_names[] = {
  1560. "dpll2_m2_ck",
  1561. };
  1562. static struct clk_hw_omap iva2_ck_hw = {
  1563. .hw = {
  1564. .clk = &iva2_ck,
  1565. },
  1566. .ops = &clkhwops_wait,
  1567. .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
  1568. .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
  1569. .clkdm_name = "iva2_clkdm",
  1570. };
  1571. DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
  1572. static struct clk mad2d_ick;
  1573. static struct clk_hw_omap mad2d_ick_hw = {
  1574. .hw = {
  1575. .clk = &mad2d_ick,
  1576. },
  1577. .ops = &clkhwops_iclk_wait,
  1578. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
  1579. .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
  1580. .clkdm_name = "d2d_clkdm",
  1581. };
  1582. DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
  1583. static struct clk mailboxes_ick;
  1584. static struct clk_hw_omap mailboxes_ick_hw = {
  1585. .hw = {
  1586. .clk = &mailboxes_ick,
  1587. },
  1588. .ops = &clkhwops_iclk_wait,
  1589. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1590. .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
  1591. .clkdm_name = "core_l4_clkdm",
  1592. };
  1593. DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
  1594. static const struct clksel_rate common_mcbsp_96m_rates[] = {
  1595. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  1596. { .div = 0 }
  1597. };
  1598. static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
  1599. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  1600. { .div = 0 }
  1601. };
  1602. static const struct clksel mcbsp_15_clksel[] = {
  1603. { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
  1604. { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
  1605. { .parent = NULL },
  1606. };
  1607. static const char *mcbsp1_fck_parent_names[] = {
  1608. "core_96m_fck", "mcbsp_clks",
  1609. };
  1610. DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
  1611. OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
  1612. OMAP2_MCBSP1_CLKS_MASK,
  1613. OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1614. OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
  1615. mcbsp1_fck_parent_names, clkout2_src_ck_ops);
  1616. static struct clk mcbsp1_ick;
  1617. static struct clk_hw_omap mcbsp1_ick_hw = {
  1618. .hw = {
  1619. .clk = &mcbsp1_ick,
  1620. },
  1621. .ops = &clkhwops_iclk_wait,
  1622. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1623. .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
  1624. .clkdm_name = "core_l4_clkdm",
  1625. };
  1626. DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
  1627. static struct clk per_96m_fck;
  1628. DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
  1629. DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
  1630. static const struct clksel mcbsp_234_clksel[] = {
  1631. { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
  1632. { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
  1633. { .parent = NULL },
  1634. };
  1635. static const char *mcbsp2_fck_parent_names[] = {
  1636. "per_96m_fck", "mcbsp_clks",
  1637. };
  1638. DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
  1639. OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
  1640. OMAP2_MCBSP2_CLKS_MASK,
  1641. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1642. OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
  1643. mcbsp2_fck_parent_names, clkout2_src_ck_ops);
  1644. static struct clk mcbsp2_ick;
  1645. static struct clk_hw_omap mcbsp2_ick_hw = {
  1646. .hw = {
  1647. .clk = &mcbsp2_ick,
  1648. },
  1649. .ops = &clkhwops_iclk_wait,
  1650. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1651. .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
  1652. .clkdm_name = "per_clkdm",
  1653. };
  1654. DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1655. DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
  1656. OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
  1657. OMAP2_MCBSP3_CLKS_MASK,
  1658. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1659. OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
  1660. mcbsp2_fck_parent_names, clkout2_src_ck_ops);
  1661. static struct clk mcbsp3_ick;
  1662. static struct clk_hw_omap mcbsp3_ick_hw = {
  1663. .hw = {
  1664. .clk = &mcbsp3_ick,
  1665. },
  1666. .ops = &clkhwops_iclk_wait,
  1667. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1668. .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
  1669. .clkdm_name = "per_clkdm",
  1670. };
  1671. DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1672. DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
  1673. OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
  1674. OMAP2_MCBSP4_CLKS_MASK,
  1675. OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  1676. OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
  1677. mcbsp2_fck_parent_names, clkout2_src_ck_ops);
  1678. static struct clk mcbsp4_ick;
  1679. static struct clk_hw_omap mcbsp4_ick_hw = {
  1680. .hw = {
  1681. .clk = &mcbsp4_ick,
  1682. },
  1683. .ops = &clkhwops_iclk_wait,
  1684. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  1685. .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
  1686. .clkdm_name = "per_clkdm",
  1687. };
  1688. DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
  1689. DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
  1690. OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
  1691. OMAP2_MCBSP5_CLKS_MASK,
  1692. OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1693. OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
  1694. mcbsp1_fck_parent_names, clkout2_src_ck_ops);
  1695. static struct clk mcbsp5_ick;
  1696. static struct clk_hw_omap mcbsp5_ick_hw = {
  1697. .hw = {
  1698. .clk = &mcbsp5_ick,
  1699. },
  1700. .ops = &clkhwops_iclk_wait,
  1701. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1702. .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
  1703. .clkdm_name = "core_l4_clkdm",
  1704. };
  1705. DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
  1706. static struct clk mcspi1_fck;
  1707. static struct clk_hw_omap mcspi1_fck_hw = {
  1708. .hw = {
  1709. .clk = &mcspi1_fck,
  1710. },
  1711. .ops = &clkhwops_wait,
  1712. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1713. .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
  1714. .clkdm_name = "core_l4_clkdm",
  1715. };
  1716. DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
  1717. static struct clk mcspi1_ick;
  1718. static struct clk_hw_omap mcspi1_ick_hw = {
  1719. .hw = {
  1720. .clk = &mcspi1_ick,
  1721. },
  1722. .ops = &clkhwops_iclk_wait,
  1723. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1724. .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
  1725. .clkdm_name = "core_l4_clkdm",
  1726. };
  1727. DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
  1728. static struct clk mcspi2_fck;
  1729. static struct clk_hw_omap mcspi2_fck_hw = {
  1730. .hw = {
  1731. .clk = &mcspi2_fck,
  1732. },
  1733. .ops = &clkhwops_wait,
  1734. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1735. .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
  1736. .clkdm_name = "core_l4_clkdm",
  1737. };
  1738. DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
  1739. static struct clk mcspi2_ick;
  1740. static struct clk_hw_omap mcspi2_ick_hw = {
  1741. .hw = {
  1742. .clk = &mcspi2_ick,
  1743. },
  1744. .ops = &clkhwops_iclk_wait,
  1745. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1746. .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
  1747. .clkdm_name = "core_l4_clkdm",
  1748. };
  1749. DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
  1750. static struct clk mcspi3_fck;
  1751. static struct clk_hw_omap mcspi3_fck_hw = {
  1752. .hw = {
  1753. .clk = &mcspi3_fck,
  1754. },
  1755. .ops = &clkhwops_wait,
  1756. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1757. .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
  1758. .clkdm_name = "core_l4_clkdm",
  1759. };
  1760. DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
  1761. static struct clk mcspi3_ick;
  1762. static struct clk_hw_omap mcspi3_ick_hw = {
  1763. .hw = {
  1764. .clk = &mcspi3_ick,
  1765. },
  1766. .ops = &clkhwops_iclk_wait,
  1767. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1768. .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
  1769. .clkdm_name = "core_l4_clkdm",
  1770. };
  1771. DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
  1772. static struct clk mcspi4_fck;
  1773. static struct clk_hw_omap mcspi4_fck_hw = {
  1774. .hw = {
  1775. .clk = &mcspi4_fck,
  1776. },
  1777. .ops = &clkhwops_wait,
  1778. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1779. .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
  1780. .clkdm_name = "core_l4_clkdm",
  1781. };
  1782. DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
  1783. static struct clk mcspi4_ick;
  1784. static struct clk_hw_omap mcspi4_ick_hw = {
  1785. .hw = {
  1786. .clk = &mcspi4_ick,
  1787. },
  1788. .ops = &clkhwops_iclk_wait,
  1789. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1790. .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
  1791. .clkdm_name = "core_l4_clkdm",
  1792. };
  1793. DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
  1794. static struct clk mmchs1_fck;
  1795. static struct clk_hw_omap mmchs1_fck_hw = {
  1796. .hw = {
  1797. .clk = &mmchs1_fck,
  1798. },
  1799. .ops = &clkhwops_wait,
  1800. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1801. .enable_bit = OMAP3430_EN_MMC1_SHIFT,
  1802. .clkdm_name = "core_l4_clkdm",
  1803. };
  1804. DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
  1805. static struct clk mmchs1_ick;
  1806. static struct clk_hw_omap mmchs1_ick_hw = {
  1807. .hw = {
  1808. .clk = &mmchs1_ick,
  1809. },
  1810. .ops = &clkhwops_iclk_wait,
  1811. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1812. .enable_bit = OMAP3430_EN_MMC1_SHIFT,
  1813. .clkdm_name = "core_l4_clkdm",
  1814. };
  1815. DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
  1816. static struct clk mmchs2_fck;
  1817. static struct clk_hw_omap mmchs2_fck_hw = {
  1818. .hw = {
  1819. .clk = &mmchs2_fck,
  1820. },
  1821. .ops = &clkhwops_wait,
  1822. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1823. .enable_bit = OMAP3430_EN_MMC2_SHIFT,
  1824. .clkdm_name = "core_l4_clkdm",
  1825. };
  1826. DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
  1827. static struct clk mmchs2_ick;
  1828. static struct clk_hw_omap mmchs2_ick_hw = {
  1829. .hw = {
  1830. .clk = &mmchs2_ick,
  1831. },
  1832. .ops = &clkhwops_iclk_wait,
  1833. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1834. .enable_bit = OMAP3430_EN_MMC2_SHIFT,
  1835. .clkdm_name = "core_l4_clkdm",
  1836. };
  1837. DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
  1838. static struct clk mmchs3_fck;
  1839. static struct clk_hw_omap mmchs3_fck_hw = {
  1840. .hw = {
  1841. .clk = &mmchs3_fck,
  1842. },
  1843. .ops = &clkhwops_wait,
  1844. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1845. .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
  1846. .clkdm_name = "core_l4_clkdm",
  1847. };
  1848. DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
  1849. static struct clk mmchs3_ick;
  1850. static struct clk_hw_omap mmchs3_ick_hw = {
  1851. .hw = {
  1852. .clk = &mmchs3_ick,
  1853. },
  1854. .ops = &clkhwops_iclk_wait,
  1855. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1856. .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
  1857. .clkdm_name = "core_l4_clkdm",
  1858. };
  1859. DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
  1860. static struct clk modem_fck;
  1861. static struct clk_hw_omap modem_fck_hw = {
  1862. .hw = {
  1863. .clk = &modem_fck,
  1864. },
  1865. .ops = &clkhwops_iclk_wait,
  1866. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1867. .enable_bit = OMAP3430_EN_MODEM_SHIFT,
  1868. .clkdm_name = "d2d_clkdm",
  1869. };
  1870. DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
  1871. static struct clk mspro_fck;
  1872. static struct clk_hw_omap mspro_fck_hw = {
  1873. .hw = {
  1874. .clk = &mspro_fck,
  1875. },
  1876. .ops = &clkhwops_wait,
  1877. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1878. .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
  1879. .clkdm_name = "core_l4_clkdm",
  1880. };
  1881. DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
  1882. static struct clk mspro_ick;
  1883. static struct clk_hw_omap mspro_ick_hw = {
  1884. .hw = {
  1885. .clk = &mspro_ick,
  1886. },
  1887. .ops = &clkhwops_iclk_wait,
  1888. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1889. .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
  1890. .clkdm_name = "core_l4_clkdm",
  1891. };
  1892. DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
  1893. static struct clk omap_192m_alwon_fck;
  1894. DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
  1895. DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
  1896. core_ck_ops);
  1897. static struct clk omap_32ksync_ick;
  1898. static struct clk_hw_omap omap_32ksync_ick_hw = {
  1899. .hw = {
  1900. .clk = &omap_32ksync_ick,
  1901. },
  1902. .ops = &clkhwops_iclk_wait,
  1903. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  1904. .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
  1905. .clkdm_name = "wkup_clkdm",
  1906. };
  1907. DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
  1908. static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
  1909. { .div = 1, .val = 1, .flags = RATE_IN_36XX },
  1910. { .div = 2, .val = 2, .flags = RATE_IN_36XX },
  1911. { .div = 0 }
  1912. };
  1913. static const struct clksel omap_96m_alwon_fck_clksel[] = {
  1914. { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
  1915. { .parent = NULL }
  1916. };
  1917. static struct clk omap_96m_alwon_fck_3630;
  1918. static const char *omap_96m_alwon_fck_3630_parent_names[] = {
  1919. "omap_192m_alwon_fck",
  1920. };
  1921. static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
  1922. .set_rate = &omap2_clksel_set_rate,
  1923. .recalc_rate = &omap2_clksel_recalc,
  1924. .round_rate = &omap2_clksel_round_rate,
  1925. };
  1926. static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
  1927. .hw = {
  1928. .clk = &omap_96m_alwon_fck_3630,
  1929. },
  1930. .clksel = omap_96m_alwon_fck_clksel,
  1931. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1932. .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
  1933. };
  1934. static struct clk omap_96m_alwon_fck_3630 = {
  1935. .name = "omap_96m_alwon_fck",
  1936. .hw = &omap_96m_alwon_fck_3630_hw.hw,
  1937. .parent_names = omap_96m_alwon_fck_3630_parent_names,
  1938. .num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
  1939. .ops = &omap_96m_alwon_fck_3630_ops,
  1940. };
  1941. static struct clk omapctrl_ick;
  1942. static struct clk_hw_omap omapctrl_ick_hw = {
  1943. .hw = {
  1944. .clk = &omapctrl_ick,
  1945. },
  1946. .ops = &clkhwops_iclk_wait,
  1947. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1948. .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
  1949. .flags = ENABLE_ON_INIT,
  1950. .clkdm_name = "core_l4_clkdm",
  1951. };
  1952. DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
  1953. DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
  1954. OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  1955. OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
  1956. CLK_DIVIDER_ONE_BASED, NULL);
  1957. DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
  1958. OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  1959. OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
  1960. CLK_DIVIDER_ONE_BASED, NULL);
  1961. static struct clk per_48m_fck;
  1962. DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
  1963. DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
  1964. static struct clk security_l3_ick;
  1965. DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
  1966. DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
  1967. static struct clk pka_ick;
  1968. static const char *pka_ick_parent_names[] = {
  1969. "security_l3_ick",
  1970. };
  1971. static struct clk_hw_omap pka_ick_hw = {
  1972. .hw = {
  1973. .clk = &pka_ick,
  1974. },
  1975. .ops = &clkhwops_iclk_wait,
  1976. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1977. .enable_bit = OMAP3430_EN_PKA_SHIFT,
  1978. };
  1979. DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
  1980. DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
  1981. OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
  1982. OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
  1983. CLK_DIVIDER_ONE_BASED, NULL);
  1984. static struct clk rng_ick;
  1985. static struct clk_hw_omap rng_ick_hw = {
  1986. .hw = {
  1987. .clk = &rng_ick,
  1988. },
  1989. .ops = &clkhwops_iclk_wait,
  1990. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1991. .enable_bit = OMAP3430_EN_RNG_SHIFT,
  1992. };
  1993. DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
  1994. static struct clk sad2d_ick;
  1995. static struct clk_hw_omap sad2d_ick_hw = {
  1996. .hw = {
  1997. .clk = &sad2d_ick,
  1998. },
  1999. .ops = &clkhwops_iclk_wait,
  2000. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2001. .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
  2002. .clkdm_name = "d2d_clkdm",
  2003. };
  2004. DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
  2005. static struct clk sdrc_ick;
  2006. static struct clk_hw_omap sdrc_ick_hw = {
  2007. .hw = {
  2008. .clk = &sdrc_ick,
  2009. },
  2010. .ops = &clkhwops_wait,
  2011. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2012. .enable_bit = OMAP3430_EN_SDRC_SHIFT,
  2013. .flags = ENABLE_ON_INIT,
  2014. .clkdm_name = "core_l3_clkdm",
  2015. };
  2016. DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
  2017. static const struct clksel_rate sgx_core_rates[] = {
  2018. { .div = 2, .val = 5, .flags = RATE_IN_36XX },
  2019. { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
  2020. { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
  2021. { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
  2022. { .div = 0 }
  2023. };
  2024. static const struct clksel_rate sgx_96m_rates[] = {
  2025. { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
  2026. { .div = 0 }
  2027. };
  2028. static const struct clksel_rate sgx_192m_rates[] = {
  2029. { .div = 1, .val = 4, .flags = RATE_IN_36XX },
  2030. { .div = 0 }
  2031. };
  2032. static const struct clksel_rate sgx_corex2_rates[] = {
  2033. { .div = 3, .val = 6, .flags = RATE_IN_36XX },
  2034. { .div = 5, .val = 7, .flags = RATE_IN_36XX },
  2035. { .div = 0 }
  2036. };
  2037. static const struct clksel sgx_clksel[] = {
  2038. { .parent = &core_ck, .rates = sgx_core_rates },
  2039. { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
  2040. { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
  2041. { .parent = &corex2_fck, .rates = sgx_corex2_rates },
  2042. { .parent = NULL },
  2043. };
  2044. static const char *sgx_fck_parent_names[] = {
  2045. "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
  2046. };
  2047. static struct clk sgx_fck;
  2048. static const struct clk_ops sgx_fck_ops = {
  2049. .init = &omap2_init_clk_clkdm,
  2050. .enable = &omap2_dflt_clk_enable,
  2051. .disable = &omap2_dflt_clk_disable,
  2052. .is_enabled = &omap2_dflt_clk_is_enabled,
  2053. .recalc_rate = &omap2_clksel_recalc,
  2054. .set_rate = &omap2_clksel_set_rate,
  2055. .round_rate = &omap2_clksel_round_rate,
  2056. .get_parent = &omap2_clksel_find_parent_index,
  2057. .set_parent = &omap2_clksel_set_parent,
  2058. };
  2059. DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
  2060. OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
  2061. OMAP3430ES2_CLKSEL_SGX_MASK,
  2062. OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
  2063. OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
  2064. &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
  2065. static struct clk sgx_ick;
  2066. static struct clk_hw_omap sgx_ick_hw = {
  2067. .hw = {
  2068. .clk = &sgx_ick,
  2069. },
  2070. .ops = &clkhwops_wait,
  2071. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
  2072. .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
  2073. .clkdm_name = "sgx_clkdm",
  2074. };
  2075. DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
  2076. static struct clk sha11_ick;
  2077. static struct clk_hw_omap sha11_ick_hw = {
  2078. .hw = {
  2079. .clk = &sha11_ick,
  2080. },
  2081. .ops = &clkhwops_iclk_wait,
  2082. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  2083. .enable_bit = OMAP3430_EN_SHA11_SHIFT,
  2084. };
  2085. DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
  2086. static struct clk sha12_ick;
  2087. static struct clk_hw_omap sha12_ick_hw = {
  2088. .hw = {
  2089. .clk = &sha12_ick,
  2090. },
  2091. .ops = &clkhwops_iclk_wait,
  2092. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2093. .enable_bit = OMAP3430_EN_SHA12_SHIFT,
  2094. .clkdm_name = "core_l4_clkdm",
  2095. };
  2096. DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
  2097. static struct clk sr1_fck;
  2098. static struct clk_hw_omap sr1_fck_hw = {
  2099. .hw = {
  2100. .clk = &sr1_fck,
  2101. },
  2102. .ops = &clkhwops_wait,
  2103. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2104. .enable_bit = OMAP3430_EN_SR1_SHIFT,
  2105. .clkdm_name = "wkup_clkdm",
  2106. };
  2107. DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
  2108. static struct clk sr2_fck;
  2109. static struct clk_hw_omap sr2_fck_hw = {
  2110. .hw = {
  2111. .clk = &sr2_fck,
  2112. },
  2113. .ops = &clkhwops_wait,
  2114. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2115. .enable_bit = OMAP3430_EN_SR2_SHIFT,
  2116. .clkdm_name = "wkup_clkdm",
  2117. };
  2118. DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
  2119. static struct clk sr_l4_ick;
  2120. DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
  2121. DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
  2122. static struct clk ssi_l4_ick;
  2123. DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
  2124. DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
  2125. static struct clk ssi_ick_3430es1;
  2126. static const char *ssi_ick_3430es1_parent_names[] = {
  2127. "ssi_l4_ick",
  2128. };
  2129. static struct clk_hw_omap ssi_ick_3430es1_hw = {
  2130. .hw = {
  2131. .clk = &ssi_ick_3430es1,
  2132. },
  2133. .ops = &clkhwops_iclk,
  2134. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2135. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  2136. .clkdm_name = "core_l4_clkdm",
  2137. };
  2138. DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
  2139. static struct clk ssi_ick_3430es2;
  2140. static struct clk_hw_omap ssi_ick_3430es2_hw = {
  2141. .hw = {
  2142. .clk = &ssi_ick_3430es2,
  2143. },
  2144. .ops = &clkhwops_omap3430es2_iclk_ssi_wait,
  2145. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2146. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  2147. .clkdm_name = "core_l4_clkdm",
  2148. };
  2149. DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
  2150. static const struct clksel_rate ssi_ssr_corex2_rates[] = {
  2151. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  2152. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  2153. { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
  2154. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  2155. { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
  2156. { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
  2157. { .div = 0 }
  2158. };
  2159. static const struct clksel ssi_ssr_clksel[] = {
  2160. { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
  2161. { .parent = NULL },
  2162. };
  2163. static const char *ssi_ssr_fck_3430es1_parent_names[] = {
  2164. "corex2_fck",
  2165. };
  2166. static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
  2167. .init = &omap2_init_clk_clkdm,
  2168. .enable = &omap2_dflt_clk_enable,
  2169. .disable = &omap2_dflt_clk_disable,
  2170. .is_enabled = &omap2_dflt_clk_is_enabled,
  2171. .recalc_rate = &omap2_clksel_recalc,
  2172. .set_rate = &omap2_clksel_set_rate,
  2173. .round_rate = &omap2_clksel_round_rate,
  2174. };
  2175. DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
  2176. ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  2177. OMAP3430_CLKSEL_SSI_MASK,
  2178. OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  2179. OMAP3430_EN_SSI_SHIFT,
  2180. NULL, ssi_ssr_fck_3430es1_parent_names,
  2181. ssi_ssr_fck_3430es1_ops);
  2182. DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
  2183. ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  2184. OMAP3430_CLKSEL_SSI_MASK,
  2185. OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  2186. OMAP3430_EN_SSI_SHIFT,
  2187. NULL, ssi_ssr_fck_3430es1_parent_names,
  2188. ssi_ssr_fck_3430es1_ops);
  2189. DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
  2190. &ssi_ssr_fck_3430es1, 0x0, 1, 2);
  2191. DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
  2192. &ssi_ssr_fck_3430es2, 0x0, 1, 2);
  2193. static struct clk sys_clkout1;
  2194. static const char *sys_clkout1_parent_names[] = {
  2195. "osc_sys_ck",
  2196. };
  2197. static struct clk_hw_omap sys_clkout1_hw = {
  2198. .hw = {
  2199. .clk = &sys_clkout1,
  2200. },
  2201. .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
  2202. .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
  2203. };
  2204. DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
  2205. DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
  2206. OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
  2207. OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
  2208. DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
  2209. OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2210. OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
  2211. 0x0, NULL);
  2212. DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
  2213. OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2214. OMAP3430_CLKSEL_TRACECLK_SHIFT,
  2215. OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
  2216. static struct clk ts_fck;
  2217. static struct clk_hw_omap ts_fck_hw = {
  2218. .hw = {
  2219. .clk = &ts_fck,
  2220. },
  2221. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  2222. .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
  2223. .clkdm_name = "core_l4_clkdm",
  2224. };
  2225. DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
  2226. static struct clk uart1_fck;
  2227. static struct clk_hw_omap uart1_fck_hw = {
  2228. .hw = {
  2229. .clk = &uart1_fck,
  2230. },
  2231. .ops = &clkhwops_wait,
  2232. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  2233. .enable_bit = OMAP3430_EN_UART1_SHIFT,
  2234. .clkdm_name = "core_l4_clkdm",
  2235. };
  2236. DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
  2237. static struct clk uart1_ick;
  2238. static struct clk_hw_omap uart1_ick_hw = {
  2239. .hw = {
  2240. .clk = &uart1_ick,
  2241. },
  2242. .ops = &clkhwops_iclk_wait,
  2243. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2244. .enable_bit = OMAP3430_EN_UART1_SHIFT,
  2245. .clkdm_name = "core_l4_clkdm",
  2246. };
  2247. DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
  2248. static struct clk uart2_fck;
  2249. static struct clk_hw_omap uart2_fck_hw = {
  2250. .hw = {
  2251. .clk = &uart2_fck,
  2252. },
  2253. .ops = &clkhwops_wait,
  2254. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  2255. .enable_bit = OMAP3430_EN_UART2_SHIFT,
  2256. .clkdm_name = "core_l4_clkdm",
  2257. };
  2258. DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
  2259. static struct clk uart2_ick;
  2260. static struct clk_hw_omap uart2_ick_hw = {
  2261. .hw = {
  2262. .clk = &uart2_ick,
  2263. },
  2264. .ops = &clkhwops_iclk_wait,
  2265. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2266. .enable_bit = OMAP3430_EN_UART2_SHIFT,
  2267. .clkdm_name = "core_l4_clkdm",
  2268. };
  2269. DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
  2270. static struct clk uart3_fck;
  2271. static const char *uart3_fck_parent_names[] = {
  2272. "per_48m_fck",
  2273. };
  2274. static struct clk_hw_omap uart3_fck_hw = {
  2275. .hw = {
  2276. .clk = &uart3_fck,
  2277. },
  2278. .ops = &clkhwops_wait,
  2279. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2280. .enable_bit = OMAP3430_EN_UART3_SHIFT,
  2281. .clkdm_name = "per_clkdm",
  2282. };
  2283. DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
  2284. static struct clk uart3_ick;
  2285. static struct clk_hw_omap uart3_ick_hw = {
  2286. .hw = {
  2287. .clk = &uart3_ick,
  2288. },
  2289. .ops = &clkhwops_iclk_wait,
  2290. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2291. .enable_bit = OMAP3430_EN_UART3_SHIFT,
  2292. .clkdm_name = "per_clkdm",
  2293. };
  2294. DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
  2295. static struct clk uart4_fck;
  2296. static struct clk_hw_omap uart4_fck_hw = {
  2297. .hw = {
  2298. .clk = &uart4_fck,
  2299. },
  2300. .ops = &clkhwops_wait,
  2301. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2302. .enable_bit = OMAP3630_EN_UART4_SHIFT,
  2303. .clkdm_name = "per_clkdm",
  2304. };
  2305. DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
  2306. static struct clk uart4_fck_am35xx;
  2307. static struct clk_hw_omap uart4_fck_am35xx_hw = {
  2308. .hw = {
  2309. .clk = &uart4_fck_am35xx,
  2310. },
  2311. .ops = &clkhwops_wait,
  2312. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  2313. .enable_bit = AM35XX_EN_UART4_SHIFT,
  2314. .clkdm_name = "core_l4_clkdm",
  2315. };
  2316. DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
  2317. static struct clk uart4_ick;
  2318. static struct clk_hw_omap uart4_ick_hw = {
  2319. .hw = {
  2320. .clk = &uart4_ick,
  2321. },
  2322. .ops = &clkhwops_iclk_wait,
  2323. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2324. .enable_bit = OMAP3630_EN_UART4_SHIFT,
  2325. .clkdm_name = "per_clkdm",
  2326. };
  2327. DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
  2328. static struct clk uart4_ick_am35xx;
  2329. static struct clk_hw_omap uart4_ick_am35xx_hw = {
  2330. .hw = {
  2331. .clk = &uart4_ick_am35xx,
  2332. },
  2333. .ops = &clkhwops_iclk_wait,
  2334. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2335. .enable_bit = AM35XX_EN_UART4_SHIFT,
  2336. .clkdm_name = "core_l4_clkdm",
  2337. };
  2338. DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
  2339. static const struct clksel_rate div2_rates[] = {
  2340. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  2341. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  2342. { .div = 0 }
  2343. };
  2344. static const struct clksel usb_l4_clksel[] = {
  2345. { .parent = &l4_ick, .rates = div2_rates },
  2346. { .parent = NULL },
  2347. };
  2348. static const char *usb_l4_ick_parent_names[] = {
  2349. "l4_ick",
  2350. };
  2351. DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
  2352. OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  2353. OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
  2354. OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  2355. OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
  2356. &clkhwops_iclk_wait, usb_l4_ick_parent_names,
  2357. ssi_ssr_fck_3430es1_ops);
  2358. static struct clk usbhost_120m_fck;
  2359. static const char *usbhost_120m_fck_parent_names[] = {
  2360. "dpll5_m2_ck",
  2361. };
  2362. static struct clk_hw_omap usbhost_120m_fck_hw = {
  2363. .hw = {
  2364. .clk = &usbhost_120m_fck,
  2365. },
  2366. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
  2367. .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
  2368. .clkdm_name = "usbhost_clkdm",
  2369. };
  2370. DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
  2371. aes2_ick_ops);
  2372. static struct clk usbhost_48m_fck;
  2373. static struct clk_hw_omap usbhost_48m_fck_hw = {
  2374. .hw = {
  2375. .clk = &usbhost_48m_fck,
  2376. },
  2377. .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
  2378. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
  2379. .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
  2380. .clkdm_name = "usbhost_clkdm",
  2381. };
  2382. DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
  2383. static struct clk usbhost_ick;
  2384. static struct clk_hw_omap usbhost_ick_hw = {
  2385. .hw = {
  2386. .clk = &usbhost_ick,
  2387. },
  2388. .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
  2389. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
  2390. .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
  2391. .clkdm_name = "usbhost_clkdm",
  2392. };
  2393. DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
  2394. static struct clk usbtll_fck;
  2395. static struct clk_hw_omap usbtll_fck_hw = {
  2396. .hw = {
  2397. .clk = &usbtll_fck,
  2398. },
  2399. .ops = &clkhwops_wait,
  2400. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  2401. .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
  2402. .clkdm_name = "core_l4_clkdm",
  2403. };
  2404. DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
  2405. static struct clk usbtll_ick;
  2406. static struct clk_hw_omap usbtll_ick_hw = {
  2407. .hw = {
  2408. .clk = &usbtll_ick,
  2409. },
  2410. .ops = &clkhwops_iclk_wait,
  2411. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
  2412. .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
  2413. .clkdm_name = "core_l4_clkdm",
  2414. };
  2415. DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
  2416. static const struct clksel_rate usim_96m_rates[] = {
  2417. { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
  2418. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  2419. { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
  2420. { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
  2421. { .div = 0 }
  2422. };
  2423. static const struct clksel_rate usim_120m_rates[] = {
  2424. { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
  2425. { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
  2426. { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
  2427. { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
  2428. { .div = 0 }
  2429. };
  2430. static const struct clksel usim_clksel[] = {
  2431. { .parent = &omap_96m_fck, .rates = usim_96m_rates },
  2432. { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
  2433. { .parent = &sys_ck, .rates = div2_rates },
  2434. { .parent = NULL },
  2435. };
  2436. static const char *usim_fck_parent_names[] = {
  2437. "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
  2438. };
  2439. static struct clk usim_fck;
  2440. static const struct clk_ops usim_fck_ops = {
  2441. .enable = &omap2_dflt_clk_enable,
  2442. .disable = &omap2_dflt_clk_disable,
  2443. .is_enabled = &omap2_dflt_clk_is_enabled,
  2444. .recalc_rate = &omap2_clksel_recalc,
  2445. .get_parent = &omap2_clksel_find_parent_index,
  2446. .set_parent = &omap2_clksel_set_parent,
  2447. };
  2448. DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
  2449. OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
  2450. OMAP3430ES2_CLKSEL_USIMOCP_MASK,
  2451. OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2452. OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
  2453. usim_fck_parent_names, usim_fck_ops);
  2454. static struct clk usim_ick;
  2455. static struct clk_hw_omap usim_ick_hw = {
  2456. .hw = {
  2457. .clk = &usim_ick,
  2458. },
  2459. .ops = &clkhwops_iclk_wait,
  2460. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2461. .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
  2462. .clkdm_name = "wkup_clkdm",
  2463. };
  2464. DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
  2465. static struct clk vpfe_fck;
  2466. static const char *vpfe_fck_parent_names[] = {
  2467. "pclk_ck",
  2468. };
  2469. static struct clk_hw_omap vpfe_fck_hw = {
  2470. .hw = {
  2471. .clk = &vpfe_fck,
  2472. },
  2473. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  2474. .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
  2475. };
  2476. DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
  2477. static struct clk vpfe_ick;
  2478. static struct clk_hw_omap vpfe_ick_hw = {
  2479. .hw = {
  2480. .clk = &vpfe_ick,
  2481. },
  2482. .ops = &clkhwops_am35xx_ipss_module_wait,
  2483. .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
  2484. .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
  2485. .clkdm_name = "core_l3_clkdm",
  2486. };
  2487. DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
  2488. static struct clk wdt1_fck;
  2489. DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
  2490. DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
  2491. static struct clk wdt1_ick;
  2492. static struct clk_hw_omap wdt1_ick_hw = {
  2493. .hw = {
  2494. .clk = &wdt1_ick,
  2495. },
  2496. .ops = &clkhwops_iclk_wait,
  2497. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2498. .enable_bit = OMAP3430_EN_WDT1_SHIFT,
  2499. .clkdm_name = "wkup_clkdm",
  2500. };
  2501. DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
  2502. static struct clk wdt2_fck;
  2503. static struct clk_hw_omap wdt2_fck_hw = {
  2504. .hw = {
  2505. .clk = &wdt2_fck,
  2506. },
  2507. .ops = &clkhwops_wait,
  2508. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2509. .enable_bit = OMAP3430_EN_WDT2_SHIFT,
  2510. .clkdm_name = "wkup_clkdm",
  2511. };
  2512. DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
  2513. static struct clk wdt2_ick;
  2514. static struct clk_hw_omap wdt2_ick_hw = {
  2515. .hw = {
  2516. .clk = &wdt2_ick,
  2517. },
  2518. .ops = &clkhwops_iclk_wait,
  2519. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2520. .enable_bit = OMAP3430_EN_WDT2_SHIFT,
  2521. .clkdm_name = "wkup_clkdm",
  2522. };
  2523. DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
  2524. static struct clk wdt3_fck;
  2525. static struct clk_hw_omap wdt3_fck_hw = {
  2526. .hw = {
  2527. .clk = &wdt3_fck,
  2528. },
  2529. .ops = &clkhwops_wait,
  2530. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2531. .enable_bit = OMAP3430_EN_WDT3_SHIFT,
  2532. .clkdm_name = "per_clkdm",
  2533. };
  2534. DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
  2535. static struct clk wdt3_ick;
  2536. static struct clk_hw_omap wdt3_ick_hw = {
  2537. .hw = {
  2538. .clk = &wdt3_ick,
  2539. },
  2540. .ops = &clkhwops_iclk_wait,
  2541. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2542. .enable_bit = OMAP3430_EN_WDT3_SHIFT,
  2543. .clkdm_name = "per_clkdm",
  2544. };
  2545. DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
  2546. /*
  2547. * clocks specific to omap3430es1
  2548. */
  2549. static struct omap_clk omap3430es1_clks[] = {
  2550. CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
  2551. CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
  2552. CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
  2553. CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
  2554. CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
  2555. CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
  2556. CLK(NULL, "fshostusb_fck", &fshostusb_fck),
  2557. CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
  2558. CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
  2559. CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
  2560. CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
  2561. CLK(NULL, "fac_ick", &fac_ick),
  2562. CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
  2563. CLK(NULL, "usb_l4_ick", &usb_l4_ick),
  2564. CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
  2565. CLK("omapdss_dss", "ick", &dss_ick_3430es1),
  2566. CLK(NULL, "dss_ick", &dss_ick_3430es1),
  2567. };
  2568. /*
  2569. * clocks specific to am35xx
  2570. */
  2571. static struct omap_clk am35xx_clks[] = {
  2572. CLK(NULL, "ipss_ick", &ipss_ick),
  2573. CLK(NULL, "rmii_ck", &rmii_ck),
  2574. CLK(NULL, "pclk_ck", &pclk_ck),
  2575. CLK(NULL, "emac_ick", &emac_ick),
  2576. CLK(NULL, "emac_fck", &emac_fck),
  2577. CLK("davinci_emac.0", NULL, &emac_ick),
  2578. CLK("davinci_mdio.0", NULL, &emac_fck),
  2579. CLK("vpfe-capture", "master", &vpfe_ick),
  2580. CLK("vpfe-capture", "slave", &vpfe_fck),
  2581. CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
  2582. CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
  2583. CLK(NULL, "hecc_ck", &hecc_ck),
  2584. CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
  2585. CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
  2586. };
  2587. /*
  2588. * clocks specific to omap36xx
  2589. */
  2590. static struct omap_clk omap36xx_clks[] = {
  2591. CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
  2592. CLK(NULL, "uart4_fck", &uart4_fck),
  2593. };
  2594. /*
  2595. * clocks common to omap36xx omap34xx
  2596. */
  2597. static struct omap_clk omap34xx_omap36xx_clks[] = {
  2598. CLK(NULL, "aes1_ick", &aes1_ick),
  2599. CLK("omap_rng", "ick", &rng_ick),
  2600. CLK(NULL, "sha11_ick", &sha11_ick),
  2601. CLK(NULL, "des1_ick", &des1_ick),
  2602. CLK(NULL, "cam_mclk", &cam_mclk),
  2603. CLK(NULL, "cam_ick", &cam_ick),
  2604. CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
  2605. CLK(NULL, "security_l3_ick", &security_l3_ick),
  2606. CLK(NULL, "pka_ick", &pka_ick),
  2607. CLK(NULL, "icr_ick", &icr_ick),
  2608. CLK("omap-aes", "ick", &aes2_ick),
  2609. CLK("omap-sham", "ick", &sha12_ick),
  2610. CLK(NULL, "des2_ick", &des2_ick),
  2611. CLK(NULL, "mspro_ick", &mspro_ick),
  2612. CLK(NULL, "mailboxes_ick", &mailboxes_ick),
  2613. CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
  2614. CLK(NULL, "sr1_fck", &sr1_fck),
  2615. CLK(NULL, "sr2_fck", &sr2_fck),
  2616. CLK(NULL, "sr_l4_ick", &sr_l4_ick),
  2617. CLK(NULL, "security_l4_ick2", &security_l4_ick2),
  2618. CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
  2619. CLK(NULL, "dpll2_fck", &dpll2_fck),
  2620. CLK(NULL, "iva2_ck", &iva2_ck),
  2621. CLK(NULL, "modem_fck", &modem_fck),
  2622. CLK(NULL, "sad2d_ick", &sad2d_ick),
  2623. CLK(NULL, "mad2d_ick", &mad2d_ick),
  2624. CLK(NULL, "mspro_fck", &mspro_fck),
  2625. CLK(NULL, "dpll2_ck", &dpll2_ck),
  2626. CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
  2627. };
  2628. /*
  2629. * clocks common to omap36xx and omap3430es2plus
  2630. */
  2631. static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
  2632. CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
  2633. CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
  2634. CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
  2635. CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
  2636. CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
  2637. CLK(NULL, "usim_fck", &usim_fck),
  2638. CLK(NULL, "usim_ick", &usim_ick),
  2639. };
  2640. /*
  2641. * clocks common to am35xx omap36xx and omap3430es2plus
  2642. */
  2643. static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
  2644. CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
  2645. CLK(NULL, "dpll5_ck", &dpll5_ck),
  2646. CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
  2647. CLK(NULL, "sgx_fck", &sgx_fck),
  2648. CLK(NULL, "sgx_ick", &sgx_ick),
  2649. CLK(NULL, "cpefuse_fck", &cpefuse_fck),
  2650. CLK(NULL, "ts_fck", &ts_fck),
  2651. CLK(NULL, "usbtll_fck", &usbtll_fck),
  2652. CLK("usbhs_omap", "usbtll_fck", &usbtll_fck),
  2653. CLK("usbhs_tll", "usbtll_fck", &usbtll_fck),
  2654. CLK(NULL, "usbtll_ick", &usbtll_ick),
  2655. CLK("usbhs_omap", "usbtll_ick", &usbtll_ick),
  2656. CLK("usbhs_tll", "usbtll_ick", &usbtll_ick),
  2657. CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
  2658. CLK(NULL, "mmchs3_ick", &mmchs3_ick),
  2659. CLK(NULL, "mmchs3_fck", &mmchs3_fck),
  2660. CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
  2661. CLK("omapdss_dss", "ick", &dss_ick_3430es2),
  2662. CLK(NULL, "dss_ick", &dss_ick_3430es2),
  2663. CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
  2664. CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
  2665. CLK(NULL, "usbhost_ick", &usbhost_ick),
  2666. CLK("usbhs_omap", "usbhost_ick", &usbhost_ick),
  2667. };
  2668. /*
  2669. * common clocks
  2670. */
  2671. static struct omap_clk omap3xxx_clks[] = {
  2672. CLK(NULL, "apb_pclk", &dummy_apb_pclk),
  2673. CLK(NULL, "omap_32k_fck", &omap_32k_fck),
  2674. CLK(NULL, "virt_12m_ck", &virt_12m_ck),
  2675. CLK(NULL, "virt_13m_ck", &virt_13m_ck),
  2676. CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
  2677. CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
  2678. CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
  2679. CLK(NULL, "osc_sys_ck", &osc_sys_ck),
  2680. CLK("twl", "fck", &osc_sys_ck),
  2681. CLK(NULL, "sys_ck", &sys_ck),
  2682. CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
  2683. CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
  2684. CLK(NULL, "sys_altclk", &sys_altclk),
  2685. CLK(NULL, "mcbsp_clks", &mcbsp_clks),
  2686. CLK(NULL, "sys_clkout1", &sys_clkout1),
  2687. CLK(NULL, "dpll1_ck", &dpll1_ck),
  2688. CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
  2689. CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
  2690. CLK(NULL, "dpll3_ck", &dpll3_ck),
  2691. CLK(NULL, "core_ck", &core_ck),
  2692. CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
  2693. CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
  2694. CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
  2695. CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
  2696. CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
  2697. CLK(NULL, "dpll4_ck", &dpll4_ck),
  2698. CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
  2699. CLK(NULL, "omap_96m_fck", &omap_96m_fck),
  2700. CLK(NULL, "cm_96m_fck", &cm_96m_fck),
  2701. CLK(NULL, "omap_54m_fck", &omap_54m_fck),
  2702. CLK(NULL, "omap_48m_fck", &omap_48m_fck),
  2703. CLK(NULL, "omap_12m_fck", &omap_12m_fck),
  2704. CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
  2705. CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
  2706. CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
  2707. CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
  2708. CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
  2709. CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
  2710. CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
  2711. CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
  2712. CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
  2713. CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
  2714. CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
  2715. CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
  2716. CLK(NULL, "sys_clkout2", &sys_clkout2),
  2717. CLK(NULL, "corex2_fck", &corex2_fck),
  2718. CLK(NULL, "dpll1_fck", &dpll1_fck),
  2719. CLK(NULL, "mpu_ck", &mpu_ck),
  2720. CLK(NULL, "arm_fck", &arm_fck),
  2721. CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
  2722. CLK(NULL, "l3_ick", &l3_ick),
  2723. CLK(NULL, "l4_ick", &l4_ick),
  2724. CLK(NULL, "rm_ick", &rm_ick),
  2725. CLK(NULL, "gpt10_fck", &gpt10_fck),
  2726. CLK(NULL, "gpt11_fck", &gpt11_fck),
  2727. CLK(NULL, "core_96m_fck", &core_96m_fck),
  2728. CLK(NULL, "mmchs2_fck", &mmchs2_fck),
  2729. CLK(NULL, "mmchs1_fck", &mmchs1_fck),
  2730. CLK(NULL, "i2c3_fck", &i2c3_fck),
  2731. CLK(NULL, "i2c2_fck", &i2c2_fck),
  2732. CLK(NULL, "i2c1_fck", &i2c1_fck),
  2733. CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
  2734. CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
  2735. CLK(NULL, "core_48m_fck", &core_48m_fck),
  2736. CLK(NULL, "mcspi4_fck", &mcspi4_fck),
  2737. CLK(NULL, "mcspi3_fck", &mcspi3_fck),
  2738. CLK(NULL, "mcspi2_fck", &mcspi2_fck),
  2739. CLK(NULL, "mcspi1_fck", &mcspi1_fck),
  2740. CLK(NULL, "uart2_fck", &uart2_fck),
  2741. CLK(NULL, "uart1_fck", &uart1_fck),
  2742. CLK(NULL, "core_12m_fck", &core_12m_fck),
  2743. CLK("omap_hdq.0", "fck", &hdq_fck),
  2744. CLK(NULL, "hdq_fck", &hdq_fck),
  2745. CLK(NULL, "core_l3_ick", &core_l3_ick),
  2746. CLK(NULL, "sdrc_ick", &sdrc_ick),
  2747. CLK(NULL, "gpmc_fck", &gpmc_fck),
  2748. CLK(NULL, "core_l4_ick", &core_l4_ick),
  2749. CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
  2750. CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
  2751. CLK(NULL, "mmchs2_ick", &mmchs2_ick),
  2752. CLK(NULL, "mmchs1_ick", &mmchs1_ick),
  2753. CLK("omap_hdq.0", "ick", &hdq_ick),
  2754. CLK(NULL, "hdq_ick", &hdq_ick),
  2755. CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
  2756. CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
  2757. CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
  2758. CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
  2759. CLK(NULL, "mcspi4_ick", &mcspi4_ick),
  2760. CLK(NULL, "mcspi3_ick", &mcspi3_ick),
  2761. CLK(NULL, "mcspi2_ick", &mcspi2_ick),
  2762. CLK(NULL, "mcspi1_ick", &mcspi1_ick),
  2763. CLK("omap_i2c.3", "ick", &i2c3_ick),
  2764. CLK("omap_i2c.2", "ick", &i2c2_ick),
  2765. CLK("omap_i2c.1", "ick", &i2c1_ick),
  2766. CLK(NULL, "i2c3_ick", &i2c3_ick),
  2767. CLK(NULL, "i2c2_ick", &i2c2_ick),
  2768. CLK(NULL, "i2c1_ick", &i2c1_ick),
  2769. CLK(NULL, "uart2_ick", &uart2_ick),
  2770. CLK(NULL, "uart1_ick", &uart1_ick),
  2771. CLK(NULL, "gpt11_ick", &gpt11_ick),
  2772. CLK(NULL, "gpt10_ick", &gpt10_ick),
  2773. CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
  2774. CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
  2775. CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
  2776. CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
  2777. CLK(NULL, "omapctrl_ick", &omapctrl_ick),
  2778. CLK(NULL, "dss_tv_fck", &dss_tv_fck),
  2779. CLK(NULL, "dss_96m_fck", &dss_96m_fck),
  2780. CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
  2781. CLK(NULL, "utmi_p1_gfclk", &dummy_ck),
  2782. CLK(NULL, "utmi_p2_gfclk", &dummy_ck),
  2783. CLK(NULL, "xclk60mhsp1_ck", &dummy_ck),
  2784. CLK(NULL, "xclk60mhsp2_ck", &dummy_ck),
  2785. CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck),
  2786. CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck),
  2787. CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
  2788. CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
  2789. CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
  2790. CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
  2791. CLK(NULL, "init_60m_fclk", &dummy_ck),
  2792. CLK(NULL, "gpt1_fck", &gpt1_fck),
  2793. CLK(NULL, "aes2_ick", &aes2_ick),
  2794. CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
  2795. CLK(NULL, "gpio1_dbck", &gpio1_dbck),
  2796. CLK(NULL, "sha12_ick", &sha12_ick),
  2797. CLK(NULL, "wdt2_fck", &wdt2_fck),
  2798. CLK("omap_wdt", "ick", &wdt2_ick),
  2799. CLK(NULL, "wdt2_ick", &wdt2_ick),
  2800. CLK(NULL, "wdt1_ick", &wdt1_ick),
  2801. CLK(NULL, "gpio1_ick", &gpio1_ick),
  2802. CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
  2803. CLK(NULL, "gpt12_ick", &gpt12_ick),
  2804. CLK(NULL, "gpt1_ick", &gpt1_ick),
  2805. CLK(NULL, "per_96m_fck", &per_96m_fck),
  2806. CLK(NULL, "per_48m_fck", &per_48m_fck),
  2807. CLK(NULL, "uart3_fck", &uart3_fck),
  2808. CLK(NULL, "gpt2_fck", &gpt2_fck),
  2809. CLK(NULL, "gpt3_fck", &gpt3_fck),
  2810. CLK(NULL, "gpt4_fck", &gpt4_fck),
  2811. CLK(NULL, "gpt5_fck", &gpt5_fck),
  2812. CLK(NULL, "gpt6_fck", &gpt6_fck),
  2813. CLK(NULL, "gpt7_fck", &gpt7_fck),
  2814. CLK(NULL, "gpt8_fck", &gpt8_fck),
  2815. CLK(NULL, "gpt9_fck", &gpt9_fck),
  2816. CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
  2817. CLK(NULL, "gpio6_dbck", &gpio6_dbck),
  2818. CLK(NULL, "gpio5_dbck", &gpio5_dbck),
  2819. CLK(NULL, "gpio4_dbck", &gpio4_dbck),
  2820. CLK(NULL, "gpio3_dbck", &gpio3_dbck),
  2821. CLK(NULL, "gpio2_dbck", &gpio2_dbck),
  2822. CLK(NULL, "wdt3_fck", &wdt3_fck),
  2823. CLK(NULL, "per_l4_ick", &per_l4_ick),
  2824. CLK(NULL, "gpio6_ick", &gpio6_ick),
  2825. CLK(NULL, "gpio5_ick", &gpio5_ick),
  2826. CLK(NULL, "gpio4_ick", &gpio4_ick),
  2827. CLK(NULL, "gpio3_ick", &gpio3_ick),
  2828. CLK(NULL, "gpio2_ick", &gpio2_ick),
  2829. CLK(NULL, "wdt3_ick", &wdt3_ick),
  2830. CLK(NULL, "uart3_ick", &uart3_ick),
  2831. CLK(NULL, "uart4_ick", &uart4_ick),
  2832. CLK(NULL, "gpt9_ick", &gpt9_ick),
  2833. CLK(NULL, "gpt8_ick", &gpt8_ick),
  2834. CLK(NULL, "gpt7_ick", &gpt7_ick),
  2835. CLK(NULL, "gpt6_ick", &gpt6_ick),
  2836. CLK(NULL, "gpt5_ick", &gpt5_ick),
  2837. CLK(NULL, "gpt4_ick", &gpt4_ick),
  2838. CLK(NULL, "gpt3_ick", &gpt3_ick),
  2839. CLK(NULL, "gpt2_ick", &gpt2_ick),
  2840. CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
  2841. CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
  2842. CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
  2843. CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
  2844. CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
  2845. CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
  2846. CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
  2847. CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
  2848. CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
  2849. CLK("etb", "emu_src_ck", &emu_src_ck),
  2850. CLK(NULL, "emu_src_ck", &emu_src_ck),
  2851. CLK(NULL, "pclk_fck", &pclk_fck),
  2852. CLK(NULL, "pclkx2_fck", &pclkx2_fck),
  2853. CLK(NULL, "atclk_fck", &atclk_fck),
  2854. CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
  2855. CLK(NULL, "traceclk_fck", &traceclk_fck),
  2856. CLK(NULL, "secure_32k_fck", &secure_32k_fck),
  2857. CLK(NULL, "gpt12_fck", &gpt12_fck),
  2858. CLK(NULL, "wdt1_fck", &wdt1_fck),
  2859. CLK(NULL, "timer_32k_ck", &omap_32k_fck),
  2860. CLK(NULL, "timer_sys_ck", &sys_ck),
  2861. CLK(NULL, "cpufreq_ck", &dpll1_ck),
  2862. };
  2863. static const char *enable_init_clks[] = {
  2864. "sdrc_ick",
  2865. "gpmc_fck",
  2866. "omapctrl_ick",
  2867. };
  2868. int __init omap3xxx_clk_init(void)
  2869. {
  2870. if (omap3_has_192mhz_clk())
  2871. omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
  2872. if (cpu_is_omap3630()) {
  2873. dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
  2874. dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
  2875. dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
  2876. dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
  2877. dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
  2878. dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
  2879. }
  2880. /*
  2881. * XXX This type of dynamic rewriting of the clock tree is
  2882. * deprecated and should be revised soon.
  2883. */
  2884. if (cpu_is_omap3630())
  2885. dpll4_dd = dpll4_dd_3630;
  2886. else
  2887. dpll4_dd = dpll4_dd_34xx;
  2888. /*
  2889. * 3505 must be tested before 3517, since 3517 returns true
  2890. * for both AM3517 chips and AM3517 family chips, which
  2891. * includes 3505. Unfortunately there's no obvious family
  2892. * test for 3517/3505 :-(
  2893. */
  2894. if (soc_is_am35xx()) {
  2895. cpu_mask = RATE_IN_34XX;
  2896. omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
  2897. omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
  2898. ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
  2899. omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
  2900. } else if (cpu_is_omap3630()) {
  2901. cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
  2902. omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
  2903. omap_clocks_register(omap36xx_omap3430es2plus_clks,
  2904. ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
  2905. omap_clocks_register(omap34xx_omap36xx_clks,
  2906. ARRAY_SIZE(omap34xx_omap36xx_clks));
  2907. omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
  2908. ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
  2909. omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
  2910. } else if (soc_is_am33xx()) {
  2911. cpu_mask = RATE_IN_AM33XX;
  2912. } else if (cpu_is_ti814x()) {
  2913. cpu_mask = RATE_IN_TI814X;
  2914. } else if (cpu_is_omap34xx()) {
  2915. if (omap_rev() == OMAP3430_REV_ES1_0) {
  2916. cpu_mask = RATE_IN_3430ES1;
  2917. omap_clocks_register(omap3430es1_clks,
  2918. ARRAY_SIZE(omap3430es1_clks));
  2919. omap_clocks_register(omap34xx_omap36xx_clks,
  2920. ARRAY_SIZE(omap34xx_omap36xx_clks));
  2921. omap_clocks_register(omap3xxx_clks,
  2922. ARRAY_SIZE(omap3xxx_clks));
  2923. } else {
  2924. /*
  2925. * Assume that anything that we haven't matched yet
  2926. * has 3430ES2-type clocks.
  2927. */
  2928. cpu_mask = RATE_IN_3430ES2PLUS;
  2929. omap_clocks_register(omap34xx_omap36xx_clks,
  2930. ARRAY_SIZE(omap34xx_omap36xx_clks));
  2931. omap_clocks_register(omap36xx_omap3430es2plus_clks,
  2932. ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
  2933. omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
  2934. ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
  2935. omap_clocks_register(omap3xxx_clks,
  2936. ARRAY_SIZE(omap3xxx_clks));
  2937. }
  2938. } else {
  2939. WARN(1, "clock: could not identify OMAP3 variant\n");
  2940. }
  2941. omap2_clk_disable_autoidle_all();
  2942. omap2_clk_enable_init_clocks(enable_init_clks,
  2943. ARRAY_SIZE(enable_init_clks));
  2944. pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
  2945. (clk_get_rate(&osc_sys_ck) / 1000000),
  2946. (clk_get_rate(&osc_sys_ck) / 100000) % 10,
  2947. (clk_get_rate(&core_ck) / 1000000),
  2948. (clk_get_rate(&arm_fck) / 1000000));
  2949. /*
  2950. * Lock DPLL5 -- here only until other device init code can
  2951. * handle this
  2952. */
  2953. if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
  2954. omap3_clk_lock_dpll5();
  2955. /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
  2956. sdrc_ick_p = clk_get(NULL, "sdrc_ick");
  2957. arm_fck_p = clk_get(NULL, "arm_fck");
  2958. return 0;
  2959. }