cclock33xx_data.c 28 KB

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  1. /*
  2. * AM33XX Clock data
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. * Vaibhav Hiremath <hvaibhav@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/clk-private.h>
  19. #include <linux/clkdev.h>
  20. #include <linux/io.h>
  21. #include "am33xx.h"
  22. #include "soc.h"
  23. #include "iomap.h"
  24. #include "clock.h"
  25. #include "control.h"
  26. #include "cm.h"
  27. #include "cm33xx.h"
  28. #include "cm-regbits-33xx.h"
  29. #include "prm.h"
  30. /* Modulemode control */
  31. #define AM33XX_MODULEMODE_HWCTRL_SHIFT 0
  32. #define AM33XX_MODULEMODE_SWCTRL_SHIFT 1
  33. /*LIST_HEAD(clocks);*/
  34. /* Root clocks */
  35. /* RTC 32k */
  36. DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
  37. /* On-Chip 32KHz RC OSC */
  38. DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
  39. /* Crystal input clks */
  40. DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
  41. DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
  42. DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
  43. DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
  44. /* Oscillator clock */
  45. /* 19.2, 24, 25 or 26 MHz */
  46. static const char *sys_clkin_ck_parents[] = {
  47. "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
  48. "virt_26000000_ck",
  49. };
  50. /*
  51. * sys_clk in: input to the dpll and also used as funtional clock for,
  52. * adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
  53. *
  54. */
  55. DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
  56. AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
  57. AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
  58. AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
  59. 0, NULL);
  60. /* External clock - 12 MHz */
  61. DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
  62. /* Module clocks and DPLL outputs */
  63. /* DPLL_CORE */
  64. static struct dpll_data dpll_core_dd = {
  65. .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_CORE,
  66. .clk_bypass = &sys_clkin_ck,
  67. .clk_ref = &sys_clkin_ck,
  68. .control_reg = AM33XX_CM_CLKMODE_DPLL_CORE,
  69. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  70. .idlest_reg = AM33XX_CM_IDLEST_DPLL_CORE,
  71. .mult_mask = AM33XX_DPLL_MULT_MASK,
  72. .div1_mask = AM33XX_DPLL_DIV_MASK,
  73. .enable_mask = AM33XX_DPLL_EN_MASK,
  74. .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
  75. .max_multiplier = 2047,
  76. .max_divider = 128,
  77. .min_divider = 1,
  78. };
  79. /* CLKDCOLDO output */
  80. static const char *dpll_core_ck_parents[] = {
  81. "sys_clkin_ck",
  82. };
  83. static struct clk dpll_core_ck;
  84. static const struct clk_ops dpll_core_ck_ops = {
  85. .recalc_rate = &omap3_dpll_recalc,
  86. .get_parent = &omap2_init_dpll_parent,
  87. };
  88. static struct clk_hw_omap dpll_core_ck_hw = {
  89. .hw = {
  90. .clk = &dpll_core_ck,
  91. },
  92. .dpll_data = &dpll_core_dd,
  93. .ops = &clkhwops_omap3_dpll,
  94. };
  95. DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
  96. static const char *dpll_core_x2_ck_parents[] = {
  97. "dpll_core_ck",
  98. };
  99. static struct clk dpll_core_x2_ck;
  100. static const struct clk_ops dpll_x2_ck_ops = {
  101. .recalc_rate = &omap3_clkoutx2_recalc,
  102. };
  103. static struct clk_hw_omap dpll_core_x2_ck_hw = {
  104. .hw = {
  105. .clk = &dpll_core_x2_ck,
  106. },
  107. .flags = CLOCK_CLKOUTX2,
  108. };
  109. DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
  110. DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
  111. 0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
  112. AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
  113. AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
  114. NULL);
  115. DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
  116. 0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
  117. AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
  118. AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
  119. CLK_DIVIDER_ONE_BASED, NULL);
  120. DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
  121. 0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
  122. AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
  123. AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
  124. CLK_DIVIDER_ONE_BASED, NULL);
  125. /* DPLL_MPU */
  126. static struct dpll_data dpll_mpu_dd = {
  127. .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_MPU,
  128. .clk_bypass = &sys_clkin_ck,
  129. .clk_ref = &sys_clkin_ck,
  130. .control_reg = AM33XX_CM_CLKMODE_DPLL_MPU,
  131. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  132. .idlest_reg = AM33XX_CM_IDLEST_DPLL_MPU,
  133. .mult_mask = AM33XX_DPLL_MULT_MASK,
  134. .div1_mask = AM33XX_DPLL_DIV_MASK,
  135. .enable_mask = AM33XX_DPLL_EN_MASK,
  136. .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
  137. .max_multiplier = 2047,
  138. .max_divider = 128,
  139. .min_divider = 1,
  140. };
  141. /* CLKOUT: fdpll/M2 */
  142. static struct clk dpll_mpu_ck;
  143. static const struct clk_ops dpll_mpu_ck_ops = {
  144. .enable = &omap3_noncore_dpll_enable,
  145. .disable = &omap3_noncore_dpll_disable,
  146. .recalc_rate = &omap3_dpll_recalc,
  147. .round_rate = &omap2_dpll_round_rate,
  148. .set_rate = &omap3_noncore_dpll_set_rate,
  149. .get_parent = &omap2_init_dpll_parent,
  150. };
  151. static struct clk_hw_omap dpll_mpu_ck_hw = {
  152. .hw = {
  153. .clk = &dpll_mpu_ck,
  154. },
  155. .dpll_data = &dpll_mpu_dd,
  156. .ops = &clkhwops_omap3_dpll,
  157. };
  158. DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
  159. /*
  160. * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
  161. * and ALT_CLK1/2)
  162. */
  163. DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
  164. 0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
  165. AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
  166. /* DPLL_DDR */
  167. static struct dpll_data dpll_ddr_dd = {
  168. .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DDR,
  169. .clk_bypass = &sys_clkin_ck,
  170. .clk_ref = &sys_clkin_ck,
  171. .control_reg = AM33XX_CM_CLKMODE_DPLL_DDR,
  172. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  173. .idlest_reg = AM33XX_CM_IDLEST_DPLL_DDR,
  174. .mult_mask = AM33XX_DPLL_MULT_MASK,
  175. .div1_mask = AM33XX_DPLL_DIV_MASK,
  176. .enable_mask = AM33XX_DPLL_EN_MASK,
  177. .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
  178. .max_multiplier = 2047,
  179. .max_divider = 128,
  180. .min_divider = 1,
  181. };
  182. /* CLKOUT: fdpll/M2 */
  183. static struct clk dpll_ddr_ck;
  184. static const struct clk_ops dpll_ddr_ck_ops = {
  185. .recalc_rate = &omap3_dpll_recalc,
  186. .get_parent = &omap2_init_dpll_parent,
  187. .round_rate = &omap2_dpll_round_rate,
  188. .set_rate = &omap3_noncore_dpll_set_rate,
  189. };
  190. static struct clk_hw_omap dpll_ddr_ck_hw = {
  191. .hw = {
  192. .clk = &dpll_ddr_ck,
  193. },
  194. .dpll_data = &dpll_ddr_dd,
  195. .ops = &clkhwops_omap3_dpll,
  196. };
  197. DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
  198. /*
  199. * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
  200. * and ALT_CLK1/2)
  201. */
  202. DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
  203. 0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
  204. AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
  205. CLK_DIVIDER_ONE_BASED, NULL);
  206. /* emif_fck functional clock */
  207. DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
  208. 0x0, 1, 2);
  209. /* DPLL_DISP */
  210. static struct dpll_data dpll_disp_dd = {
  211. .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_DISP,
  212. .clk_bypass = &sys_clkin_ck,
  213. .clk_ref = &sys_clkin_ck,
  214. .control_reg = AM33XX_CM_CLKMODE_DPLL_DISP,
  215. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  216. .idlest_reg = AM33XX_CM_IDLEST_DPLL_DISP,
  217. .mult_mask = AM33XX_DPLL_MULT_MASK,
  218. .div1_mask = AM33XX_DPLL_DIV_MASK,
  219. .enable_mask = AM33XX_DPLL_EN_MASK,
  220. .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
  221. .max_multiplier = 2047,
  222. .max_divider = 128,
  223. .min_divider = 1,
  224. };
  225. /* CLKOUT: fdpll/M2 */
  226. static struct clk dpll_disp_ck;
  227. static struct clk_hw_omap dpll_disp_ck_hw = {
  228. .hw = {
  229. .clk = &dpll_disp_ck,
  230. },
  231. .dpll_data = &dpll_disp_dd,
  232. .ops = &clkhwops_omap3_dpll,
  233. };
  234. DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
  235. /*
  236. * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
  237. * and ALT_CLK1/2)
  238. */
  239. DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
  240. CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
  241. AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
  242. CLK_DIVIDER_ONE_BASED, NULL);
  243. /* DPLL_PER */
  244. static struct dpll_data dpll_per_dd = {
  245. .mult_div1_reg = AM33XX_CM_CLKSEL_DPLL_PERIPH,
  246. .clk_bypass = &sys_clkin_ck,
  247. .clk_ref = &sys_clkin_ck,
  248. .control_reg = AM33XX_CM_CLKMODE_DPLL_PER,
  249. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  250. .idlest_reg = AM33XX_CM_IDLEST_DPLL_PER,
  251. .mult_mask = AM33XX_DPLL_MULT_PERIPH_MASK,
  252. .div1_mask = AM33XX_DPLL_PER_DIV_MASK,
  253. .enable_mask = AM33XX_DPLL_EN_MASK,
  254. .idlest_mask = AM33XX_ST_DPLL_CLK_MASK,
  255. .max_multiplier = 2047,
  256. .max_divider = 128,
  257. .min_divider = 1,
  258. .flags = DPLL_J_TYPE,
  259. };
  260. /* CLKDCOLDO */
  261. static struct clk dpll_per_ck;
  262. static struct clk_hw_omap dpll_per_ck_hw = {
  263. .hw = {
  264. .clk = &dpll_per_ck,
  265. },
  266. .dpll_data = &dpll_per_dd,
  267. .ops = &clkhwops_omap3_dpll,
  268. };
  269. DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
  270. /* CLKOUT: fdpll/M2 */
  271. DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
  272. AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
  273. AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
  274. NULL);
  275. DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
  276. &dpll_per_m2_ck, 0x0, 1, 4);
  277. DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
  278. &dpll_per_m2_ck, 0x0, 1, 4);
  279. DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
  280. &dpll_core_m4_ck, 0x0, 1, 2);
  281. DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
  282. 1, 2);
  283. DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
  284. 8);
  285. /*
  286. * Below clock nodes describes clockdomains derived out
  287. * of core clock.
  288. */
  289. static const struct clk_ops clk_ops_null = {
  290. };
  291. static const char *l3_gclk_parents[] = {
  292. "dpll_core_m4_ck"
  293. };
  294. static struct clk l3_gclk;
  295. DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
  296. DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
  297. static struct clk l4hs_gclk;
  298. DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
  299. DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
  300. static const char *l3s_gclk_parents[] = {
  301. "dpll_core_m4_div2_ck"
  302. };
  303. static struct clk l3s_gclk;
  304. DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
  305. DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
  306. static struct clk l4fw_gclk;
  307. DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
  308. DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
  309. static struct clk l4ls_gclk;
  310. DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
  311. DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
  312. static struct clk sysclk_div_ck;
  313. DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
  314. DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
  315. /*
  316. * In order to match the clock domain with hwmod clockdomain entry,
  317. * separate clock nodes is required for the modules which are
  318. * directly getting their funtioncal clock from sys_clkin.
  319. */
  320. static struct clk adc_tsc_fck;
  321. DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
  322. DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
  323. static struct clk dcan0_fck;
  324. DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
  325. DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
  326. static struct clk dcan1_fck;
  327. DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
  328. DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
  329. static struct clk mcasp0_fck;
  330. DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
  331. DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
  332. static struct clk mcasp1_fck;
  333. DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
  334. DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
  335. static struct clk smartreflex0_fck;
  336. DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
  337. DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
  338. static struct clk smartreflex1_fck;
  339. DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
  340. DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
  341. static struct clk sha0_fck;
  342. DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
  343. DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
  344. static struct clk aes0_fck;
  345. DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
  346. DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
  347. /*
  348. * Modules clock nodes
  349. *
  350. * The following clock leaf nodes are added for the moment because:
  351. *
  352. * - hwmod data is not present for these modules, either hwmod
  353. * control is not required or its not populated.
  354. * - Driver code is not yet migrated to use hwmod/runtime pm
  355. * - Modules outside kernel access (to disable them by default)
  356. *
  357. * - debugss
  358. * - mmu (gfx domain)
  359. * - cefuse
  360. * - usbotg_fck (its additional clock and not really a modulemode)
  361. * - ieee5000
  362. */
  363. DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
  364. AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
  365. 0x0, NULL);
  366. DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
  367. AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
  368. 0x0, NULL);
  369. DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
  370. AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
  371. 0x0, NULL);
  372. /*
  373. * clkdiv32 is generated from fixed division of 732.4219
  374. */
  375. DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
  376. DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0,
  377. AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
  378. 0x0, NULL);
  379. /* "usbotg_fck" is an additional clock and not really a modulemode */
  380. DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
  381. AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
  382. 0x0, NULL);
  383. DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
  384. 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
  385. AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
  386. /* Timers */
  387. static const struct clksel timer1_clkmux_sel[] = {
  388. { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
  389. { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
  390. { .parent = &tclkin_ck, .rates = div_1_2_rates },
  391. { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
  392. { .parent = &clk_32768_ck, .rates = div_1_4_rates },
  393. { .parent = NULL },
  394. };
  395. static const char *timer1_ck_parents[] = {
  396. "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
  397. "clk_32768_ck",
  398. };
  399. static struct clk timer1_fck;
  400. static const struct clk_ops timer1_fck_ops = {
  401. .recalc_rate = &omap2_clksel_recalc,
  402. .get_parent = &omap2_clksel_find_parent_index,
  403. .set_parent = &omap2_clksel_set_parent,
  404. .init = &omap2_init_clk_clkdm,
  405. };
  406. static struct clk_hw_omap timer1_fck_hw = {
  407. .hw = {
  408. .clk = &timer1_fck,
  409. },
  410. .clkdm_name = "l4ls_clkdm",
  411. .clksel = timer1_clkmux_sel,
  412. .clksel_reg = AM33XX_CLKSEL_TIMER1MS_CLK,
  413. .clksel_mask = AM33XX_CLKSEL_0_2_MASK,
  414. };
  415. DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
  416. static const struct clksel timer2_to_7_clk_sel[] = {
  417. { .parent = &tclkin_ck, .rates = div_1_0_rates },
  418. { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
  419. { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
  420. { .parent = NULL },
  421. };
  422. static const char *timer2_to_7_ck_parents[] = {
  423. "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
  424. };
  425. static struct clk timer2_fck;
  426. static struct clk_hw_omap timer2_fck_hw = {
  427. .hw = {
  428. .clk = &timer2_fck,
  429. },
  430. .clkdm_name = "l4ls_clkdm",
  431. .clksel = timer2_to_7_clk_sel,
  432. .clksel_reg = AM33XX_CLKSEL_TIMER2_CLK,
  433. .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
  434. };
  435. DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
  436. static struct clk timer3_fck;
  437. static struct clk_hw_omap timer3_fck_hw = {
  438. .hw = {
  439. .clk = &timer3_fck,
  440. },
  441. .clkdm_name = "l4ls_clkdm",
  442. .clksel = timer2_to_7_clk_sel,
  443. .clksel_reg = AM33XX_CLKSEL_TIMER3_CLK,
  444. .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
  445. };
  446. DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
  447. static struct clk timer4_fck;
  448. static struct clk_hw_omap timer4_fck_hw = {
  449. .hw = {
  450. .clk = &timer4_fck,
  451. },
  452. .clkdm_name = "l4ls_clkdm",
  453. .clksel = timer2_to_7_clk_sel,
  454. .clksel_reg = AM33XX_CLKSEL_TIMER4_CLK,
  455. .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
  456. };
  457. DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
  458. static struct clk timer5_fck;
  459. static struct clk_hw_omap timer5_fck_hw = {
  460. .hw = {
  461. .clk = &timer5_fck,
  462. },
  463. .clkdm_name = "l4ls_clkdm",
  464. .clksel = timer2_to_7_clk_sel,
  465. .clksel_reg = AM33XX_CLKSEL_TIMER5_CLK,
  466. .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
  467. };
  468. DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
  469. static struct clk timer6_fck;
  470. static struct clk_hw_omap timer6_fck_hw = {
  471. .hw = {
  472. .clk = &timer6_fck,
  473. },
  474. .clkdm_name = "l4ls_clkdm",
  475. .clksel = timer2_to_7_clk_sel,
  476. .clksel_reg = AM33XX_CLKSEL_TIMER6_CLK,
  477. .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
  478. };
  479. DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
  480. static struct clk timer7_fck;
  481. static struct clk_hw_omap timer7_fck_hw = {
  482. .hw = {
  483. .clk = &timer7_fck,
  484. },
  485. .clkdm_name = "l4ls_clkdm",
  486. .clksel = timer2_to_7_clk_sel,
  487. .clksel_reg = AM33XX_CLKSEL_TIMER7_CLK,
  488. .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
  489. };
  490. DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
  491. DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
  492. "dpll_core_m5_ck",
  493. &dpll_core_m5_ck,
  494. 0x0,
  495. 1, 2);
  496. static const struct clk_ops cpsw_fck_ops = {
  497. .recalc_rate = &omap2_clksel_recalc,
  498. .get_parent = &omap2_clksel_find_parent_index,
  499. .set_parent = &omap2_clksel_set_parent,
  500. };
  501. static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
  502. { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
  503. { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
  504. { .parent = NULL },
  505. };
  506. static const char *cpsw_cpts_rft_ck_parents[] = {
  507. "dpll_core_m5_ck", "dpll_core_m4_ck",
  508. };
  509. static struct clk cpsw_cpts_rft_clk;
  510. static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
  511. .hw = {
  512. .clk = &cpsw_cpts_rft_clk,
  513. },
  514. .clkdm_name = "cpsw_125mhz_clkdm",
  515. .clksel = cpsw_cpts_rft_clkmux_sel,
  516. .clksel_reg = AM33XX_CM_CPTS_RFT_CLKSEL,
  517. .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
  518. };
  519. DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
  520. /* gpio */
  521. static const char *gpio0_ck_parents[] = {
  522. "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
  523. };
  524. static const struct clksel gpio0_dbclk_mux_sel[] = {
  525. { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
  526. { .parent = &clk_32768_ck, .rates = div_1_1_rates },
  527. { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
  528. { .parent = NULL },
  529. };
  530. static const struct clk_ops gpio_fck_ops = {
  531. .recalc_rate = &omap2_clksel_recalc,
  532. .get_parent = &omap2_clksel_find_parent_index,
  533. .set_parent = &omap2_clksel_set_parent,
  534. .init = &omap2_init_clk_clkdm,
  535. };
  536. static struct clk gpio0_dbclk_mux_ck;
  537. static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
  538. .hw = {
  539. .clk = &gpio0_dbclk_mux_ck,
  540. },
  541. .clkdm_name = "l4_wkup_clkdm",
  542. .clksel = gpio0_dbclk_mux_sel,
  543. .clksel_reg = AM33XX_CLKSEL_GPIO0_DBCLK,
  544. .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
  545. };
  546. DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
  547. DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
  548. AM33XX_CM_WKUP_GPIO0_CLKCTRL,
  549. AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
  550. DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
  551. AM33XX_CM_PER_GPIO1_CLKCTRL,
  552. AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
  553. DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
  554. AM33XX_CM_PER_GPIO2_CLKCTRL,
  555. AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
  556. DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
  557. AM33XX_CM_PER_GPIO3_CLKCTRL,
  558. AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
  559. static const char *pruss_ck_parents[] = {
  560. "l3_gclk", "dpll_disp_m2_ck",
  561. };
  562. static const struct clksel pruss_ocp_clk_mux_sel[] = {
  563. { .parent = &l3_gclk, .rates = div_1_0_rates },
  564. { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
  565. { .parent = NULL },
  566. };
  567. static struct clk pruss_ocp_gclk;
  568. static struct clk_hw_omap pruss_ocp_gclk_hw = {
  569. .hw = {
  570. .clk = &pruss_ocp_gclk,
  571. },
  572. .clkdm_name = "pruss_ocp_clkdm",
  573. .clksel = pruss_ocp_clk_mux_sel,
  574. .clksel_reg = AM33XX_CLKSEL_PRUSS_OCP_CLK,
  575. .clksel_mask = AM33XX_CLKSEL_0_0_MASK,
  576. };
  577. DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
  578. static const char *lcd_ck_parents[] = {
  579. "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
  580. };
  581. static const struct clksel lcd_clk_mux_sel[] = {
  582. { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
  583. { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
  584. { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
  585. { .parent = NULL },
  586. };
  587. static struct clk lcd_gclk;
  588. static struct clk_hw_omap lcd_gclk_hw = {
  589. .hw = {
  590. .clk = &lcd_gclk,
  591. },
  592. .clkdm_name = "lcdc_clkdm",
  593. .clksel = lcd_clk_mux_sel,
  594. .clksel_reg = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
  595. .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
  596. };
  597. DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
  598. gpio_fck_ops, CLK_SET_RATE_PARENT);
  599. DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
  600. static const char *gfx_ck_parents[] = {
  601. "dpll_core_m4_ck", "dpll_per_m2_ck",
  602. };
  603. static const struct clksel gfx_clksel_sel[] = {
  604. { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
  605. { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
  606. { .parent = NULL },
  607. };
  608. static struct clk gfx_fclk_clksel_ck;
  609. static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
  610. .hw = {
  611. .clk = &gfx_fclk_clksel_ck,
  612. },
  613. .clksel = gfx_clksel_sel,
  614. .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
  615. .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
  616. };
  617. DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
  618. static const struct clk_div_table div_1_0_2_1_rates[] = {
  619. { .div = 1, .val = 0, },
  620. { .div = 2, .val = 1, },
  621. { .div = 0 },
  622. };
  623. DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
  624. &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
  625. AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
  626. 0x0, div_1_0_2_1_rates, NULL);
  627. static const char *sysclkout_ck_parents[] = {
  628. "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
  629. "lcd_gclk",
  630. };
  631. static const struct clksel sysclkout_pre_sel[] = {
  632. { .parent = &clk_32768_ck, .rates = div_1_0_rates },
  633. { .parent = &l3_gclk, .rates = div_1_1_rates },
  634. { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
  635. { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
  636. { .parent = &lcd_gclk, .rates = div_1_4_rates },
  637. { .parent = NULL },
  638. };
  639. static struct clk sysclkout_pre_ck;
  640. static struct clk_hw_omap sysclkout_pre_ck_hw = {
  641. .hw = {
  642. .clk = &sysclkout_pre_ck,
  643. },
  644. .clksel = sysclkout_pre_sel,
  645. .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
  646. .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
  647. };
  648. DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
  649. /* Divide by 8 clock rates with default clock is 1/1*/
  650. static const struct clk_div_table div8_rates[] = {
  651. { .div = 1, .val = 0, },
  652. { .div = 2, .val = 1, },
  653. { .div = 3, .val = 2, },
  654. { .div = 4, .val = 3, },
  655. { .div = 5, .val = 4, },
  656. { .div = 6, .val = 5, },
  657. { .div = 7, .val = 6, },
  658. { .div = 8, .val = 7, },
  659. { .div = 0 },
  660. };
  661. DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
  662. 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
  663. AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
  664. DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
  665. AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
  666. static const char *wdt_ck_parents[] = {
  667. "clk_rc32k_ck", "clkdiv32k_ick",
  668. };
  669. static const struct clksel wdt_clkmux_sel[] = {
  670. { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
  671. { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
  672. { .parent = NULL },
  673. };
  674. static struct clk wdt1_fck;
  675. static struct clk_hw_omap wdt1_fck_hw = {
  676. .hw = {
  677. .clk = &wdt1_fck,
  678. },
  679. .clkdm_name = "l4_wkup_clkdm",
  680. .clksel = wdt_clkmux_sel,
  681. .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
  682. .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
  683. };
  684. DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
  685. /*
  686. * clkdev
  687. */
  688. static struct omap_clk am33xx_clks[] = {
  689. CLK(NULL, "clk_32768_ck", &clk_32768_ck),
  690. CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
  691. CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
  692. CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
  693. CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
  694. CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
  695. CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
  696. CLK(NULL, "tclkin_ck", &tclkin_ck),
  697. CLK(NULL, "dpll_core_ck", &dpll_core_ck),
  698. CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
  699. CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
  700. CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
  701. CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
  702. CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
  703. CLK("cpu0", NULL, &dpll_mpu_ck),
  704. CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
  705. CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
  706. CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
  707. CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
  708. CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
  709. CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
  710. CLK(NULL, "dpll_per_ck", &dpll_per_ck),
  711. CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
  712. CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
  713. CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
  714. CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
  715. CLK(NULL, "cefuse_fck", &cefuse_fck),
  716. CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
  717. CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
  718. CLK(NULL, "dcan0_fck", &dcan0_fck),
  719. CLK("481cc000.d_can", NULL, &dcan0_fck),
  720. CLK(NULL, "dcan1_fck", &dcan1_fck),
  721. CLK("481d0000.d_can", NULL, &dcan1_fck),
  722. CLK(NULL, "debugss_ick", &debugss_ick),
  723. CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
  724. CLK(NULL, "mcasp0_fck", &mcasp0_fck),
  725. CLK(NULL, "mcasp1_fck", &mcasp1_fck),
  726. CLK(NULL, "mmu_fck", &mmu_fck),
  727. CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
  728. CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
  729. CLK(NULL, "sha0_fck", &sha0_fck),
  730. CLK(NULL, "aes0_fck", &aes0_fck),
  731. CLK(NULL, "timer1_fck", &timer1_fck),
  732. CLK(NULL, "timer2_fck", &timer2_fck),
  733. CLK(NULL, "timer3_fck", &timer3_fck),
  734. CLK(NULL, "timer4_fck", &timer4_fck),
  735. CLK(NULL, "timer5_fck", &timer5_fck),
  736. CLK(NULL, "timer6_fck", &timer6_fck),
  737. CLK(NULL, "timer7_fck", &timer7_fck),
  738. CLK(NULL, "usbotg_fck", &usbotg_fck),
  739. CLK(NULL, "ieee5000_fck", &ieee5000_fck),
  740. CLK(NULL, "wdt1_fck", &wdt1_fck),
  741. CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
  742. CLK(NULL, "l3_gclk", &l3_gclk),
  743. CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
  744. CLK(NULL, "l4hs_gclk", &l4hs_gclk),
  745. CLK(NULL, "l3s_gclk", &l3s_gclk),
  746. CLK(NULL, "l4fw_gclk", &l4fw_gclk),
  747. CLK(NULL, "l4ls_gclk", &l4ls_gclk),
  748. CLK(NULL, "clk_24mhz", &clk_24mhz),
  749. CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
  750. CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
  751. CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
  752. CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
  753. CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
  754. CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
  755. CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
  756. CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
  757. CLK(NULL, "lcd_gclk", &lcd_gclk),
  758. CLK(NULL, "mmc_clk", &mmc_clk),
  759. CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
  760. CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
  761. CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
  762. CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
  763. CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
  764. CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
  765. };
  766. static const char *enable_init_clks[] = {
  767. "dpll_ddr_m2_ck",
  768. "dpll_mpu_m2_ck",
  769. "l3_gclk",
  770. "l4hs_gclk",
  771. "l4fw_gclk",
  772. "l4ls_gclk",
  773. };
  774. int __init am33xx_clk_init(void)
  775. {
  776. if (soc_is_am33xx())
  777. cpu_mask = RATE_IN_AM33XX;
  778. omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
  779. omap2_clk_disable_autoidle_all();
  780. omap2_clk_enable_init_clocks(enable_init_clks,
  781. ARRAY_SIZE(enable_init_clks));
  782. /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
  783. * physically present, in such a case HWMOD enabling of
  784. * clock would be failure with default parent. And timer
  785. * probe thinks clock is already enabled, this leads to
  786. * crash upon accessing timer 3 & 6 registers in probe.
  787. * Fix by setting parent of both these timers to master
  788. * oscillator clock.
  789. */
  790. clk_set_parent(&timer3_fck, &sys_clkin_ck);
  791. clk_set_parent(&timer6_fck, &sys_clkin_ck);
  792. /*
  793. * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
  794. * the design/spec, so as a result, for example, timer which supposed
  795. * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
  796. * not expected by any use-case, so change WDT1 clock source to PRCM
  797. * 32KHz clock.
  798. */
  799. clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
  800. return 0;
  801. }