mach-imx6q.c 6.2 KB

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  1. /*
  2. * Copyright 2011-2013 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clkdev.h>
  14. #include <linux/clocksource.h>
  15. #include <linux/cpu.h>
  16. #include <linux/delay.h>
  17. #include <linux/export.h>
  18. #include <linux/init.h>
  19. #include <linux/io.h>
  20. #include <linux/irq.h>
  21. #include <linux/irqchip.h>
  22. #include <linux/of.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/of_platform.h>
  26. #include <linux/opp.h>
  27. #include <linux/phy.h>
  28. #include <linux/regmap.h>
  29. #include <linux/micrel_phy.h>
  30. #include <linux/mfd/syscon.h>
  31. #include <asm/hardware/cache-l2x0.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach/map.h>
  34. #include <asm/system_misc.h>
  35. #include "common.h"
  36. #include "cpuidle.h"
  37. #include "hardware.h"
  38. static u32 chip_revision;
  39. int imx6q_revision(void)
  40. {
  41. return chip_revision;
  42. }
  43. static void __init imx6q_init_revision(void)
  44. {
  45. u32 rev = imx_anatop_get_digprog();
  46. switch (rev & 0xff) {
  47. case 0:
  48. chip_revision = IMX_CHIP_REVISION_1_0;
  49. break;
  50. case 1:
  51. chip_revision = IMX_CHIP_REVISION_1_1;
  52. break;
  53. case 2:
  54. chip_revision = IMX_CHIP_REVISION_1_2;
  55. break;
  56. default:
  57. chip_revision = IMX_CHIP_REVISION_UNKNOWN;
  58. }
  59. mxc_set_cpu_type(rev >> 16 & 0xff);
  60. }
  61. static void imx6q_restart(char mode, const char *cmd)
  62. {
  63. struct device_node *np;
  64. void __iomem *wdog_base;
  65. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
  66. wdog_base = of_iomap(np, 0);
  67. if (!wdog_base)
  68. goto soft;
  69. imx_src_prepare_restart();
  70. /* enable wdog */
  71. writew_relaxed(1 << 2, wdog_base);
  72. /* write twice to ensure the request will not get ignored */
  73. writew_relaxed(1 << 2, wdog_base);
  74. /* wait for reset to assert ... */
  75. mdelay(500);
  76. pr_err("Watchdog reset failed to assert reset\n");
  77. /* delay to allow the serial port to show the message */
  78. mdelay(50);
  79. soft:
  80. /* we'll take a jump through zero as a poor second */
  81. soft_restart(0);
  82. }
  83. /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
  84. static int ksz9021rn_phy_fixup(struct phy_device *phydev)
  85. {
  86. if (IS_BUILTIN(CONFIG_PHYLIB)) {
  87. /* min rx data delay */
  88. phy_write(phydev, 0x0b, 0x8105);
  89. phy_write(phydev, 0x0c, 0x0000);
  90. /* max rx/tx clock delay, min rx/tx control delay */
  91. phy_write(phydev, 0x0b, 0x8104);
  92. phy_write(phydev, 0x0c, 0xf0f0);
  93. phy_write(phydev, 0x0b, 0x104);
  94. }
  95. return 0;
  96. }
  97. static void __init imx6q_sabrelite_cko1_setup(void)
  98. {
  99. struct clk *cko1_sel, *ahb, *cko1;
  100. unsigned long rate;
  101. cko1_sel = clk_get_sys(NULL, "cko1_sel");
  102. ahb = clk_get_sys(NULL, "ahb");
  103. cko1 = clk_get_sys(NULL, "cko1");
  104. if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
  105. pr_err("cko1 setup failed!\n");
  106. goto put_clk;
  107. }
  108. clk_set_parent(cko1_sel, ahb);
  109. rate = clk_round_rate(cko1, 16000000);
  110. clk_set_rate(cko1, rate);
  111. put_clk:
  112. if (!IS_ERR(cko1_sel))
  113. clk_put(cko1_sel);
  114. if (!IS_ERR(ahb))
  115. clk_put(ahb);
  116. if (!IS_ERR(cko1))
  117. clk_put(cko1);
  118. }
  119. static void __init imx6q_sabrelite_init(void)
  120. {
  121. if (IS_BUILTIN(CONFIG_PHYLIB))
  122. phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
  123. ksz9021rn_phy_fixup);
  124. imx6q_sabrelite_cko1_setup();
  125. }
  126. static void __init imx6q_1588_init(void)
  127. {
  128. struct regmap *gpr;
  129. gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
  130. if (!IS_ERR(gpr))
  131. regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
  132. else
  133. pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
  134. }
  135. static void __init imx6q_usb_init(void)
  136. {
  137. imx_anatop_usb_chrg_detect_disable();
  138. }
  139. static void __init imx6q_init_machine(void)
  140. {
  141. if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
  142. imx6q_sabrelite_init();
  143. of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
  144. imx_anatop_init();
  145. imx6q_pm_init();
  146. imx6q_usb_init();
  147. imx6q_1588_init();
  148. }
  149. #define OCOTP_CFG3 0x440
  150. #define OCOTP_CFG3_SPEED_SHIFT 16
  151. #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
  152. static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
  153. {
  154. struct device_node *np;
  155. void __iomem *base;
  156. u32 val;
  157. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
  158. if (!np) {
  159. pr_warn("failed to find ocotp node\n");
  160. return;
  161. }
  162. base = of_iomap(np, 0);
  163. if (!base) {
  164. pr_warn("failed to map ocotp\n");
  165. goto put_node;
  166. }
  167. val = readl_relaxed(base + OCOTP_CFG3);
  168. val >>= OCOTP_CFG3_SPEED_SHIFT;
  169. if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
  170. if (opp_disable(cpu_dev, 1200000000))
  171. pr_warn("failed to disable 1.2 GHz OPP\n");
  172. put_node:
  173. of_node_put(np);
  174. }
  175. static void __init imx6q_opp_init(struct device *cpu_dev)
  176. {
  177. struct device_node *np;
  178. np = of_find_node_by_path("/cpus/cpu@0");
  179. if (!np) {
  180. pr_warn("failed to find cpu0 node\n");
  181. return;
  182. }
  183. cpu_dev->of_node = np;
  184. if (of_init_opp_table(cpu_dev)) {
  185. pr_warn("failed to init OPP table\n");
  186. goto put_node;
  187. }
  188. imx6q_opp_check_1p2ghz(cpu_dev);
  189. put_node:
  190. of_node_put(np);
  191. }
  192. static struct platform_device imx6q_cpufreq_pdev = {
  193. .name = "imx6q-cpufreq",
  194. };
  195. static void __init imx6q_init_late(void)
  196. {
  197. /*
  198. * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
  199. * to run cpuidle on them.
  200. */
  201. if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
  202. imx6q_cpuidle_init();
  203. if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
  204. imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
  205. platform_device_register(&imx6q_cpufreq_pdev);
  206. }
  207. }
  208. static void __init imx6q_map_io(void)
  209. {
  210. debug_ll_io_init();
  211. imx_scu_map_io();
  212. }
  213. static void __init imx6q_init_irq(void)
  214. {
  215. imx6q_init_revision();
  216. l2x0_of_init(0, ~0UL);
  217. imx_src_init();
  218. imx_gpc_init();
  219. irqchip_init();
  220. }
  221. static void __init imx6q_timer_init(void)
  222. {
  223. mx6q_clocks_init();
  224. clocksource_of_init();
  225. imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
  226. imx6q_revision());
  227. }
  228. static const char *imx6q_dt_compat[] __initdata = {
  229. "fsl,imx6dl",
  230. "fsl,imx6q",
  231. NULL,
  232. };
  233. DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
  234. .smp = smp_ops(imx_smp_ops),
  235. .map_io = imx6q_map_io,
  236. .init_irq = imx6q_init_irq,
  237. .init_time = imx6q_timer_init,
  238. .init_machine = imx6q_init_machine,
  239. .init_late = imx6q_init_late,
  240. .dt_compat = imx6q_dt_compat,
  241. .restart = imx6q_restart,
  242. MACHINE_END