r8a7790.dtsi 1.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
  1. /*
  2. * Device Tree Source for the r8a7790 SoC
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. / {
  11. compatible = "renesas,r8a7790";
  12. interrupt-parent = <&gic>;
  13. #address-cells = <2>;
  14. #size-cells = <2>;
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. cpu0: cpu@0 {
  19. device_type = "cpu";
  20. compatible = "arm,cortex-a15";
  21. reg = <0>;
  22. clock-frequency = <1300000000>;
  23. };
  24. };
  25. gic: interrupt-controller@f1001000 {
  26. compatible = "arm,cortex-a15-gic";
  27. #interrupt-cells = <3>;
  28. #address-cells = <0>;
  29. interrupt-controller;
  30. reg = <0 0xf1001000 0 0x1000>,
  31. <0 0xf1002000 0 0x1000>,
  32. <0 0xf1004000 0 0x2000>,
  33. <0 0xf1006000 0 0x2000>;
  34. interrupts = <1 9 0xf04>;
  35. gic-cpuif@4 {
  36. compatible = "arm,gic-cpuif";
  37. cpuif-id = <4>;
  38. cpu = <&cpu0>;
  39. };
  40. };
  41. timer {
  42. compatible = "arm,armv7-timer";
  43. interrupts = <1 13 0xf08>,
  44. <1 14 0xf08>,
  45. <1 11 0xf08>,
  46. <1 10 0xf08>;
  47. };
  48. irqc0: interrupt-controller@e61c0000 {
  49. compatible = "renesas,irqc";
  50. #interrupt-cells = <2>;
  51. interrupt-controller;
  52. reg = <0 0xe61c0000 0 0x200>;
  53. interrupt-parent = <&gic>;
  54. interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
  55. };
  56. };