imx6dl.dtsi 4.8 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. */
  9. #include "imx6qdl.dtsi"
  10. #include "imx6dl-pinfunc.h"
  11. / {
  12. cpus {
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. cpu@0 {
  16. compatible = "arm,cortex-a9";
  17. reg = <0>;
  18. next-level-cache = <&L2>;
  19. };
  20. cpu@1 {
  21. compatible = "arm,cortex-a9";
  22. reg = <1>;
  23. next-level-cache = <&L2>;
  24. };
  25. };
  26. soc {
  27. aips1: aips-bus@02000000 {
  28. iomuxc: iomuxc@020e0000 {
  29. compatible = "fsl,imx6dl-iomuxc";
  30. reg = <0x020e0000 0x4000>;
  31. enet {
  32. pinctrl_enet_1: enetgrp-1 {
  33. fsl,pins = <
  34. MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  35. MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  36. MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  37. MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  38. MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  39. MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  40. MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  41. MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  42. MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  43. MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  44. MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  45. MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  46. MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  47. MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  48. MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  49. MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  50. >;
  51. };
  52. pinctrl_enet_2: enetgrp-2 {
  53. fsl,pins = <
  54. MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
  55. MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
  56. MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
  57. MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
  58. MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
  59. MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
  60. MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
  61. MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
  62. MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
  63. MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
  64. MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
  65. MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
  66. MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
  67. MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
  68. MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
  69. >;
  70. };
  71. };
  72. uart1 {
  73. pinctrl_uart1_1: uart1grp-1 {
  74. fsl,pins = <
  75. MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
  76. MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  77. >;
  78. };
  79. };
  80. uart4 {
  81. pinctrl_uart4_1: uart4grp-1 {
  82. fsl,pins = <
  83. MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
  84. MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
  85. >;
  86. };
  87. };
  88. usbotg {
  89. pinctrl_usbotg_2: usbotggrp-2 {
  90. fsl,pins = <
  91. MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
  92. >;
  93. };
  94. };
  95. usdhc2 {
  96. pinctrl_usdhc2_1: usdhc2grp-1 {
  97. fsl,pins = <
  98. MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
  99. MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
  100. MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
  101. MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
  102. MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
  103. MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
  104. MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
  105. MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
  106. MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
  107. MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
  108. >;
  109. };
  110. };
  111. usdhc3 {
  112. pinctrl_usdhc3_1: usdhc3grp-1 {
  113. fsl,pins = <
  114. MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
  115. MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
  116. MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  117. MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  118. MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  119. MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  120. MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
  121. MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
  122. MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
  123. MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
  124. >;
  125. };
  126. pinctrl_usdhc3_2: usdhc3grp_2 {
  127. fsl,pins = <
  128. MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
  129. MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
  130. MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
  131. MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
  132. MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
  133. MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
  134. >;
  135. };
  136. };
  137. };
  138. pxp: pxp@020f0000 {
  139. reg = <0x020f0000 0x4000>;
  140. interrupts = <0 98 0x04>;
  141. };
  142. epdc: epdc@020f4000 {
  143. reg = <0x020f4000 0x4000>;
  144. interrupts = <0 97 0x04>;
  145. };
  146. lcdif: lcdif@020f8000 {
  147. reg = <0x020f8000 0x4000>;
  148. interrupts = <0 39 0x04>;
  149. };
  150. };
  151. aips2: aips-bus@02100000 {
  152. i2c4: i2c@021f8000 {
  153. #address-cells = <1>;
  154. #size-cells = <0>;
  155. compatible = "fsl,imx1-i2c";
  156. reg = <0x021f8000 0x4000>;
  157. interrupts = <0 35 0x04>;
  158. status = "disabled";
  159. };
  160. };
  161. };
  162. };