linux-vybrid_public/arch/arm/boot/dts/imx53-mba53.dts

/*
 * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx53-tqma53.dtsi"

/ {
	model = "TQ MBa53 starter kit";
	compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
};

&iomuxc {
	lvds1 {
		pinctrl_lvds1_1: lvds1-grp1 {
			fsl,pins = <
				MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
				MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
				MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
				MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
				MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
			>;
		};

		pinctrl_lvds1_2: lvds1-grp2 {
			fsl,pins = <
				MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
				MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
				MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
				MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
				MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
			>;
		};
	};

	disp1 {
		pinctrl_disp1_1: disp1-grp1 {
			fsl,pins = <
				MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x10000 /* DISP1_DRDY */
				MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x10000 /* DISP1_HSYNC */
				MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x10000 /* DISP1_VSYNC */
				MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
				MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
				MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
				MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
				MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
				MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
				MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
				MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
				MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
				MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
				MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
				MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
				MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
				MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
				MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x10000
				MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x10000
				MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x10000
				MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x10000
				MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x10000
				MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x10000
				MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x10000
				MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x10000
				MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x10000
				MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x10000
			>;
		};
	};
};

&cspi {
	status = "okay";
};

&i2c2 {
	codec: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
	};

	expander: pca9554@20 {
		compatible = "pca9554";
		reg = <0x20>;
		interrupts = <109>;
	};

	sensor2: lm75@49 {
		compatible = "lm75";
		reg = <0x49>;
	};
};

&fec {
	status = "okay";
};

&esdhc2 {
	status = "okay";
};

&uart3 {
	status = "okay";
};

&ecspi1 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&can1 {
	status = "okay";
};

&can2 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};