imx23.dtsi 13 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. serial0 = &auart0;
  19. serial1 = &auart1;
  20. };
  21. cpus {
  22. cpu@0 {
  23. compatible = "arm,arm926ejs";
  24. };
  25. };
  26. apb@80000000 {
  27. compatible = "simple-bus";
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. reg = <0x80000000 0x80000>;
  31. ranges;
  32. apbh@80000000 {
  33. compatible = "simple-bus";
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. reg = <0x80000000 0x40000>;
  37. ranges;
  38. icoll: interrupt-controller@80000000 {
  39. compatible = "fsl,imx23-icoll", "fsl,icoll";
  40. interrupt-controller;
  41. #interrupt-cells = <1>;
  42. reg = <0x80000000 0x2000>;
  43. };
  44. dma_apbh: dma-apbh@80004000 {
  45. compatible = "fsl,imx23-dma-apbh";
  46. reg = <0x80004000 0x2000>;
  47. interrupts = <0 14 20 0
  48. 13 13 13 13>;
  49. interrupt-names = "empty", "ssp0", "ssp1", "empty",
  50. "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  51. #dma-cells = <1>;
  52. dma-channels = <8>;
  53. clocks = <&clks 15>;
  54. };
  55. ecc@80008000 {
  56. reg = <0x80008000 0x2000>;
  57. status = "disabled";
  58. };
  59. gpmi-nand@8000c000 {
  60. compatible = "fsl,imx23-gpmi-nand";
  61. #address-cells = <1>;
  62. #size-cells = <1>;
  63. reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
  64. reg-names = "gpmi-nand", "bch";
  65. interrupts = <13>, <56>;
  66. interrupt-names = "gpmi-dma", "bch";
  67. clocks = <&clks 34>;
  68. clock-names = "gpmi_io";
  69. dmas = <&dma_apbh 4>;
  70. dma-names = "rx-tx";
  71. fsl,gpmi-dma-channel = <4>;
  72. status = "disabled";
  73. };
  74. ssp0: ssp@80010000 {
  75. reg = <0x80010000 0x2000>;
  76. interrupts = <15 14>;
  77. clocks = <&clks 33>;
  78. dmas = <&dma_apbh 1>;
  79. dma-names = "rx-tx";
  80. fsl,ssp-dma-channel = <1>;
  81. status = "disabled";
  82. };
  83. etm@80014000 {
  84. reg = <0x80014000 0x2000>;
  85. status = "disabled";
  86. };
  87. pinctrl@80018000 {
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. compatible = "fsl,imx23-pinctrl", "simple-bus";
  91. reg = <0x80018000 0x2000>;
  92. gpio0: gpio@0 {
  93. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  94. interrupts = <16>;
  95. gpio-controller;
  96. #gpio-cells = <2>;
  97. interrupt-controller;
  98. #interrupt-cells = <2>;
  99. };
  100. gpio1: gpio@1 {
  101. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  102. interrupts = <17>;
  103. gpio-controller;
  104. #gpio-cells = <2>;
  105. interrupt-controller;
  106. #interrupt-cells = <2>;
  107. };
  108. gpio2: gpio@2 {
  109. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  110. interrupts = <18>;
  111. gpio-controller;
  112. #gpio-cells = <2>;
  113. interrupt-controller;
  114. #interrupt-cells = <2>;
  115. };
  116. duart_pins_a: duart@0 {
  117. reg = <0>;
  118. fsl,pinmux-ids = <
  119. 0x11a2 /* MX23_PAD_PWM0__DUART_RX */
  120. 0x11b2 /* MX23_PAD_PWM1__DUART_TX */
  121. >;
  122. fsl,drive-strength = <0>;
  123. fsl,voltage = <1>;
  124. fsl,pull-up = <0>;
  125. };
  126. auart0_pins_a: auart0@0 {
  127. reg = <0>;
  128. fsl,pinmux-ids = <
  129. 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
  130. 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
  131. 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
  132. 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
  133. >;
  134. fsl,drive-strength = <0>;
  135. fsl,voltage = <1>;
  136. fsl,pull-up = <0>;
  137. };
  138. auart0_2pins_a: auart0-2pins@0 {
  139. reg = <0>;
  140. fsl,pinmux-ids = <
  141. 0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
  142. 0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
  143. >;
  144. fsl,drive-strength = <0>;
  145. fsl,voltage = <1>;
  146. fsl,pull-up = <0>;
  147. };
  148. gpmi_pins_a: gpmi-nand@0 {
  149. reg = <0>;
  150. fsl,pinmux-ids = <
  151. 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
  152. 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
  153. 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
  154. 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
  155. 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
  156. 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
  157. 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
  158. 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
  159. 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
  160. 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
  161. 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
  162. 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
  163. 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
  164. 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
  165. 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
  166. 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
  167. 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
  168. >;
  169. fsl,drive-strength = <0>;
  170. fsl,voltage = <1>;
  171. fsl,pull-up = <0>;
  172. };
  173. gpmi_pins_fixup: gpmi-pins-fixup {
  174. fsl,pinmux-ids = <
  175. 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
  176. 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
  177. 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
  178. >;
  179. fsl,drive-strength = <2>;
  180. };
  181. mmc0_4bit_pins_a: mmc0-4bit@0 {
  182. reg = <0>;
  183. fsl,pinmux-ids = <
  184. 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
  185. 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
  186. 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
  187. 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
  188. 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
  189. 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
  190. >;
  191. fsl,drive-strength = <1>;
  192. fsl,voltage = <1>;
  193. fsl,pull-up = <1>;
  194. };
  195. mmc0_8bit_pins_a: mmc0-8bit@0 {
  196. reg = <0>;
  197. fsl,pinmux-ids = <
  198. 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
  199. 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
  200. 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
  201. 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
  202. 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
  203. 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
  204. 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
  205. 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
  206. 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
  207. 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
  208. 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
  209. >;
  210. fsl,drive-strength = <1>;
  211. fsl,voltage = <1>;
  212. fsl,pull-up = <1>;
  213. };
  214. mmc0_pins_fixup: mmc0-pins-fixup {
  215. fsl,pinmux-ids = <
  216. 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
  217. 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
  218. >;
  219. fsl,pull-up = <0>;
  220. };
  221. pwm2_pins_a: pwm2@0 {
  222. reg = <0>;
  223. fsl,pinmux-ids = <
  224. 0x11c0 /* MX23_PAD_PWM2__PWM2 */
  225. >;
  226. fsl,drive-strength = <0>;
  227. fsl,voltage = <1>;
  228. fsl,pull-up = <0>;
  229. };
  230. lcdif_24bit_pins_a: lcdif-24bit@0 {
  231. reg = <0>;
  232. fsl,pinmux-ids = <
  233. 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
  234. 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
  235. 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
  236. 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
  237. 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
  238. 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
  239. 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
  240. 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
  241. 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
  242. 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
  243. 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
  244. 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
  245. 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
  246. 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
  247. 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
  248. 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
  249. 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
  250. 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
  251. 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
  252. 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
  253. 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
  254. 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
  255. 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
  256. 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
  257. 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
  258. 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
  259. 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
  260. 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
  261. >;
  262. fsl,drive-strength = <0>;
  263. fsl,voltage = <1>;
  264. fsl,pull-up = <0>;
  265. };
  266. spi2_pins_a: spi2@0 {
  267. reg = <0>;
  268. fsl,pinmux-ids = <
  269. 0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
  270. 0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
  271. 0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
  272. 0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
  273. >;
  274. fsl,drive-strength = <1>;
  275. fsl,voltage = <1>;
  276. fsl,pull-up = <1>;
  277. };
  278. };
  279. digctl@8001c000 {
  280. compatible = "fsl,imx23-digctl";
  281. reg = <0x8001c000 2000>;
  282. status = "disabled";
  283. };
  284. emi@80020000 {
  285. reg = <0x80020000 0x2000>;
  286. status = "disabled";
  287. };
  288. dma_apbx: dma-apbx@80024000 {
  289. compatible = "fsl,imx23-dma-apbx";
  290. reg = <0x80024000 0x2000>;
  291. interrupts = <7 5 9 26
  292. 19 0 25 23
  293. 60 58 9 0
  294. 0 0 0 0>;
  295. interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
  296. "saif0", "empty", "auart0-rx", "auart0-tx",
  297. "auart1-rx", "auart1-tx", "saif1", "empty",
  298. "empty", "empty", "empty", "empty";
  299. #dma-cells = <1>;
  300. dma-channels = <16>;
  301. clocks = <&clks 16>;
  302. };
  303. dcp@80028000 {
  304. reg = <0x80028000 0x2000>;
  305. status = "disabled";
  306. };
  307. pxp@8002a000 {
  308. reg = <0x8002a000 0x2000>;
  309. status = "disabled";
  310. };
  311. ocotp@8002c000 {
  312. compatible = "fsl,ocotp";
  313. reg = <0x8002c000 0x2000>;
  314. status = "disabled";
  315. };
  316. axi-ahb@8002e000 {
  317. reg = <0x8002e000 0x2000>;
  318. status = "disabled";
  319. };
  320. lcdif@80030000 {
  321. compatible = "fsl,imx23-lcdif";
  322. reg = <0x80030000 2000>;
  323. interrupts = <46 45>;
  324. clocks = <&clks 38>;
  325. status = "disabled";
  326. };
  327. ssp1: ssp@80034000 {
  328. reg = <0x80034000 0x2000>;
  329. interrupts = <2 20>;
  330. clocks = <&clks 33>;
  331. dmas = <&dma_apbh 2>;
  332. dma-names = "rx-tx";
  333. fsl,ssp-dma-channel = <2>;
  334. status = "disabled";
  335. };
  336. tvenc@80038000 {
  337. reg = <0x80038000 0x2000>;
  338. status = "disabled";
  339. };
  340. };
  341. apbx@80040000 {
  342. compatible = "simple-bus";
  343. #address-cells = <1>;
  344. #size-cells = <1>;
  345. reg = <0x80040000 0x40000>;
  346. ranges;
  347. clks: clkctrl@80040000 {
  348. compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
  349. reg = <0x80040000 0x2000>;
  350. #clock-cells = <1>;
  351. };
  352. saif0: saif@80042000 {
  353. reg = <0x80042000 0x2000>;
  354. dmas = <&dma_apbx 4>;
  355. dma-names = "rx-tx";
  356. status = "disabled";
  357. };
  358. power@80044000 {
  359. reg = <0x80044000 0x2000>;
  360. status = "disabled";
  361. };
  362. saif1: saif@80046000 {
  363. reg = <0x80046000 0x2000>;
  364. dmas = <&dma_apbx 10>;
  365. dma-names = "rx-tx";
  366. status = "disabled";
  367. };
  368. audio-out@80048000 {
  369. reg = <0x80048000 0x2000>;
  370. dmas = <&dma_apbx 1>;
  371. dma-names = "tx";
  372. status = "disabled";
  373. };
  374. audio-in@8004c000 {
  375. reg = <0x8004c000 0x2000>;
  376. dmas = <&dma_apbx 0>;
  377. dma-names = "rx";
  378. status = "disabled";
  379. };
  380. lradc@80050000 {
  381. compatible = "fsl,imx23-lradc";
  382. reg = <0x80050000 0x2000>;
  383. interrupts = <36 37 38 39 40 41 42 43 44>;
  384. status = "disabled";
  385. };
  386. spdif@80054000 {
  387. reg = <0x80054000 2000>;
  388. dmas = <&dma_apbx 2>;
  389. dma-names = "tx";
  390. status = "disabled";
  391. };
  392. i2c@80058000 {
  393. reg = <0x80058000 0x2000>;
  394. dmas = <&dma_apbx 3>;
  395. dma-names = "rx-tx";
  396. status = "disabled";
  397. };
  398. rtc@8005c000 {
  399. compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
  400. reg = <0x8005c000 0x2000>;
  401. interrupts = <22>;
  402. };
  403. pwm: pwm@80064000 {
  404. compatible = "fsl,imx23-pwm";
  405. reg = <0x80064000 0x2000>;
  406. clocks = <&clks 30>;
  407. #pwm-cells = <2>;
  408. fsl,pwm-number = <5>;
  409. status = "disabled";
  410. };
  411. timrot@80068000 {
  412. compatible = "fsl,imx23-timrot", "fsl,timrot";
  413. reg = <0x80068000 0x2000>;
  414. interrupts = <28 29 30 31>;
  415. clocks = <&clks 28>;
  416. };
  417. auart0: serial@8006c000 {
  418. compatible = "fsl,imx23-auart";
  419. reg = <0x8006c000 0x2000>;
  420. interrupts = <24 25 23>;
  421. clocks = <&clks 32>;
  422. dmas = <&dma_apbx 6>, <&dma_apbx 7>;
  423. dma-names = "rx", "tx";
  424. status = "disabled";
  425. };
  426. auart1: serial@8006e000 {
  427. compatible = "fsl,imx23-auart";
  428. reg = <0x8006e000 0x2000>;
  429. interrupts = <59 60 58>;
  430. clocks = <&clks 32>;
  431. dmas = <&dma_apbx 8>, <&dma_apbx 9>;
  432. dma-names = "rx", "tx";
  433. status = "disabled";
  434. };
  435. duart: serial@80070000 {
  436. compatible = "arm,pl011", "arm,primecell";
  437. reg = <0x80070000 0x2000>;
  438. interrupts = <0>;
  439. clocks = <&clks 32>, <&clks 16>;
  440. clock-names = "uart", "apb_pclk";
  441. status = "disabled";
  442. };
  443. usbphy0: usbphy@8007c000 {
  444. compatible = "fsl,imx23-usbphy";
  445. reg = <0x8007c000 0x2000>;
  446. clocks = <&clks 41>;
  447. status = "disabled";
  448. };
  449. };
  450. };
  451. ahb@80080000 {
  452. compatible = "simple-bus";
  453. #address-cells = <1>;
  454. #size-cells = <1>;
  455. reg = <0x80080000 0x80000>;
  456. ranges;
  457. usb0: usb@80080000 {
  458. compatible = "fsl,imx23-usb", "fsl,imx27-usb";
  459. reg = <0x80080000 0x40000>;
  460. interrupts = <11>;
  461. fsl,usbphy = <&usbphy0>;
  462. clocks = <&clks 40>;
  463. status = "disabled";
  464. };
  465. };
  466. };