exynos5250.dtsi 14 KB

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  1. /*
  2. * SAMSUNG EXYNOS5250 SoC device tree source
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
  8. * EXYNOS5250 based board files can include this file and provide
  9. * values for board specfic bindings.
  10. *
  11. * Note: This file does not include device nodes for all the controllers in
  12. * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13. * additional nodes can be added to this file.
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License version 2 as
  17. * published by the Free Software Foundation.
  18. */
  19. /include/ "skeleton.dtsi"
  20. /include/ "exynos5250-pinctrl.dtsi"
  21. / {
  22. compatible = "samsung,exynos5250";
  23. interrupt-parent = <&gic>;
  24. aliases {
  25. spi0 = &spi_0;
  26. spi1 = &spi_1;
  27. spi2 = &spi_2;
  28. gsc0 = &gsc_0;
  29. gsc1 = &gsc_1;
  30. gsc2 = &gsc_2;
  31. gsc3 = &gsc_3;
  32. mshc0 = &dwmmc_0;
  33. mshc1 = &dwmmc_1;
  34. mshc2 = &dwmmc_2;
  35. mshc3 = &dwmmc_3;
  36. i2c0 = &i2c_0;
  37. i2c1 = &i2c_1;
  38. i2c2 = &i2c_2;
  39. i2c3 = &i2c_3;
  40. i2c4 = &i2c_4;
  41. i2c5 = &i2c_5;
  42. i2c6 = &i2c_6;
  43. i2c7 = &i2c_7;
  44. i2c8 = &i2c_8;
  45. pinctrl0 = &pinctrl_0;
  46. pinctrl1 = &pinctrl_1;
  47. pinctrl2 = &pinctrl_2;
  48. pinctrl3 = &pinctrl_3;
  49. };
  50. chipid@10000000 {
  51. compatible = "samsung,exynos4210-chipid";
  52. reg = <0x10000000 0x100>;
  53. };
  54. pd_gsc: gsc-power-domain@0x10044000 {
  55. compatible = "samsung,exynos4210-pd";
  56. reg = <0x10044000 0x20>;
  57. };
  58. pd_mfc: mfc-power-domain@0x10044040 {
  59. compatible = "samsung,exynos4210-pd";
  60. reg = <0x10044040 0x20>;
  61. };
  62. clock: clock-controller@0x10010000 {
  63. compatible = "samsung,exynos5250-clock";
  64. reg = <0x10010000 0x30000>;
  65. #clock-cells = <1>;
  66. };
  67. gic:interrupt-controller@10481000 {
  68. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  69. #interrupt-cells = <3>;
  70. interrupt-controller;
  71. reg = <0x10481000 0x1000>,
  72. <0x10482000 0x1000>,
  73. <0x10484000 0x2000>,
  74. <0x10486000 0x2000>;
  75. interrupts = <1 9 0xf04>;
  76. };
  77. timer {
  78. compatible = "arm,armv7-timer";
  79. interrupts = <1 13 0xf08>,
  80. <1 14 0xf08>,
  81. <1 11 0xf08>,
  82. <1 10 0xf08>;
  83. };
  84. combiner:interrupt-controller@10440000 {
  85. compatible = "samsung,exynos4210-combiner";
  86. #interrupt-cells = <2>;
  87. interrupt-controller;
  88. samsung,combiner-nr = <32>;
  89. reg = <0x10440000 0x1000>;
  90. interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  91. <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  92. <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  93. <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  94. <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
  95. <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
  96. <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
  97. <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
  98. };
  99. mct@101C0000 {
  100. compatible = "samsung,exynos4210-mct";
  101. reg = <0x101C0000 0x800>;
  102. interrupt-controller;
  103. #interrups-cells = <2>;
  104. interrupt-parent = <&mct_map>;
  105. interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
  106. <4 0>, <5 0>;
  107. clocks = <&clock 1>, <&clock 335>;
  108. clock-names = "fin_pll", "mct";
  109. mct_map: mct-map {
  110. #interrupt-cells = <2>;
  111. #address-cells = <0>;
  112. #size-cells = <0>;
  113. interrupt-map = <0x0 0 &combiner 23 3>,
  114. <0x1 0 &combiner 23 4>,
  115. <0x2 0 &combiner 25 2>,
  116. <0x3 0 &combiner 25 3>,
  117. <0x4 0 &gic 0 120 0>,
  118. <0x5 0 &gic 0 121 0>;
  119. };
  120. };
  121. pmu {
  122. compatible = "arm,cortex-a15-pmu";
  123. interrupt-parent = <&combiner>;
  124. interrupts = <1 2>, <22 4>;
  125. };
  126. pinctrl_0: pinctrl@11400000 {
  127. compatible = "samsung,exynos5250-pinctrl";
  128. reg = <0x11400000 0x1000>;
  129. interrupts = <0 46 0>;
  130. wakup_eint: wakeup-interrupt-controller {
  131. compatible = "samsung,exynos4210-wakeup-eint";
  132. interrupt-parent = <&gic>;
  133. interrupts = <0 32 0>;
  134. };
  135. };
  136. pinctrl_1: pinctrl@13400000 {
  137. compatible = "samsung,exynos5250-pinctrl";
  138. reg = <0x13400000 0x1000>;
  139. interrupts = <0 45 0>;
  140. };
  141. pinctrl_2: pinctrl@10d10000 {
  142. compatible = "samsung,exynos5250-pinctrl";
  143. reg = <0x10d10000 0x1000>;
  144. interrupts = <0 50 0>;
  145. };
  146. pinctrl_3: pinctrl@03680000 {
  147. compatible = "samsung,exynos5250-pinctrl";
  148. reg = <0x0368000 0x1000>;
  149. interrupts = <0 47 0>;
  150. };
  151. watchdog {
  152. compatible = "samsung,s3c2410-wdt";
  153. reg = <0x101D0000 0x100>;
  154. interrupts = <0 42 0>;
  155. clocks = <&clock 336>;
  156. clock-names = "watchdog";
  157. };
  158. codec@11000000 {
  159. compatible = "samsung,mfc-v6";
  160. reg = <0x11000000 0x10000>;
  161. interrupts = <0 96 0>;
  162. samsung,power-domain = <&pd_mfc>;
  163. };
  164. rtc {
  165. compatible = "samsung,s3c6410-rtc";
  166. reg = <0x101E0000 0x100>;
  167. interrupts = <0 43 0>, <0 44 0>;
  168. clocks = <&clock 337>;
  169. clock-names = "rtc";
  170. status = "disabled";
  171. };
  172. tmu@10060000 {
  173. compatible = "samsung,exynos5250-tmu";
  174. reg = <0x10060000 0x100>;
  175. interrupts = <0 65 0>;
  176. clocks = <&clock 338>;
  177. clock-names = "tmu_apbif";
  178. };
  179. serial@12C00000 {
  180. compatible = "samsung,exynos4210-uart";
  181. reg = <0x12C00000 0x100>;
  182. interrupts = <0 51 0>;
  183. clocks = <&clock 289>, <&clock 146>;
  184. clock-names = "uart", "clk_uart_baud0";
  185. };
  186. serial@12C10000 {
  187. compatible = "samsung,exynos4210-uart";
  188. reg = <0x12C10000 0x100>;
  189. interrupts = <0 52 0>;
  190. clocks = <&clock 290>, <&clock 147>;
  191. clock-names = "uart", "clk_uart_baud0";
  192. };
  193. serial@12C20000 {
  194. compatible = "samsung,exynos4210-uart";
  195. reg = <0x12C20000 0x100>;
  196. interrupts = <0 53 0>;
  197. clocks = <&clock 291>, <&clock 148>;
  198. clock-names = "uart", "clk_uart_baud0";
  199. };
  200. serial@12C30000 {
  201. compatible = "samsung,exynos4210-uart";
  202. reg = <0x12C30000 0x100>;
  203. interrupts = <0 54 0>;
  204. clocks = <&clock 292>, <&clock 149>;
  205. clock-names = "uart", "clk_uart_baud0";
  206. };
  207. sata@122F0000 {
  208. compatible = "samsung,exynos5-sata-ahci";
  209. reg = <0x122F0000 0x1ff>;
  210. interrupts = <0 115 0>;
  211. clocks = <&clock 277>, <&clock 143>;
  212. clock-names = "sata", "sclk_sata";
  213. };
  214. sata-phy@12170000 {
  215. compatible = "samsung,exynos5-sata-phy";
  216. reg = <0x12170000 0x1ff>;
  217. };
  218. i2c_0: i2c@12C60000 {
  219. compatible = "samsung,s3c2440-i2c";
  220. reg = <0x12C60000 0x100>;
  221. interrupts = <0 56 0>;
  222. #address-cells = <1>;
  223. #size-cells = <0>;
  224. clocks = <&clock 294>;
  225. clock-names = "i2c";
  226. pinctrl-names = "default";
  227. pinctrl-0 = <&i2c0_bus>;
  228. };
  229. i2c_1: i2c@12C70000 {
  230. compatible = "samsung,s3c2440-i2c";
  231. reg = <0x12C70000 0x100>;
  232. interrupts = <0 57 0>;
  233. #address-cells = <1>;
  234. #size-cells = <0>;
  235. clocks = <&clock 295>;
  236. clock-names = "i2c";
  237. pinctrl-names = "default";
  238. pinctrl-0 = <&i2c1_bus>;
  239. };
  240. i2c_2: i2c@12C80000 {
  241. compatible = "samsung,s3c2440-i2c";
  242. reg = <0x12C80000 0x100>;
  243. interrupts = <0 58 0>;
  244. #address-cells = <1>;
  245. #size-cells = <0>;
  246. clocks = <&clock 296>;
  247. clock-names = "i2c";
  248. pinctrl-names = "default";
  249. pinctrl-0 = <&i2c2_bus>;
  250. };
  251. i2c_3: i2c@12C90000 {
  252. compatible = "samsung,s3c2440-i2c";
  253. reg = <0x12C90000 0x100>;
  254. interrupts = <0 59 0>;
  255. #address-cells = <1>;
  256. #size-cells = <0>;
  257. clocks = <&clock 297>;
  258. clock-names = "i2c";
  259. pinctrl-names = "default";
  260. pinctrl-0 = <&i2c3_bus>;
  261. };
  262. i2c_4: i2c@12CA0000 {
  263. compatible = "samsung,s3c2440-i2c";
  264. reg = <0x12CA0000 0x100>;
  265. interrupts = <0 60 0>;
  266. #address-cells = <1>;
  267. #size-cells = <0>;
  268. clocks = <&clock 298>;
  269. clock-names = "i2c";
  270. pinctrl-names = "default";
  271. pinctrl-0 = <&i2c4_bus>;
  272. };
  273. i2c_5: i2c@12CB0000 {
  274. compatible = "samsung,s3c2440-i2c";
  275. reg = <0x12CB0000 0x100>;
  276. interrupts = <0 61 0>;
  277. #address-cells = <1>;
  278. #size-cells = <0>;
  279. clocks = <&clock 299>;
  280. clock-names = "i2c";
  281. pinctrl-names = "default";
  282. pinctrl-0 = <&i2c5_bus>;
  283. };
  284. i2c_6: i2c@12CC0000 {
  285. compatible = "samsung,s3c2440-i2c";
  286. reg = <0x12CC0000 0x100>;
  287. interrupts = <0 62 0>;
  288. #address-cells = <1>;
  289. #size-cells = <0>;
  290. clocks = <&clock 300>;
  291. clock-names = "i2c";
  292. pinctrl-names = "default";
  293. pinctrl-0 = <&i2c6_bus>;
  294. };
  295. i2c_7: i2c@12CD0000 {
  296. compatible = "samsung,s3c2440-i2c";
  297. reg = <0x12CD0000 0x100>;
  298. interrupts = <0 63 0>;
  299. #address-cells = <1>;
  300. #size-cells = <0>;
  301. clocks = <&clock 301>;
  302. clock-names = "i2c";
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&i2c7_bus>;
  305. };
  306. i2c_8: i2c@12CE0000 {
  307. compatible = "samsung,s3c2440-hdmiphy-i2c";
  308. reg = <0x12CE0000 0x1000>;
  309. interrupts = <0 64 0>;
  310. #address-cells = <1>;
  311. #size-cells = <0>;
  312. clocks = <&clock 302>;
  313. clock-names = "i2c";
  314. };
  315. i2c@121D0000 {
  316. compatible = "samsung,exynos5-sata-phy-i2c";
  317. reg = <0x121D0000 0x100>;
  318. #address-cells = <1>;
  319. #size-cells = <0>;
  320. clocks = <&clock 288>;
  321. clock-names = "i2c";
  322. };
  323. spi_0: spi@12d20000 {
  324. compatible = "samsung,exynos4210-spi";
  325. reg = <0x12d20000 0x100>;
  326. interrupts = <0 66 0>;
  327. dmas = <&pdma0 5
  328. &pdma0 4>;
  329. dma-names = "tx", "rx";
  330. #address-cells = <1>;
  331. #size-cells = <0>;
  332. clocks = <&clock 304>, <&clock 154>;
  333. clock-names = "spi", "spi_busclk0";
  334. pinctrl-names = "default";
  335. pinctrl-0 = <&spi0_bus>;
  336. };
  337. spi_1: spi@12d30000 {
  338. compatible = "samsung,exynos4210-spi";
  339. reg = <0x12d30000 0x100>;
  340. interrupts = <0 67 0>;
  341. dmas = <&pdma1 5
  342. &pdma1 4>;
  343. dma-names = "tx", "rx";
  344. #address-cells = <1>;
  345. #size-cells = <0>;
  346. clocks = <&clock 305>, <&clock 155>;
  347. clock-names = "spi", "spi_busclk0";
  348. pinctrl-names = "default";
  349. pinctrl-0 = <&spi1_bus>;
  350. };
  351. spi_2: spi@12d40000 {
  352. compatible = "samsung,exynos4210-spi";
  353. reg = <0x12d40000 0x100>;
  354. interrupts = <0 68 0>;
  355. dmas = <&pdma0 7
  356. &pdma0 6>;
  357. dma-names = "tx", "rx";
  358. #address-cells = <1>;
  359. #size-cells = <0>;
  360. clocks = <&clock 306>, <&clock 156>;
  361. clock-names = "spi", "spi_busclk0";
  362. pinctrl-names = "default";
  363. pinctrl-0 = <&spi2_bus>;
  364. };
  365. dwmmc_0: dwmmc0@12200000 {
  366. compatible = "samsung,exynos5250-dw-mshc";
  367. reg = <0x12200000 0x1000>;
  368. interrupts = <0 75 0>;
  369. #address-cells = <1>;
  370. #size-cells = <0>;
  371. clocks = <&clock 280>, <&clock 139>;
  372. clock-names = "biu", "ciu";
  373. };
  374. dwmmc_1: dwmmc1@12210000 {
  375. compatible = "samsung,exynos5250-dw-mshc";
  376. reg = <0x12210000 0x1000>;
  377. interrupts = <0 76 0>;
  378. #address-cells = <1>;
  379. #size-cells = <0>;
  380. clocks = <&clock 281>, <&clock 140>;
  381. clock-names = "biu", "ciu";
  382. };
  383. dwmmc_2: dwmmc2@12220000 {
  384. compatible = "samsung,exynos5250-dw-mshc";
  385. reg = <0x12220000 0x1000>;
  386. interrupts = <0 77 0>;
  387. #address-cells = <1>;
  388. #size-cells = <0>;
  389. clocks = <&clock 282>, <&clock 141>;
  390. clock-names = "biu", "ciu";
  391. };
  392. dwmmc_3: dwmmc3@12230000 {
  393. compatible = "samsung,exynos5250-dw-mshc";
  394. reg = <0x12230000 0x1000>;
  395. interrupts = <0 78 0>;
  396. #address-cells = <1>;
  397. #size-cells = <0>;
  398. clocks = <&clock 283>, <&clock 142>;
  399. clock-names = "biu", "ciu";
  400. };
  401. i2s0: i2s@03830000 {
  402. compatible = "samsung,i2s-v5";
  403. reg = <0x03830000 0x100>;
  404. dmas = <&pdma0 10
  405. &pdma0 9
  406. &pdma0 8>;
  407. dma-names = "tx", "rx", "tx-sec";
  408. samsung,supports-6ch;
  409. samsung,supports-rstclr;
  410. samsung,supports-secdai;
  411. samsung,idma-addr = <0x03000000>;
  412. pinctrl-names = "default";
  413. pinctrl-0 = <&i2s0_bus>;
  414. };
  415. i2s1: i2s@12D60000 {
  416. compatible = "samsung,i2s-v5";
  417. reg = <0x12D60000 0x100>;
  418. dmas = <&pdma1 12
  419. &pdma1 11>;
  420. dma-names = "tx", "rx";
  421. pinctrl-names = "default";
  422. pinctrl-0 = <&i2s1_bus>;
  423. };
  424. i2s2: i2s@12D70000 {
  425. compatible = "samsung,i2s-v5";
  426. reg = <0x12D70000 0x100>;
  427. dmas = <&pdma0 12
  428. &pdma0 11>;
  429. dma-names = "tx", "rx";
  430. pinctrl-names = "default";
  431. pinctrl-0 = <&i2s2_bus>;
  432. };
  433. usb@12110000 {
  434. compatible = "samsung,exynos4210-ehci";
  435. reg = <0x12110000 0x100>;
  436. interrupts = <0 71 0>;
  437. clocks = <&clock 285>;
  438. clock-names = "usbhost";
  439. };
  440. usb@12120000 {
  441. compatible = "samsung,exynos4210-ohci";
  442. reg = <0x12120000 0x100>;
  443. interrupts = <0 71 0>;
  444. clocks = <&clock 285>;
  445. clock-names = "usbhost";
  446. };
  447. amba {
  448. #address-cells = <1>;
  449. #size-cells = <1>;
  450. compatible = "arm,amba-bus";
  451. interrupt-parent = <&gic>;
  452. ranges;
  453. pdma0: pdma@121A0000 {
  454. compatible = "arm,pl330", "arm,primecell";
  455. reg = <0x121A0000 0x1000>;
  456. interrupts = <0 34 0>;
  457. clocks = <&clock 275>;
  458. clock-names = "apb_pclk";
  459. #dma-cells = <1>;
  460. #dma-channels = <8>;
  461. #dma-requests = <32>;
  462. };
  463. pdma1: pdma@121B0000 {
  464. compatible = "arm,pl330", "arm,primecell";
  465. reg = <0x121B0000 0x1000>;
  466. interrupts = <0 35 0>;
  467. clocks = <&clock 276>;
  468. clock-names = "apb_pclk";
  469. #dma-cells = <1>;
  470. #dma-channels = <8>;
  471. #dma-requests = <32>;
  472. };
  473. mdma0: mdma@10800000 {
  474. compatible = "arm,pl330", "arm,primecell";
  475. reg = <0x10800000 0x1000>;
  476. interrupts = <0 33 0>;
  477. clocks = <&clock 271>;
  478. clock-names = "apb_pclk";
  479. #dma-cells = <1>;
  480. #dma-channels = <8>;
  481. #dma-requests = <1>;
  482. };
  483. mdma1: mdma@11C10000 {
  484. compatible = "arm,pl330", "arm,primecell";
  485. reg = <0x11C10000 0x1000>;
  486. interrupts = <0 124 0>;
  487. clocks = <&clock 271>;
  488. clock-names = "apb_pclk";
  489. #dma-cells = <1>;
  490. #dma-channels = <8>;
  491. #dma-requests = <1>;
  492. };
  493. };
  494. gsc_0: gsc@0x13e00000 {
  495. compatible = "samsung,exynos5-gsc";
  496. reg = <0x13e00000 0x1000>;
  497. interrupts = <0 85 0>;
  498. samsung,power-domain = <&pd_gsc>;
  499. clocks = <&clock 256>;
  500. clock-names = "gscl";
  501. };
  502. gsc_1: gsc@0x13e10000 {
  503. compatible = "samsung,exynos5-gsc";
  504. reg = <0x13e10000 0x1000>;
  505. interrupts = <0 86 0>;
  506. samsung,power-domain = <&pd_gsc>;
  507. clocks = <&clock 257>;
  508. clock-names = "gscl";
  509. };
  510. gsc_2: gsc@0x13e20000 {
  511. compatible = "samsung,exynos5-gsc";
  512. reg = <0x13e20000 0x1000>;
  513. interrupts = <0 87 0>;
  514. samsung,power-domain = <&pd_gsc>;
  515. clocks = <&clock 258>;
  516. clock-names = "gscl";
  517. };
  518. gsc_3: gsc@0x13e30000 {
  519. compatible = "samsung,exynos5-gsc";
  520. reg = <0x13e30000 0x1000>;
  521. interrupts = <0 88 0>;
  522. samsung,power-domain = <&pd_gsc>;
  523. clocks = <&clock 259>;
  524. clock-names = "gscl";
  525. };
  526. hdmi {
  527. compatible = "samsung,exynos5-hdmi";
  528. reg = <0x14530000 0x70000>;
  529. interrupts = <0 95 0>;
  530. clocks = <&clock 333>, <&clock 136>, <&clock 137>,
  531. <&clock 333>, <&clock 333>;
  532. clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
  533. "sclk_hdmiphy", "hdmiphy";
  534. };
  535. mixer {
  536. compatible = "samsung,exynos5-mixer";
  537. reg = <0x14450000 0x10000>;
  538. interrupts = <0 94 0>;
  539. };
  540. dp-controller {
  541. compatible = "samsung,exynos5-dp";
  542. reg = <0x145b0000 0x1000>;
  543. interrupts = <10 3>;
  544. interrupt-parent = <&combiner>;
  545. #address-cells = <1>;
  546. #size-cells = <0>;
  547. dptx-phy {
  548. reg = <0x10040720>;
  549. samsung,enable-mask = <1>;
  550. };
  551. };
  552. fimd {
  553. compatible = "samsung,exynos5250-fimd";
  554. interrupt-parent = <&combiner>;
  555. reg = <0x14400000 0x40000>;
  556. interrupt-names = "fifo", "vsync", "lcd_sys";
  557. interrupts = <18 4>, <18 5>, <18 6>;
  558. clocks = <&clock 133>, <&clock 339>;
  559. clock-names = "sclk_fimd", "fimd";
  560. };
  561. };