exynos4210.dtsi 3.0 KB

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  1. /*
  2. * Samsung's Exynos4210 SoC device tree source
  3. *
  4. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. * Copyright (c) 2010-2011 Linaro Ltd.
  7. * www.linaro.org
  8. *
  9. * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
  10. * based board files can include this file and provide values for board specfic
  11. * bindings.
  12. *
  13. * Note: This file does not include device nodes for all the controllers in
  14. * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
  15. * nodes can be added to this file.
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License version 2 as
  19. * published by the Free Software Foundation.
  20. */
  21. /include/ "exynos4.dtsi"
  22. /include/ "exynos4210-pinctrl.dtsi"
  23. / {
  24. compatible = "samsung,exynos4210";
  25. aliases {
  26. pinctrl0 = &pinctrl_0;
  27. pinctrl1 = &pinctrl_1;
  28. pinctrl2 = &pinctrl_2;
  29. };
  30. pd_lcd1: lcd1-power-domain@10023CA0 {
  31. compatible = "samsung,exynos4210-pd";
  32. reg = <0x10023CA0 0x20>;
  33. };
  34. gic:interrupt-controller@10490000 {
  35. cpu-offset = <0x8000>;
  36. };
  37. combiner:interrupt-controller@10440000 {
  38. samsung,combiner-nr = <16>;
  39. interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  40. <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  41. <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  42. <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
  43. };
  44. mct@10050000 {
  45. compatible = "samsung,exynos4210-mct";
  46. reg = <0x10050000 0x800>;
  47. interrupt-controller;
  48. #interrups-cells = <2>;
  49. interrupt-parent = <&mct_map>;
  50. interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
  51. <4 0>, <5 0>;
  52. clocks = <&clock 3>, <&clock 344>;
  53. clock-names = "fin_pll", "mct";
  54. mct_map: mct-map {
  55. #interrupt-cells = <2>;
  56. #address-cells = <0>;
  57. #size-cells = <0>;
  58. interrupt-map = <0x0 0 &gic 0 57 0>,
  59. <0x1 0 &gic 0 69 0>,
  60. <0x2 0 &combiner 12 6>,
  61. <0x3 0 &combiner 12 7>,
  62. <0x4 0 &gic 0 42 0>,
  63. <0x5 0 &gic 0 48 0>;
  64. };
  65. };
  66. clock: clock-controller@0x10030000 {
  67. compatible = "samsung,exynos4210-clock";
  68. reg = <0x10030000 0x20000>;
  69. #clock-cells = <1>;
  70. };
  71. pmu {
  72. compatible = "arm,cortex-a9-pmu";
  73. interrupt-parent = <&combiner>;
  74. interrupts = <2 2>, <3 2>;
  75. };
  76. pinctrl_0: pinctrl@11400000 {
  77. compatible = "samsung,exynos4210-pinctrl";
  78. reg = <0x11400000 0x1000>;
  79. interrupts = <0 47 0>;
  80. };
  81. pinctrl_1: pinctrl@11000000 {
  82. compatible = "samsung,exynos4210-pinctrl";
  83. reg = <0x11000000 0x1000>;
  84. interrupts = <0 46 0>;
  85. wakup_eint: wakeup-interrupt-controller {
  86. compatible = "samsung,exynos4210-wakeup-eint";
  87. interrupt-parent = <&gic>;
  88. interrupts = <0 32 0>;
  89. };
  90. };
  91. pinctrl_2: pinctrl@03860000 {
  92. compatible = "samsung,exynos4210-pinctrl";
  93. reg = <0x03860000 0x1000>;
  94. };
  95. tmu@100C0000 {
  96. compatible = "samsung,exynos4210-tmu";
  97. interrupt-parent = <&combiner>;
  98. reg = <0x100C0000 0x100>;
  99. interrupts = <2 4>;
  100. };
  101. g2d@12800000 {
  102. compatible = "samsung,s5pv210-g2d";
  103. reg = <0x12800000 0x1000>;
  104. interrupts = <0 89 0>;
  105. status = "disabled";
  106. };
  107. };