bcm11351.dtsi 1.5 KB

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  1. /*
  2. * Copyright (C) 2012 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. /include/ "skeleton.dtsi"
  14. / {
  15. model = "BCM11351 SoC";
  16. compatible = "bcm,bcm11351";
  17. interrupt-parent = <&gic>;
  18. chosen {
  19. bootargs = "console=ttyS0,115200n8";
  20. };
  21. gic: interrupt-controller@3ff00100 {
  22. compatible = "arm,cortex-a9-gic";
  23. #interrupt-cells = <3>;
  24. #address-cells = <0>;
  25. interrupt-controller;
  26. reg = <0x3ff01000 0x1000>,
  27. <0x3ff00100 0x100>;
  28. };
  29. smc@0x3404c000 {
  30. compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
  31. reg = <0x3404c000 0x400>; //1 KiB in SRAM
  32. };
  33. uart@3e000000 {
  34. compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
  35. status = "disabled";
  36. reg = <0x3e000000 0x1000>;
  37. clock-frequency = <13000000>;
  38. interrupts = <0x0 67 0x4>;
  39. reg-shift = <2>;
  40. reg-io-width = <4>;
  41. };
  42. L2: l2-cache {
  43. compatible = "arm,pl310-cache";
  44. reg = <0x3ff20000 0x1000>;
  45. cache-unified;
  46. cache-level = <2>;
  47. };
  48. timer@35006000 {
  49. compatible = "bcm,kona-timer";
  50. reg = <0x35006000 0x1000>;
  51. interrupts = <0x0 7 0x4>;
  52. clock-frequency = <32768>;
  53. };
  54. };