at91sam9n12.dtsi 11 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. model = "Atmel AT91SAM9N12 SoC";
  12. compatible = "atmel,at91sam9n12";
  13. interrupt-parent = <&aic>;
  14. aliases {
  15. serial0 = &dbgu;
  16. serial1 = &usart0;
  17. serial2 = &usart1;
  18. serial3 = &usart2;
  19. serial4 = &usart3;
  20. gpio0 = &pioA;
  21. gpio1 = &pioB;
  22. gpio2 = &pioC;
  23. gpio3 = &pioD;
  24. tcb0 = &tcb0;
  25. tcb1 = &tcb1;
  26. i2c0 = &i2c0;
  27. i2c1 = &i2c1;
  28. ssc0 = &ssc0;
  29. };
  30. cpus {
  31. cpu@0 {
  32. compatible = "arm,arm926ejs";
  33. };
  34. };
  35. memory {
  36. reg = <0x20000000 0x10000000>;
  37. };
  38. ahb {
  39. compatible = "simple-bus";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. ranges;
  43. apb {
  44. compatible = "simple-bus";
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. ranges;
  48. aic: interrupt-controller@fffff000 {
  49. #interrupt-cells = <3>;
  50. compatible = "atmel,at91rm9200-aic";
  51. interrupt-controller;
  52. reg = <0xfffff000 0x200>;
  53. };
  54. ramc0: ramc@ffffe800 {
  55. compatible = "atmel,at91sam9g45-ddramc";
  56. reg = <0xffffe800 0x200>;
  57. };
  58. pmc: pmc@fffffc00 {
  59. compatible = "atmel,at91rm9200-pmc";
  60. reg = <0xfffffc00 0x100>;
  61. };
  62. rstc@fffffe00 {
  63. compatible = "atmel,at91sam9g45-rstc";
  64. reg = <0xfffffe00 0x10>;
  65. };
  66. pit: timer@fffffe30 {
  67. compatible = "atmel,at91sam9260-pit";
  68. reg = <0xfffffe30 0xf>;
  69. interrupts = <1 4 7>;
  70. };
  71. shdwc@fffffe10 {
  72. compatible = "atmel,at91sam9x5-shdwc";
  73. reg = <0xfffffe10 0x10>;
  74. };
  75. mmc0: mmc@f0008000 {
  76. compatible = "atmel,hsmci";
  77. reg = <0xf0008000 0x600>;
  78. interrupts = <12 4 0>;
  79. dmas = <&dma 1 0>;
  80. dma-names = "rxtx";
  81. #address-cells = <1>;
  82. #size-cells = <0>;
  83. status = "disabled";
  84. };
  85. tcb0: timer@f8008000 {
  86. compatible = "atmel,at91sam9x5-tcb";
  87. reg = <0xf8008000 0x100>;
  88. interrupts = <17 4 0>;
  89. };
  90. tcb1: timer@f800c000 {
  91. compatible = "atmel,at91sam9x5-tcb";
  92. reg = <0xf800c000 0x100>;
  93. interrupts = <17 4 0>;
  94. };
  95. dma: dma-controller@ffffec00 {
  96. compatible = "atmel,at91sam9g45-dma";
  97. reg = <0xffffec00 0x200>;
  98. interrupts = <20 4 0>;
  99. #dma-cells = <2>;
  100. };
  101. pinctrl@fffff400 {
  102. #address-cells = <1>;
  103. #size-cells = <1>;
  104. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  105. ranges = <0xfffff400 0xfffff400 0x800>;
  106. atmel,mux-mask = <
  107. /* A B C */
  108. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  109. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  110. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  111. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  112. >;
  113. /* shared pinctrl settings */
  114. dbgu {
  115. pinctrl_dbgu: dbgu-0 {
  116. atmel,pins =
  117. <0 9 0x1 0x0 /* PA9 periph A */
  118. 0 10 0x1 0x1>; /* PA10 periph with pullup */
  119. };
  120. };
  121. usart0 {
  122. pinctrl_usart0: usart0-0 {
  123. atmel,pins =
  124. <0 1 0x1 0x1 /* PA1 periph A with pullup */
  125. 0 0 0x1 0x0>; /* PA0 periph A */
  126. };
  127. pinctrl_usart0_rts: usart0_rts-0 {
  128. atmel,pins =
  129. <0 2 0x1 0x0>; /* PA2 periph A */
  130. };
  131. pinctrl_usart0_cts: usart0_cts-0 {
  132. atmel,pins =
  133. <0 3 0x1 0x0>; /* PA3 periph A */
  134. };
  135. };
  136. usart1 {
  137. pinctrl_usart1: usart1-0 {
  138. atmel,pins =
  139. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  140. 0 5 0x1 0x0>; /* PA5 periph A */
  141. };
  142. };
  143. usart2 {
  144. pinctrl_usart2: usart2-0 {
  145. atmel,pins =
  146. <0 8 0x1 0x1 /* PA8 periph A with pullup */
  147. 0 7 0x1 0x0>; /* PA7 periph A */
  148. };
  149. pinctrl_usart2_rts: usart2_rts-0 {
  150. atmel,pins =
  151. <1 0 0x2 0x0>; /* PB0 periph B */
  152. };
  153. pinctrl_usart2_cts: usart2_cts-0 {
  154. atmel,pins =
  155. <1 1 0x2 0x0>; /* PB1 periph B */
  156. };
  157. };
  158. usart3 {
  159. pinctrl_usart3: usart3-0 {
  160. atmel,pins =
  161. <2 23 0x2 0x1 /* PC23 periph B with pullup */
  162. 2 22 0x2 0x0>; /* PC22 periph B */
  163. };
  164. pinctrl_usart3_rts: usart3_rts-0 {
  165. atmel,pins =
  166. <2 24 0x2 0x0>; /* PC24 periph B */
  167. };
  168. pinctrl_usart3_cts: usart3_cts-0 {
  169. atmel,pins =
  170. <2 25 0x2 0x0>; /* PC25 periph B */
  171. };
  172. };
  173. uart0 {
  174. pinctrl_uart0: uart0-0 {
  175. atmel,pins =
  176. <2 9 0x3 0x1 /* PC9 periph C with pullup */
  177. 2 8 0x3 0x0>; /* PC8 periph C */
  178. };
  179. };
  180. uart1 {
  181. pinctrl_uart1: uart1-0 {
  182. atmel,pins =
  183. <2 16 0x3 0x1 /* PC17 periph C with pullup */
  184. 2 17 0x3 0x0>; /* PC16 periph C */
  185. };
  186. };
  187. nand {
  188. pinctrl_nand: nand-0 {
  189. atmel,pins =
  190. <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
  191. 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  192. };
  193. };
  194. mmc0 {
  195. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  196. atmel,pins =
  197. <0 17 0x1 0x0 /* PA17 periph A */
  198. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  199. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  200. };
  201. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  202. atmel,pins =
  203. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  204. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  205. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  206. };
  207. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  208. atmel,pins =
  209. <0 11 0x2 0x1 /* PA11 periph B with pullup */
  210. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  211. 0 13 0x2 0x1 /* PA13 periph B with pullup */
  212. 0 14 0x2 0x1>; /* PA14 periph B with pullup */
  213. };
  214. };
  215. ssc0 {
  216. pinctrl_ssc0_tx: ssc0_tx-0 {
  217. atmel,pins =
  218. <0 24 0x2 0x0 /* PA24 periph B */
  219. 0 25 0x2 0x0 /* PA25 periph B */
  220. 0 26 0x2 0x0>; /* PA26 periph B */
  221. };
  222. pinctrl_ssc0_rx: ssc0_rx-0 {
  223. atmel,pins =
  224. <0 27 0x2 0x0 /* PA27 periph B */
  225. 0 28 0x2 0x0 /* PA28 periph B */
  226. 0 29 0x2 0x0>; /* PA29 periph B */
  227. };
  228. };
  229. spi0 {
  230. pinctrl_spi0: spi0-0 {
  231. atmel,pins =
  232. <0 11 0x1 0x0 /* PA11 periph A SPI0_MISO pin */
  233. 0 12 0x1 0x0 /* PA12 periph A SPI0_MOSI pin */
  234. 0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
  235. };
  236. };
  237. spi1 {
  238. pinctrl_spi1: spi1-0 {
  239. atmel,pins =
  240. <0 21 0x2 0x0 /* PA21 periph B SPI1_MISO pin */
  241. 0 22 0x2 0x0 /* PA22 periph B SPI1_MOSI pin */
  242. 0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
  243. };
  244. };
  245. pioA: gpio@fffff400 {
  246. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  247. reg = <0xfffff400 0x200>;
  248. interrupts = <2 4 1>;
  249. #gpio-cells = <2>;
  250. gpio-controller;
  251. interrupt-controller;
  252. #interrupt-cells = <2>;
  253. };
  254. pioB: gpio@fffff600 {
  255. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  256. reg = <0xfffff600 0x200>;
  257. interrupts = <2 4 1>;
  258. #gpio-cells = <2>;
  259. gpio-controller;
  260. interrupt-controller;
  261. #interrupt-cells = <2>;
  262. };
  263. pioC: gpio@fffff800 {
  264. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  265. reg = <0xfffff800 0x200>;
  266. interrupts = <3 4 1>;
  267. #gpio-cells = <2>;
  268. gpio-controller;
  269. interrupt-controller;
  270. #interrupt-cells = <2>;
  271. };
  272. pioD: gpio@fffffa00 {
  273. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  274. reg = <0xfffffa00 0x200>;
  275. interrupts = <3 4 1>;
  276. #gpio-cells = <2>;
  277. gpio-controller;
  278. interrupt-controller;
  279. #interrupt-cells = <2>;
  280. };
  281. };
  282. dbgu: serial@fffff200 {
  283. compatible = "atmel,at91sam9260-usart";
  284. reg = <0xfffff200 0x200>;
  285. interrupts = <1 4 7>;
  286. pinctrl-names = "default";
  287. pinctrl-0 = <&pinctrl_dbgu>;
  288. status = "disabled";
  289. };
  290. ssc0: ssc@f0010000 {
  291. compatible = "atmel,at91sam9g45-ssc";
  292. reg = <0xf0010000 0x4000>;
  293. interrupts = <28 4 5>;
  294. pinctrl-names = "default";
  295. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  296. status = "disabled";
  297. };
  298. usart0: serial@f801c000 {
  299. compatible = "atmel,at91sam9260-usart";
  300. reg = <0xf801c000 0x4000>;
  301. interrupts = <5 4 5>;
  302. pinctrl-names = "default";
  303. pinctrl-0 = <&pinctrl_usart0>;
  304. status = "disabled";
  305. };
  306. usart1: serial@f8020000 {
  307. compatible = "atmel,at91sam9260-usart";
  308. reg = <0xf8020000 0x4000>;
  309. interrupts = <6 4 5>;
  310. pinctrl-names = "default";
  311. pinctrl-0 = <&pinctrl_usart1>;
  312. status = "disabled";
  313. };
  314. usart2: serial@f8024000 {
  315. compatible = "atmel,at91sam9260-usart";
  316. reg = <0xf8024000 0x4000>;
  317. interrupts = <7 4 5>;
  318. pinctrl-names = "default";
  319. pinctrl-0 = <&pinctrl_usart2>;
  320. status = "disabled";
  321. };
  322. usart3: serial@f8028000 {
  323. compatible = "atmel,at91sam9260-usart";
  324. reg = <0xf8028000 0x4000>;
  325. interrupts = <8 4 5>;
  326. pinctrl-names = "default";
  327. pinctrl-0 = <&pinctrl_usart3>;
  328. status = "disabled";
  329. };
  330. i2c0: i2c@f8010000 {
  331. compatible = "atmel,at91sam9x5-i2c";
  332. reg = <0xf8010000 0x100>;
  333. interrupts = <9 4 6>;
  334. dmas = <&dma 1 13>,
  335. <&dma 1 14>;
  336. dma-names = "tx", "rx";
  337. #address-cells = <1>;
  338. #size-cells = <0>;
  339. status = "disabled";
  340. };
  341. i2c1: i2c@f8014000 {
  342. compatible = "atmel,at91sam9x5-i2c";
  343. reg = <0xf8014000 0x100>;
  344. interrupts = <10 4 6>;
  345. dmas = <&dma 1 15>,
  346. <&dma 1 16>;
  347. dma-names = "tx", "rx";
  348. #address-cells = <1>;
  349. #size-cells = <0>;
  350. status = "disabled";
  351. };
  352. spi0: spi@f0000000 {
  353. #address-cells = <1>;
  354. #size-cells = <0>;
  355. compatible = "atmel,at91rm9200-spi";
  356. reg = <0xf0000000 0x100>;
  357. interrupts = <13 4 3>;
  358. pinctrl-names = "default";
  359. pinctrl-0 = <&pinctrl_spi0>;
  360. status = "disabled";
  361. };
  362. spi1: spi@f0004000 {
  363. #address-cells = <1>;
  364. #size-cells = <0>;
  365. compatible = "atmel,at91rm9200-spi";
  366. reg = <0xf0004000 0x100>;
  367. interrupts = <14 4 3>;
  368. pinctrl-names = "default";
  369. pinctrl-0 = <&pinctrl_spi1>;
  370. status = "disabled";
  371. };
  372. };
  373. nand0: nand@40000000 {
  374. compatible = "atmel,at91rm9200-nand";
  375. #address-cells = <1>;
  376. #size-cells = <1>;
  377. reg = < 0x40000000 0x10000000
  378. 0xffffe000 0x00000600
  379. 0xffffe600 0x00000200
  380. 0x00108000 0x00018000
  381. >;
  382. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  383. atmel,nand-addr-offset = <21>;
  384. atmel,nand-cmd-offset = <22>;
  385. pinctrl-names = "default";
  386. pinctrl-0 = <&pinctrl_nand>;
  387. gpios = <&pioD 5 0
  388. &pioD 4 0
  389. 0
  390. >;
  391. status = "disabled";
  392. };
  393. usb0: ohci@00500000 {
  394. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  395. reg = <0x00500000 0x00100000>;
  396. interrupts = <22 4 2>;
  397. status = "disabled";
  398. };
  399. };
  400. i2c@0 {
  401. compatible = "i2c-gpio";
  402. gpios = <&pioA 30 0 /* sda */
  403. &pioA 31 0 /* scl */
  404. >;
  405. i2c-gpio,sda-open-drain;
  406. i2c-gpio,scl-open-drain;
  407. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  408. #address-cells = <1>;
  409. #size-cells = <0>;
  410. status = "disabled";
  411. };
  412. };