at91sam9g45.dtsi 15 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. ssc0 = &ssc0;
  32. ssc1 = &ssc1;
  33. };
  34. cpus {
  35. cpu@0 {
  36. compatible = "arm,arm926ejs";
  37. };
  38. };
  39. memory {
  40. reg = <0x70000000 0x10000000>;
  41. };
  42. ahb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. apb {
  48. compatible = "simple-bus";
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. ranges;
  52. aic: interrupt-controller@fffff000 {
  53. #interrupt-cells = <3>;
  54. compatible = "atmel,at91rm9200-aic";
  55. interrupt-controller;
  56. reg = <0xfffff000 0x200>;
  57. atmel,external-irqs = <31>;
  58. };
  59. ramc0: ramc@ffffe400 {
  60. compatible = "atmel,at91sam9g45-ddramc";
  61. reg = <0xffffe400 0x200
  62. 0xffffe600 0x200>;
  63. };
  64. pmc: pmc@fffffc00 {
  65. compatible = "atmel,at91rm9200-pmc";
  66. reg = <0xfffffc00 0x100>;
  67. };
  68. rstc@fffffd00 {
  69. compatible = "atmel,at91sam9g45-rstc";
  70. reg = <0xfffffd00 0x10>;
  71. };
  72. pit: timer@fffffd30 {
  73. compatible = "atmel,at91sam9260-pit";
  74. reg = <0xfffffd30 0xf>;
  75. interrupts = <1 4 7>;
  76. };
  77. shdwc@fffffd10 {
  78. compatible = "atmel,at91sam9rl-shdwc";
  79. reg = <0xfffffd10 0x10>;
  80. };
  81. tcb0: timer@fff7c000 {
  82. compatible = "atmel,at91rm9200-tcb";
  83. reg = <0xfff7c000 0x100>;
  84. interrupts = <18 4 0>;
  85. };
  86. tcb1: timer@fffd4000 {
  87. compatible = "atmel,at91rm9200-tcb";
  88. reg = <0xfffd4000 0x100>;
  89. interrupts = <18 4 0>;
  90. };
  91. dma: dma-controller@ffffec00 {
  92. compatible = "atmel,at91sam9g45-dma";
  93. reg = <0xffffec00 0x200>;
  94. interrupts = <21 4 0>;
  95. #dma-cells = <2>;
  96. };
  97. pinctrl@fffff200 {
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  101. ranges = <0xfffff200 0xfffff200 0xa00>;
  102. atmel,mux-mask = <
  103. /* A B */
  104. 0xffffffff 0xffc003ff /* pioA */
  105. 0xffffffff 0x800f8f00 /* pioB */
  106. 0xffffffff 0x00000e00 /* pioC */
  107. 0xffffffff 0xff0c1381 /* pioD */
  108. 0xffffffff 0x81ffff81 /* pioE */
  109. >;
  110. /* shared pinctrl settings */
  111. dbgu {
  112. pinctrl_dbgu: dbgu-0 {
  113. atmel,pins =
  114. <1 12 0x1 0x0 /* PB12 periph A */
  115. 1 13 0x1 0x0>; /* PB13 periph A */
  116. };
  117. };
  118. usart0 {
  119. pinctrl_usart0: usart0-0 {
  120. atmel,pins =
  121. <1 19 0x1 0x1 /* PB19 periph A with pullup */
  122. 1 18 0x1 0x0>; /* PB18 periph A */
  123. };
  124. pinctrl_usart0_rts: usart0_rts-0 {
  125. atmel,pins =
  126. <1 17 0x2 0x0>; /* PB17 periph B */
  127. };
  128. pinctrl_usart0_cts: usart0_cts-0 {
  129. atmel,pins =
  130. <1 15 0x2 0x0>; /* PB15 periph B */
  131. };
  132. };
  133. uart1 {
  134. pinctrl_usart1: usart1-0 {
  135. atmel,pins =
  136. <1 4 0x1 0x1 /* PB4 periph A with pullup */
  137. 1 5 0x1 0x0>; /* PB5 periph A */
  138. };
  139. pinctrl_usart1_rts: usart1_rts-0 {
  140. atmel,pins =
  141. <3 16 0x1 0x0>; /* PD16 periph A */
  142. };
  143. pinctrl_usart1_cts: usart1_cts-0 {
  144. atmel,pins =
  145. <3 17 0x1 0x0>; /* PD17 periph A */
  146. };
  147. };
  148. usart2 {
  149. pinctrl_usart2: usart2-0 {
  150. atmel,pins =
  151. <1 6 0x1 0x1 /* PB6 periph A with pullup */
  152. 1 7 0x1 0x0>; /* PB7 periph A */
  153. };
  154. pinctrl_usart2_rts: usart2_rts-0 {
  155. atmel,pins =
  156. <2 9 0x2 0x0>; /* PC9 periph B */
  157. };
  158. pinctrl_usart2_cts: usart2_cts-0 {
  159. atmel,pins =
  160. <2 11 0x2 0x0>; /* PC11 periph B */
  161. };
  162. };
  163. usart3 {
  164. pinctrl_usart3: usart3-0 {
  165. atmel,pins =
  166. <1 8 0x1 0x1 /* PB9 periph A with pullup */
  167. 1 9 0x1 0x0>; /* PB8 periph A */
  168. };
  169. pinctrl_usart3_rts: usart3_rts-0 {
  170. atmel,pins =
  171. <0 23 0x2 0x0>; /* PA23 periph B */
  172. };
  173. pinctrl_usart3_cts: usart3_cts-0 {
  174. atmel,pins =
  175. <0 24 0x2 0x0>; /* PA24 periph B */
  176. };
  177. };
  178. nand {
  179. pinctrl_nand: nand-0 {
  180. atmel,pins =
  181. <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
  182. 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
  183. };
  184. };
  185. macb {
  186. pinctrl_macb_rmii: macb_rmii-0 {
  187. atmel,pins =
  188. <0 10 0x1 0x0 /* PA10 periph A */
  189. 0 11 0x1 0x0 /* PA11 periph A */
  190. 0 12 0x1 0x0 /* PA12 periph A */
  191. 0 13 0x1 0x0 /* PA13 periph A */
  192. 0 14 0x1 0x0 /* PA14 periph A */
  193. 0 15 0x1 0x0 /* PA15 periph A */
  194. 0 16 0x1 0x0 /* PA16 periph A */
  195. 0 17 0x1 0x0 /* PA17 periph A */
  196. 0 18 0x1 0x0 /* PA18 periph A */
  197. 0 19 0x1 0x0>; /* PA19 periph A */
  198. };
  199. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  200. atmel,pins =
  201. <0 6 0x2 0x0 /* PA6 periph B */
  202. 0 7 0x2 0x0 /* PA7 periph B */
  203. 0 8 0x2 0x0 /* PA8 periph B */
  204. 0 9 0x2 0x0 /* PA9 periph B */
  205. 0 27 0x2 0x0 /* PA27 periph B */
  206. 0 28 0x2 0x0 /* PA28 periph B */
  207. 0 29 0x2 0x0 /* PA29 periph B */
  208. 0 30 0x2 0x0>; /* PA30 periph B */
  209. };
  210. };
  211. mmc0 {
  212. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  213. atmel,pins =
  214. <0 0 0x1 0x0 /* PA0 periph A */
  215. 0 1 0x1 0x1 /* PA1 periph A with pullup */
  216. 0 2 0x1 0x1>; /* PA2 periph A with pullup */
  217. };
  218. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  219. atmel,pins =
  220. <0 3 0x1 0x1 /* PA3 periph A with pullup */
  221. 0 4 0x1 0x1 /* PA4 periph A with pullup */
  222. 0 5 0x1 0x1>; /* PA5 periph A with pullup */
  223. };
  224. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  225. atmel,pins =
  226. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  227. 0 7 0x1 0x1 /* PA7 periph A with pullup */
  228. 0 8 0x1 0x1 /* PA8 periph A with pullup */
  229. 0 9 0x1 0x1>; /* PA9 periph A with pullup */
  230. };
  231. };
  232. mmc1 {
  233. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  234. atmel,pins =
  235. <0 31 0x1 0x0 /* PA31 periph A */
  236. 0 22 0x1 0x1 /* PA22 periph A with pullup */
  237. 0 23 0x1 0x1>; /* PA23 periph A with pullup */
  238. };
  239. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  240. atmel,pins =
  241. <0 24 0x1 0x1 /* PA24 periph A with pullup */
  242. 0 25 0x1 0x1 /* PA25 periph A with pullup */
  243. 0 26 0x1 0x1>; /* PA26 periph A with pullup */
  244. };
  245. pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
  246. atmel,pins =
  247. <0 27 0x1 0x1 /* PA27 periph A with pullup */
  248. 0 28 0x1 0x1 /* PA28 periph A with pullup */
  249. 0 29 0x1 0x1 /* PA29 periph A with pullup */
  250. 0 20 0x1 0x1>; /* PA30 periph A with pullup */
  251. };
  252. };
  253. ssc0 {
  254. pinctrl_ssc0_tx: ssc0_tx-0 {
  255. atmel,pins =
  256. <3 0 0x1 0x0 /* PD0 periph A */
  257. 3 1 0x1 0x0 /* PD1 periph A */
  258. 3 2 0x1 0x0>; /* PD2 periph A */
  259. };
  260. pinctrl_ssc0_rx: ssc0_rx-0 {
  261. atmel,pins =
  262. <3 3 0x1 0x0 /* PD3 periph A */
  263. 3 4 0x1 0x0 /* PD4 periph A */
  264. 3 5 0x1 0x0>; /* PD5 periph A */
  265. };
  266. };
  267. ssc1 {
  268. pinctrl_ssc1_tx: ssc1_tx-0 {
  269. atmel,pins =
  270. <3 10 0x1 0x0 /* PD10 periph A */
  271. 3 11 0x1 0x0 /* PD11 periph A */
  272. 3 12 0x1 0x0>; /* PD12 periph A */
  273. };
  274. pinctrl_ssc1_rx: ssc1_rx-0 {
  275. atmel,pins =
  276. <3 13 0x1 0x0 /* PD13 periph A */
  277. 3 14 0x1 0x0 /* PD14 periph A */
  278. 3 15 0x1 0x0>; /* PD15 periph A */
  279. };
  280. };
  281. spi0 {
  282. pinctrl_spi0: spi0-0 {
  283. atmel,pins =
  284. <1 0 0x1 0x0 /* PB0 periph A SPI0_MISO pin */
  285. 1 1 0x1 0x0 /* PB1 periph A SPI0_MOSI pin */
  286. 1 2 0x1 0x0>; /* PB2 periph A SPI0_SPCK pin */
  287. };
  288. };
  289. spi1 {
  290. pinctrl_spi1: spi1-0 {
  291. atmel,pins =
  292. <1 14 0x1 0x0 /* PB14 periph A SPI1_MISO pin */
  293. 1 15 0x1 0x0 /* PB15 periph A SPI1_MOSI pin */
  294. 1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */
  295. };
  296. };
  297. pioA: gpio@fffff200 {
  298. compatible = "atmel,at91rm9200-gpio";
  299. reg = <0xfffff200 0x200>;
  300. interrupts = <2 4 1>;
  301. #gpio-cells = <2>;
  302. gpio-controller;
  303. interrupt-controller;
  304. #interrupt-cells = <2>;
  305. };
  306. pioB: gpio@fffff400 {
  307. compatible = "atmel,at91rm9200-gpio";
  308. reg = <0xfffff400 0x200>;
  309. interrupts = <3 4 1>;
  310. #gpio-cells = <2>;
  311. gpio-controller;
  312. interrupt-controller;
  313. #interrupt-cells = <2>;
  314. };
  315. pioC: gpio@fffff600 {
  316. compatible = "atmel,at91rm9200-gpio";
  317. reg = <0xfffff600 0x200>;
  318. interrupts = <4 4 1>;
  319. #gpio-cells = <2>;
  320. gpio-controller;
  321. interrupt-controller;
  322. #interrupt-cells = <2>;
  323. };
  324. pioD: gpio@fffff800 {
  325. compatible = "atmel,at91rm9200-gpio";
  326. reg = <0xfffff800 0x200>;
  327. interrupts = <5 4 1>;
  328. #gpio-cells = <2>;
  329. gpio-controller;
  330. interrupt-controller;
  331. #interrupt-cells = <2>;
  332. };
  333. pioE: gpio@fffffa00 {
  334. compatible = "atmel,at91rm9200-gpio";
  335. reg = <0xfffffa00 0x200>;
  336. interrupts = <5 4 1>;
  337. #gpio-cells = <2>;
  338. gpio-controller;
  339. interrupt-controller;
  340. #interrupt-cells = <2>;
  341. };
  342. };
  343. dbgu: serial@ffffee00 {
  344. compatible = "atmel,at91sam9260-usart";
  345. reg = <0xffffee00 0x200>;
  346. interrupts = <1 4 7>;
  347. pinctrl-names = "default";
  348. pinctrl-0 = <&pinctrl_dbgu>;
  349. status = "disabled";
  350. };
  351. usart0: serial@fff8c000 {
  352. compatible = "atmel,at91sam9260-usart";
  353. reg = <0xfff8c000 0x200>;
  354. interrupts = <7 4 5>;
  355. atmel,use-dma-rx;
  356. atmel,use-dma-tx;
  357. pinctrl-names = "default";
  358. pinctrl-0 = <&pinctrl_usart0>;
  359. status = "disabled";
  360. };
  361. usart1: serial@fff90000 {
  362. compatible = "atmel,at91sam9260-usart";
  363. reg = <0xfff90000 0x200>;
  364. interrupts = <8 4 5>;
  365. atmel,use-dma-rx;
  366. atmel,use-dma-tx;
  367. pinctrl-names = "default";
  368. pinctrl-0 = <&pinctrl_usart1>;
  369. status = "disabled";
  370. };
  371. usart2: serial@fff94000 {
  372. compatible = "atmel,at91sam9260-usart";
  373. reg = <0xfff94000 0x200>;
  374. interrupts = <9 4 5>;
  375. atmel,use-dma-rx;
  376. atmel,use-dma-tx;
  377. pinctrl-names = "default";
  378. pinctrl-0 = <&pinctrl_usart2>;
  379. status = "disabled";
  380. };
  381. usart3: serial@fff98000 {
  382. compatible = "atmel,at91sam9260-usart";
  383. reg = <0xfff98000 0x200>;
  384. interrupts = <10 4 5>;
  385. atmel,use-dma-rx;
  386. atmel,use-dma-tx;
  387. pinctrl-names = "default";
  388. pinctrl-0 = <&pinctrl_usart3>;
  389. status = "disabled";
  390. };
  391. macb0: ethernet@fffbc000 {
  392. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  393. reg = <0xfffbc000 0x100>;
  394. interrupts = <25 4 3>;
  395. pinctrl-names = "default";
  396. pinctrl-0 = <&pinctrl_macb_rmii>;
  397. status = "disabled";
  398. };
  399. i2c0: i2c@fff84000 {
  400. compatible = "atmel,at91sam9g10-i2c";
  401. reg = <0xfff84000 0x100>;
  402. interrupts = <12 4 6>;
  403. #address-cells = <1>;
  404. #size-cells = <0>;
  405. status = "disabled";
  406. };
  407. i2c1: i2c@fff88000 {
  408. compatible = "atmel,at91sam9g10-i2c";
  409. reg = <0xfff88000 0x100>;
  410. interrupts = <13 4 6>;
  411. #address-cells = <1>;
  412. #size-cells = <0>;
  413. status = "disabled";
  414. };
  415. ssc0: ssc@fff9c000 {
  416. compatible = "atmel,at91sam9g45-ssc";
  417. reg = <0xfff9c000 0x4000>;
  418. interrupts = <16 4 5>;
  419. pinctrl-names = "default";
  420. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  421. status = "disabled";
  422. };
  423. ssc1: ssc@fffa0000 {
  424. compatible = "atmel,at91sam9g45-ssc";
  425. reg = <0xfffa0000 0x4000>;
  426. interrupts = <17 4 5>;
  427. pinctrl-names = "default";
  428. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  429. status = "disabled";
  430. };
  431. adc0: adc@fffb0000 {
  432. compatible = "atmel,at91sam9260-adc";
  433. reg = <0xfffb0000 0x100>;
  434. interrupts = <20 4 0>;
  435. atmel,adc-use-external-triggers;
  436. atmel,adc-channels-used = <0xff>;
  437. atmel,adc-vref = <3300>;
  438. atmel,adc-num-channels = <8>;
  439. atmel,adc-startup-time = <40>;
  440. atmel,adc-channel-base = <0x30>;
  441. atmel,adc-drdy-mask = <0x10000>;
  442. atmel,adc-status-register = <0x1c>;
  443. atmel,adc-trigger-register = <0x08>;
  444. atmel,adc-res = <8 10>;
  445. atmel,adc-res-names = "lowres", "highres";
  446. atmel,adc-use-res = "highres";
  447. trigger@0 {
  448. trigger-name = "external-rising";
  449. trigger-value = <0x1>;
  450. trigger-external;
  451. };
  452. trigger@1 {
  453. trigger-name = "external-falling";
  454. trigger-value = <0x2>;
  455. trigger-external;
  456. };
  457. trigger@2 {
  458. trigger-name = "external-any";
  459. trigger-value = <0x3>;
  460. trigger-external;
  461. };
  462. trigger@3 {
  463. trigger-name = "continuous";
  464. trigger-value = <0x6>;
  465. };
  466. };
  467. mmc0: mmc@fff80000 {
  468. compatible = "atmel,hsmci";
  469. reg = <0xfff80000 0x600>;
  470. interrupts = <11 4 0>;
  471. dmas = <&dma 1 0>;
  472. dma-names = "rxtx";
  473. #address-cells = <1>;
  474. #size-cells = <0>;
  475. status = "disabled";
  476. };
  477. mmc1: mmc@fffd0000 {
  478. compatible = "atmel,hsmci";
  479. reg = <0xfffd0000 0x600>;
  480. interrupts = <29 4 0>;
  481. dmas = <&dma 1 13>;
  482. dma-names = "rxtx";
  483. #address-cells = <1>;
  484. #size-cells = <0>;
  485. status = "disabled";
  486. };
  487. watchdog@fffffd40 {
  488. compatible = "atmel,at91sam9260-wdt";
  489. reg = <0xfffffd40 0x10>;
  490. status = "disabled";
  491. };
  492. spi0: spi@fffa4000 {
  493. #address-cells = <1>;
  494. #size-cells = <0>;
  495. compatible = "atmel,at91rm9200-spi";
  496. reg = <0xfffa4000 0x200>;
  497. interrupts = <14 4 3>;
  498. pinctrl-names = "default";
  499. pinctrl-0 = <&pinctrl_spi0>;
  500. status = "disabled";
  501. };
  502. spi1: spi@fffa8000 {
  503. #address-cells = <1>;
  504. #size-cells = <0>;
  505. compatible = "atmel,at91rm9200-spi";
  506. reg = <0xfffa8000 0x200>;
  507. interrupts = <15 4 3>;
  508. pinctrl-names = "default";
  509. pinctrl-0 = <&pinctrl_spi1>;
  510. status = "disabled";
  511. };
  512. };
  513. nand0: nand@40000000 {
  514. compatible = "atmel,at91rm9200-nand";
  515. #address-cells = <1>;
  516. #size-cells = <1>;
  517. reg = <0x40000000 0x10000000
  518. 0xffffe200 0x200
  519. >;
  520. atmel,nand-addr-offset = <21>;
  521. atmel,nand-cmd-offset = <22>;
  522. pinctrl-names = "default";
  523. pinctrl-0 = <&pinctrl_nand>;
  524. gpios = <&pioC 8 0
  525. &pioC 14 0
  526. 0
  527. >;
  528. status = "disabled";
  529. };
  530. usb0: ohci@00700000 {
  531. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  532. reg = <0x00700000 0x100000>;
  533. interrupts = <22 4 2>;
  534. status = "disabled";
  535. };
  536. usb1: ehci@00800000 {
  537. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  538. reg = <0x00800000 0x100000>;
  539. interrupts = <22 4 2>;
  540. status = "disabled";
  541. };
  542. };
  543. i2c@0 {
  544. compatible = "i2c-gpio";
  545. gpios = <&pioA 20 0 /* sda */
  546. &pioA 21 0 /* scl */
  547. >;
  548. i2c-gpio,sda-open-drain;
  549. i2c-gpio,scl-open-drain;
  550. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  551. #address-cells = <1>;
  552. #size-cells = <0>;
  553. status = "disabled";
  554. };
  555. };