at91rm9200.dtsi 12 KB

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  1. /*
  2. * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2012 Joachim Eastwood <manabian@gmail.com>
  7. *
  8. * Based on at91sam9260.dtsi
  9. *
  10. * Licensed under GPLv2 or later.
  11. */
  12. /include/ "skeleton.dtsi"
  13. / {
  14. model = "Atmel AT91RM9200 family SoC";
  15. compatible = "atmel,at91rm9200";
  16. interrupt-parent = <&aic>;
  17. aliases {
  18. serial0 = &dbgu;
  19. serial1 = &usart0;
  20. serial2 = &usart1;
  21. serial3 = &usart2;
  22. serial4 = &usart3;
  23. gpio0 = &pioA;
  24. gpio1 = &pioB;
  25. gpio2 = &pioC;
  26. gpio3 = &pioD;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. ssc0 = &ssc0;
  31. ssc1 = &ssc1;
  32. ssc2 = &ssc2;
  33. };
  34. cpus {
  35. cpu@0 {
  36. compatible = "arm,arm920t";
  37. };
  38. };
  39. memory {
  40. reg = <0x20000000 0x04000000>;
  41. };
  42. ahb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. apb {
  48. compatible = "simple-bus";
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. ranges;
  52. aic: interrupt-controller@fffff000 {
  53. #interrupt-cells = <3>;
  54. compatible = "atmel,at91rm9200-aic";
  55. interrupt-controller;
  56. reg = <0xfffff000 0x200>;
  57. atmel,external-irqs = <25 26 27 28 29 30 31>;
  58. };
  59. ramc0: ramc@ffffff00 {
  60. compatible = "atmel,at91rm9200-sdramc";
  61. reg = <0xffffff00 0x100>;
  62. };
  63. pmc: pmc@fffffc00 {
  64. compatible = "atmel,at91rm9200-pmc";
  65. reg = <0xfffffc00 0x100>;
  66. };
  67. st: timer@fffffd00 {
  68. compatible = "atmel,at91rm9200-st";
  69. reg = <0xfffffd00 0x100>;
  70. interrupts = <1 4 7>;
  71. };
  72. tcb0: timer@fffa0000 {
  73. compatible = "atmel,at91rm9200-tcb";
  74. reg = <0xfffa0000 0x100>;
  75. interrupts = <17 4 0 18 4 0 19 4 0>;
  76. };
  77. tcb1: timer@fffa4000 {
  78. compatible = "atmel,at91rm9200-tcb";
  79. reg = <0xfffa4000 0x100>;
  80. interrupts = <20 4 0 21 4 0 22 4 0>;
  81. };
  82. i2c0: i2c@fffb8000 {
  83. compatible = "atmel,at91rm9200-i2c";
  84. reg = <0xfffb8000 0x4000>;
  85. interrupts = <12 4 6>;
  86. pinctrl-names = "default";
  87. pinctrl-0 = <&pinctrl_twi>;
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. status = "disabled";
  91. };
  92. mmc0: mmc@fffb4000 {
  93. compatible = "atmel,hsmci";
  94. reg = <0xfffb4000 0x4000>;
  95. interrupts = <10 4 0>;
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. status = "disabled";
  99. };
  100. ssc0: ssc@fffd0000 {
  101. compatible = "atmel,at91rm9200-ssc";
  102. reg = <0xfffd0000 0x4000>;
  103. interrupts = <14 4 5>;
  104. pinctrl-names = "default";
  105. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  106. status = "disable";
  107. };
  108. ssc1: ssc@fffd4000 {
  109. compatible = "atmel,at91rm9200-ssc";
  110. reg = <0xfffd4000 0x4000>;
  111. interrupts = <15 4 5>;
  112. pinctrl-names = "default";
  113. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  114. status = "disable";
  115. };
  116. ssc2: ssc@fffd8000 {
  117. compatible = "atmel,at91rm9200-ssc";
  118. reg = <0xfffd8000 0x4000>;
  119. interrupts = <16 4 5>;
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
  122. status = "disable";
  123. };
  124. macb0: ethernet@fffbc000 {
  125. compatible = "cdns,at91rm9200-emac", "cdns,emac";
  126. reg = <0xfffbc000 0x4000>;
  127. interrupts = <24 4 3>;
  128. phy-mode = "rmii";
  129. pinctrl-names = "default";
  130. pinctrl-0 = <&pinctrl_macb_rmii>;
  131. status = "disabled";
  132. };
  133. pinctrl@fffff400 {
  134. #address-cells = <1>;
  135. #size-cells = <1>;
  136. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  137. ranges = <0xfffff400 0xfffff400 0x800>;
  138. atmel,mux-mask = <
  139. /* A B */
  140. 0xffffffff 0xffffffff /* pioA */
  141. 0xffffffff 0x083fffff /* pioB */
  142. 0xffff3fff 0x00000000 /* pioC */
  143. 0x03ff87ff 0x0fffff80 /* pioD */
  144. >;
  145. /* shared pinctrl settings */
  146. dbgu {
  147. pinctrl_dbgu: dbgu-0 {
  148. atmel,pins =
  149. <0 30 0x1 0x0 /* PA30 periph A */
  150. 0 31 0x1 0x1>; /* PA31 periph with pullup */
  151. };
  152. };
  153. uart0 {
  154. pinctrl_uart0: uart0-0 {
  155. atmel,pins =
  156. <0 17 0x1 0x0 /* PA17 periph A */
  157. 0 18 0x1 0x0>; /* PA18 periph A */
  158. };
  159. pinctrl_uart0_rts: uart0_rts-0 {
  160. atmel,pins =
  161. <0 20 0x1 0x0>; /* PA20 periph A */
  162. };
  163. pinctrl_uart0_cts: uart0_cts-0 {
  164. atmel,pins =
  165. <0 21 0x1 0x0>; /* PA21 periph A */
  166. };
  167. };
  168. uart1 {
  169. pinctrl_uart1: uart1-0 {
  170. atmel,pins =
  171. <1 20 0x1 0x1 /* PB20 periph A with pullup */
  172. 1 21 0x1 0x0>; /* PB21 periph A */
  173. };
  174. pinctrl_uart1_rts: uart1_rts-0 {
  175. atmel,pins =
  176. <1 24 0x1 0x0>; /* PB24 periph A */
  177. };
  178. pinctrl_uart1_cts: uart1_cts-0 {
  179. atmel,pins =
  180. <1 26 0x1 0x0>; /* PB26 periph A */
  181. };
  182. pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
  183. atmel,pins =
  184. <1 19 0x1 0x0 /* PB19 periph A */
  185. 1 25 0x1 0x0>; /* PB25 periph A */
  186. };
  187. pinctrl_uart1_dcd: uart1_dcd-0 {
  188. atmel,pins =
  189. <1 23 0x1 0x0>; /* PB23 periph A */
  190. };
  191. pinctrl_uart1_ri: uart1_ri-0 {
  192. atmel,pins =
  193. <1 18 0x1 0x0>; /* PB18 periph A */
  194. };
  195. };
  196. uart2 {
  197. pinctrl_uart2: uart2-0 {
  198. atmel,pins =
  199. <0 22 0x1 0x0 /* PA22 periph A */
  200. 0 23 0x1 0x1>; /* PA23 periph A with pullup */
  201. };
  202. pinctrl_uart2_rts: uart2_rts-0 {
  203. atmel,pins =
  204. <0 30 0x2 0x0>; /* PA30 periph B */
  205. };
  206. pinctrl_uart2_cts: uart2_cts-0 {
  207. atmel,pins =
  208. <0 31 0x2 0x0>; /* PA31 periph B */
  209. };
  210. };
  211. uart3 {
  212. pinctrl_uart3: uart3-0 {
  213. atmel,pins =
  214. <0 5 0x2 0x1 /* PA5 periph B with pullup */
  215. 0 6 0x2 0x0>; /* PA6 periph B */
  216. };
  217. pinctrl_uart3_rts: uart3_rts-0 {
  218. atmel,pins =
  219. <1 0 0x2 0x0>; /* PB0 periph B */
  220. };
  221. pinctrl_uart3_cts: uart3_cts-0 {
  222. atmel,pins =
  223. <1 1 0x2 0x0>; /* PB1 periph B */
  224. };
  225. };
  226. nand {
  227. pinctrl_nand: nand-0 {
  228. atmel,pins =
  229. <2 2 0x0 0x1 /* PC2 gpio RDY pin pull_up */
  230. 1 1 0x0 0x1>; /* PB1 gpio CD pin pull_up */
  231. };
  232. };
  233. macb {
  234. pinctrl_macb_rmii: macb_rmii-0 {
  235. atmel,pins =
  236. <0 7 0x1 0x0 /* PA7 periph A */
  237. 0 8 0x1 0x0 /* PA8 periph A */
  238. 0 9 0x1 0x0 /* PA9 periph A */
  239. 0 10 0x1 0x0 /* PA10 periph A */
  240. 0 11 0x1 0x0 /* PA11 periph A */
  241. 0 12 0x1 0x0 /* PA12 periph A */
  242. 0 13 0x1 0x0 /* PA13 periph A */
  243. 0 14 0x1 0x0 /* PA14 periph A */
  244. 0 15 0x1 0x0 /* PA15 periph A */
  245. 0 16 0x1 0x0>; /* PA16 periph A */
  246. };
  247. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  248. atmel,pins =
  249. <1 12 0x2 0x0 /* PB12 periph B */
  250. 1 13 0x2 0x0 /* PB13 periph B */
  251. 1 14 0x2 0x0 /* PB14 periph B */
  252. 1 15 0x2 0x0 /* PB15 periph B */
  253. 1 16 0x2 0x0 /* PB16 periph B */
  254. 1 17 0x2 0x0 /* PB17 periph B */
  255. 1 18 0x2 0x0 /* PB18 periph B */
  256. 1 19 0x2 0x0>; /* PB19 periph B */
  257. };
  258. };
  259. mmc0 {
  260. pinctrl_mmc0_clk: mmc0_clk-0 {
  261. atmel,pins =
  262. <0 27 0x1 0x0>; /* PA27 periph A */
  263. };
  264. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  265. atmel,pins =
  266. <0 28 0x1 0x1 /* PA28 periph A with pullup */
  267. 0 29 0x1 0x1>; /* PA29 periph A with pullup */
  268. };
  269. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  270. atmel,pins =
  271. <1 3 0x2 0x1 /* PB3 periph B with pullup */
  272. 1 4 0x2 0x1 /* PB4 periph B with pullup */
  273. 1 5 0x2 0x1>; /* PB5 periph B with pullup */
  274. };
  275. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  276. atmel,pins =
  277. <0 8 0x2 0x1 /* PA8 periph B with pullup */
  278. 0 9 0x2 0x1>; /* PA9 periph B with pullup */
  279. };
  280. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  281. atmel,pins =
  282. <0 10 0x2 0x1 /* PA10 periph B with pullup */
  283. 0 11 0x2 0x1 /* PA11 periph B with pullup */
  284. 0 12 0x2 0x1>; /* PA12 periph B with pullup */
  285. };
  286. };
  287. ssc0 {
  288. pinctrl_ssc0_tx: ssc0_tx-0 {
  289. atmel,pins =
  290. <1 0 0x1 0x0 /* PB0 periph A */
  291. 1 1 0x1 0x0 /* PB1 periph A */
  292. 1 2 0x1 0x0>; /* PB2 periph A */
  293. };
  294. pinctrl_ssc0_rx: ssc0_rx-0 {
  295. atmel,pins =
  296. <1 3 0x1 0x0 /* PB3 periph A */
  297. 1 4 0x1 0x0 /* PB4 periph A */
  298. 1 5 0x1 0x0>; /* PB5 periph A */
  299. };
  300. };
  301. ssc1 {
  302. pinctrl_ssc1_tx: ssc1_tx-0 {
  303. atmel,pins =
  304. <1 6 0x1 0x0 /* PB6 periph A */
  305. 1 7 0x1 0x0 /* PB7 periph A */
  306. 1 8 0x1 0x0>; /* PB8 periph A */
  307. };
  308. pinctrl_ssc1_rx: ssc1_rx-0 {
  309. atmel,pins =
  310. <1 9 0x1 0x0 /* PB9 periph A */
  311. 1 10 0x1 0x0 /* PB10 periph A */
  312. 1 11 0x1 0x0>; /* PB11 periph A */
  313. };
  314. };
  315. ssc2 {
  316. pinctrl_ssc2_tx: ssc2_tx-0 {
  317. atmel,pins =
  318. <1 12 0x1 0x0 /* PB12 periph A */
  319. 1 13 0x1 0x0 /* PB13 periph A */
  320. 1 14 0x1 0x0>; /* PB14 periph A */
  321. };
  322. pinctrl_ssc2_rx: ssc2_rx-0 {
  323. atmel,pins =
  324. <1 15 0x1 0x0 /* PB15 periph A */
  325. 1 16 0x1 0x0 /* PB16 periph A */
  326. 1 17 0x1 0x0>; /* PB17 periph A */
  327. };
  328. };
  329. twi {
  330. pinctrl_twi: twi-0 {
  331. atmel,pins =
  332. <0 25 0x1 0x2 /* PA25 periph A with multi drive */
  333. 0 26 0x1 0x2>; /* PA26 periph A with multi drive */
  334. };
  335. pinctrl_twi_gpio: twi_gpio-0 {
  336. atmel,pins =
  337. <0 25 0x0 0x2 /* PA25 GPIO with multi drive */
  338. 0 26 0x0 0x2>; /* PA26 GPIO with multi drive */
  339. };
  340. };
  341. pioA: gpio@fffff400 {
  342. compatible = "atmel,at91rm9200-gpio";
  343. reg = <0xfffff400 0x200>;
  344. interrupts = <2 4 1>;
  345. #gpio-cells = <2>;
  346. gpio-controller;
  347. interrupt-controller;
  348. #interrupt-cells = <2>;
  349. };
  350. pioB: gpio@fffff600 {
  351. compatible = "atmel,at91rm9200-gpio";
  352. reg = <0xfffff600 0x200>;
  353. interrupts = <3 4 1>;
  354. #gpio-cells = <2>;
  355. gpio-controller;
  356. interrupt-controller;
  357. #interrupt-cells = <2>;
  358. };
  359. pioC: gpio@fffff800 {
  360. compatible = "atmel,at91rm9200-gpio";
  361. reg = <0xfffff800 0x200>;
  362. interrupts = <4 4 1>;
  363. #gpio-cells = <2>;
  364. gpio-controller;
  365. interrupt-controller;
  366. #interrupt-cells = <2>;
  367. };
  368. pioD: gpio@fffffa00 {
  369. compatible = "atmel,at91rm9200-gpio";
  370. reg = <0xfffffa00 0x200>;
  371. interrupts = <5 4 1>;
  372. #gpio-cells = <2>;
  373. gpio-controller;
  374. interrupt-controller;
  375. #interrupt-cells = <2>;
  376. };
  377. };
  378. dbgu: serial@fffff200 {
  379. compatible = "atmel,at91rm9200-usart";
  380. reg = <0xfffff200 0x200>;
  381. interrupts = <1 4 7>;
  382. pinctrl-names = "default";
  383. pinctrl-0 = <&pinctrl_dbgu>;
  384. status = "disabled";
  385. };
  386. usart0: serial@fffc0000 {
  387. compatible = "atmel,at91rm9200-usart";
  388. reg = <0xfffc0000 0x200>;
  389. interrupts = <6 4 5>;
  390. atmel,use-dma-rx;
  391. atmel,use-dma-tx;
  392. pinctrl-names = "default";
  393. pinctrl-0 = <&pinctrl_uart0>;
  394. status = "disabled";
  395. };
  396. usart1: serial@fffc4000 {
  397. compatible = "atmel,at91rm9200-usart";
  398. reg = <0xfffc4000 0x200>;
  399. interrupts = <7 4 5>;
  400. atmel,use-dma-rx;
  401. atmel,use-dma-tx;
  402. pinctrl-names = "default";
  403. pinctrl-0 = <&pinctrl_uart1>;
  404. status = "disabled";
  405. };
  406. usart2: serial@fffc8000 {
  407. compatible = "atmel,at91rm9200-usart";
  408. reg = <0xfffc8000 0x200>;
  409. interrupts = <8 4 5>;
  410. atmel,use-dma-rx;
  411. atmel,use-dma-tx;
  412. pinctrl-names = "default";
  413. pinctrl-0 = <&pinctrl_uart2>;
  414. status = "disabled";
  415. };
  416. usart3: serial@fffcc000 {
  417. compatible = "atmel,at91rm9200-usart";
  418. reg = <0xfffcc000 0x200>;
  419. interrupts = <23 4 5>;
  420. atmel,use-dma-rx;
  421. atmel,use-dma-tx;
  422. pinctrl-names = "default";
  423. pinctrl-0 = <&pinctrl_uart3>;
  424. status = "disabled";
  425. };
  426. usb1: gadget@fffb0000 {
  427. compatible = "atmel,at91rm9200-udc";
  428. reg = <0xfffb0000 0x4000>;
  429. interrupts = <11 4 2>;
  430. status = "disabled";
  431. };
  432. };
  433. nand0: nand@40000000 {
  434. compatible = "atmel,at91rm9200-nand";
  435. #address-cells = <1>;
  436. #size-cells = <1>;
  437. reg = <0x40000000 0x10000000>;
  438. atmel,nand-addr-offset = <21>;
  439. atmel,nand-cmd-offset = <22>;
  440. pinctrl-names = "default";
  441. pinctrl-0 = <&pinctrl_nand>;
  442. nand-ecc-mode = "soft";
  443. gpios = <&pioC 2 0
  444. 0
  445. &pioB 1 0
  446. >;
  447. status = "disabled";
  448. };
  449. usb0: ohci@00300000 {
  450. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  451. reg = <0x00300000 0x100000>;
  452. interrupts = <23 4 2>;
  453. status = "disabled";
  454. };
  455. };
  456. i2c@0 {
  457. compatible = "i2c-gpio";
  458. gpios = <&pioA 25 0 /* sda */
  459. &pioA 26 0 /* scl */
  460. >;
  461. i2c-gpio,sda-open-drain;
  462. i2c-gpio,scl-open-drain;
  463. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  464. pinctrl-names = "default";
  465. pinctrl-0 = <&pinctrl_twi_gpio>;
  466. #address-cells = <1>;
  467. #size-cells = <0>;
  468. status = "disabled";
  469. };
  470. };