armada-xp-db.dts 2.8 KB

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  1. /*
  2. * Device Tree file for Marvell Armada XP evaluation board
  3. * (DB-78460-BP)
  4. *
  5. * Copyright (C) 2012 Marvell
  6. *
  7. * Lior Amsalem <alior@marvell.com>
  8. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  9. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. /dts-v1/;
  16. /include/ "armada-xp-mv78460.dtsi"
  17. / {
  18. model = "Marvell Armada XP Evaluation Board";
  19. compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  20. chosen {
  21. bootargs = "console=ttyS0,115200 earlyprintk";
  22. };
  23. memory {
  24. device_type = "memory";
  25. reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
  26. };
  27. soc {
  28. internal-regs {
  29. serial@12000 {
  30. clock-frequency = <250000000>;
  31. status = "okay";
  32. };
  33. serial@12100 {
  34. clock-frequency = <250000000>;
  35. status = "okay";
  36. };
  37. serial@12200 {
  38. clock-frequency = <250000000>;
  39. status = "okay";
  40. };
  41. serial@12300 {
  42. clock-frequency = <250000000>;
  43. status = "okay";
  44. };
  45. sata@a0000 {
  46. nr-ports = <2>;
  47. status = "okay";
  48. };
  49. mdio {
  50. phy0: ethernet-phy@0 {
  51. reg = <0>;
  52. };
  53. phy1: ethernet-phy@1 {
  54. reg = <1>;
  55. };
  56. phy2: ethernet-phy@2 {
  57. reg = <25>;
  58. };
  59. phy3: ethernet-phy@3 {
  60. reg = <27>;
  61. };
  62. };
  63. ethernet@70000 {
  64. status = "okay";
  65. phy = <&phy0>;
  66. phy-mode = "rgmii-id";
  67. };
  68. ethernet@74000 {
  69. status = "okay";
  70. phy = <&phy1>;
  71. phy-mode = "rgmii-id";
  72. };
  73. ethernet@30000 {
  74. status = "okay";
  75. phy = <&phy2>;
  76. phy-mode = "sgmii";
  77. };
  78. ethernet@34000 {
  79. status = "okay";
  80. phy = <&phy3>;
  81. phy-mode = "sgmii";
  82. };
  83. mvsdio@d4000 {
  84. pinctrl-0 = <&sdio_pins>;
  85. pinctrl-names = "default";
  86. status = "okay";
  87. /* No CD or WP GPIOs */
  88. };
  89. usb@50000 {
  90. status = "okay";
  91. };
  92. usb@51000 {
  93. status = "okay";
  94. };
  95. usb@52000 {
  96. status = "okay";
  97. };
  98. spi0: spi@10600 {
  99. status = "okay";
  100. spi-flash@0 {
  101. #address-cells = <1>;
  102. #size-cells = <1>;
  103. compatible = "m25p64";
  104. reg = <0>; /* Chip select 0 */
  105. spi-max-frequency = <20000000>;
  106. };
  107. };
  108. pcie-controller {
  109. status = "okay";
  110. /*
  111. * All 6 slots are physically present as
  112. * standard PCIe slots on the board.
  113. */
  114. pcie@1,0 {
  115. /* Port 0, Lane 0 */
  116. status = "okay";
  117. };
  118. pcie@2,0 {
  119. /* Port 0, Lane 1 */
  120. status = "okay";
  121. };
  122. pcie@3,0 {
  123. /* Port 0, Lane 2 */
  124. status = "okay";
  125. };
  126. pcie@4,0 {
  127. /* Port 0, Lane 3 */
  128. status = "okay";
  129. };
  130. pcie@9,0 {
  131. /* Port 2, Lane 0 */
  132. status = "okay";
  133. };
  134. pcie@10,0 {
  135. /* Port 3, Lane 0 */
  136. status = "okay";
  137. };
  138. };
  139. };
  140. };
  141. };