am33xx.dtsi 9.0 KB

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  1. /*
  2. * Device Tree Source for AM33XX SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "ti,am33xx";
  13. interrupt-parent = <&intc>;
  14. aliases {
  15. serial0 = &uart1;
  16. serial1 = &uart2;
  17. serial2 = &uart3;
  18. serial3 = &uart4;
  19. serial4 = &uart5;
  20. serial5 = &uart6;
  21. d_can0 = &dcan0;
  22. d_can1 = &dcan1;
  23. };
  24. cpus {
  25. cpu@0 {
  26. compatible = "arm,cortex-a8";
  27. /*
  28. * To consider voltage drop between PMIC and SoC,
  29. * tolerance value is reduced to 2% from 4% and
  30. * voltage value is increased as a precaution.
  31. */
  32. operating-points = <
  33. /* kHz uV */
  34. 720000 1285000
  35. 600000 1225000
  36. 500000 1125000
  37. 275000 1125000
  38. >;
  39. voltage-tolerance = <2>; /* 2 percentage */
  40. clock-latency = <300000>; /* From omap-cpufreq driver */
  41. };
  42. };
  43. /*
  44. * The soc node represents the soc top level view. It is uses for IPs
  45. * that are not memory mapped in the MPU view or for the MPU itself.
  46. */
  47. soc {
  48. compatible = "ti,omap-infra";
  49. mpu {
  50. compatible = "ti,omap3-mpu";
  51. ti,hwmods = "mpu";
  52. };
  53. };
  54. am33xx_pinmux: pinmux@44e10800 {
  55. compatible = "pinctrl-single";
  56. reg = <0x44e10800 0x0238>;
  57. #address-cells = <1>;
  58. #size-cells = <0>;
  59. pinctrl-single,register-width = <32>;
  60. pinctrl-single,function-mask = <0x7f>;
  61. };
  62. /*
  63. * XXX: Use a flat representation of the AM33XX interconnect.
  64. * The real AM33XX interconnect network is quite complex.Since
  65. * that will not bring real advantage to represent that in DT
  66. * for the moment, just use a fake OCP bus entry to represent
  67. * the whole bus hierarchy.
  68. */
  69. ocp {
  70. compatible = "simple-bus";
  71. #address-cells = <1>;
  72. #size-cells = <1>;
  73. ranges;
  74. ti,hwmods = "l3_main";
  75. intc: interrupt-controller@48200000 {
  76. compatible = "ti,omap2-intc";
  77. interrupt-controller;
  78. #interrupt-cells = <1>;
  79. ti,intc-size = <128>;
  80. reg = <0x48200000 0x1000>;
  81. };
  82. gpio0: gpio@44e07000 {
  83. compatible = "ti,omap4-gpio";
  84. ti,hwmods = "gpio1";
  85. gpio-controller;
  86. #gpio-cells = <2>;
  87. interrupt-controller;
  88. #interrupt-cells = <1>;
  89. reg = <0x44e07000 0x1000>;
  90. interrupts = <96>;
  91. };
  92. gpio1: gpio@4804c000 {
  93. compatible = "ti,omap4-gpio";
  94. ti,hwmods = "gpio2";
  95. gpio-controller;
  96. #gpio-cells = <2>;
  97. interrupt-controller;
  98. #interrupt-cells = <1>;
  99. reg = <0x4804c000 0x1000>;
  100. interrupts = <98>;
  101. };
  102. gpio2: gpio@481ac000 {
  103. compatible = "ti,omap4-gpio";
  104. ti,hwmods = "gpio3";
  105. gpio-controller;
  106. #gpio-cells = <2>;
  107. interrupt-controller;
  108. #interrupt-cells = <1>;
  109. reg = <0x481ac000 0x1000>;
  110. interrupts = <32>;
  111. };
  112. gpio3: gpio@481ae000 {
  113. compatible = "ti,omap4-gpio";
  114. ti,hwmods = "gpio4";
  115. gpio-controller;
  116. #gpio-cells = <2>;
  117. interrupt-controller;
  118. #interrupt-cells = <1>;
  119. reg = <0x481ae000 0x1000>;
  120. interrupts = <62>;
  121. };
  122. uart1: serial@44e09000 {
  123. compatible = "ti,omap3-uart";
  124. ti,hwmods = "uart1";
  125. clock-frequency = <48000000>;
  126. reg = <0x44e09000 0x2000>;
  127. interrupts = <72>;
  128. status = "disabled";
  129. };
  130. uart2: serial@48022000 {
  131. compatible = "ti,omap3-uart";
  132. ti,hwmods = "uart2";
  133. clock-frequency = <48000000>;
  134. reg = <0x48022000 0x2000>;
  135. interrupts = <73>;
  136. status = "disabled";
  137. };
  138. uart3: serial@48024000 {
  139. compatible = "ti,omap3-uart";
  140. ti,hwmods = "uart3";
  141. clock-frequency = <48000000>;
  142. reg = <0x48024000 0x2000>;
  143. interrupts = <74>;
  144. status = "disabled";
  145. };
  146. uart4: serial@481a6000 {
  147. compatible = "ti,omap3-uart";
  148. ti,hwmods = "uart4";
  149. clock-frequency = <48000000>;
  150. reg = <0x481a6000 0x2000>;
  151. interrupts = <44>;
  152. status = "disabled";
  153. };
  154. uart5: serial@481a8000 {
  155. compatible = "ti,omap3-uart";
  156. ti,hwmods = "uart5";
  157. clock-frequency = <48000000>;
  158. reg = <0x481a8000 0x2000>;
  159. interrupts = <45>;
  160. status = "disabled";
  161. };
  162. uart6: serial@481aa000 {
  163. compatible = "ti,omap3-uart";
  164. ti,hwmods = "uart6";
  165. clock-frequency = <48000000>;
  166. reg = <0x481aa000 0x2000>;
  167. interrupts = <46>;
  168. status = "disabled";
  169. };
  170. i2c0: i2c@44e0b000 {
  171. compatible = "ti,omap4-i2c";
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. ti,hwmods = "i2c1";
  175. reg = <0x44e0b000 0x1000>;
  176. interrupts = <70>;
  177. status = "disabled";
  178. };
  179. i2c1: i2c@4802a000 {
  180. compatible = "ti,omap4-i2c";
  181. #address-cells = <1>;
  182. #size-cells = <0>;
  183. ti,hwmods = "i2c2";
  184. reg = <0x4802a000 0x1000>;
  185. interrupts = <71>;
  186. status = "disabled";
  187. };
  188. i2c2: i2c@4819c000 {
  189. compatible = "ti,omap4-i2c";
  190. #address-cells = <1>;
  191. #size-cells = <0>;
  192. ti,hwmods = "i2c3";
  193. reg = <0x4819c000 0x1000>;
  194. interrupts = <30>;
  195. status = "disabled";
  196. };
  197. wdt2: wdt@44e35000 {
  198. compatible = "ti,omap3-wdt";
  199. ti,hwmods = "wd_timer2";
  200. reg = <0x44e35000 0x1000>;
  201. interrupts = <91>;
  202. };
  203. dcan0: d_can@481cc000 {
  204. compatible = "bosch,d_can";
  205. ti,hwmods = "d_can0";
  206. reg = <0x481cc000 0x2000
  207. 0x44e10644 0x4>;
  208. interrupts = <52>;
  209. status = "disabled";
  210. };
  211. dcan1: d_can@481d0000 {
  212. compatible = "bosch,d_can";
  213. ti,hwmods = "d_can1";
  214. reg = <0x481d0000 0x2000
  215. 0x44e10644 0x4>;
  216. interrupts = <55>;
  217. status = "disabled";
  218. };
  219. timer1: timer@44e31000 {
  220. compatible = "ti,am335x-timer-1ms";
  221. reg = <0x44e31000 0x400>;
  222. interrupts = <67>;
  223. ti,hwmods = "timer1";
  224. ti,timer-alwon;
  225. };
  226. timer2: timer@48040000 {
  227. compatible = "ti,am335x-timer";
  228. reg = <0x48040000 0x400>;
  229. interrupts = <68>;
  230. ti,hwmods = "timer2";
  231. };
  232. timer3: timer@48042000 {
  233. compatible = "ti,am335x-timer";
  234. reg = <0x48042000 0x400>;
  235. interrupts = <69>;
  236. ti,hwmods = "timer3";
  237. };
  238. timer4: timer@48044000 {
  239. compatible = "ti,am335x-timer";
  240. reg = <0x48044000 0x400>;
  241. interrupts = <92>;
  242. ti,hwmods = "timer4";
  243. ti,timer-pwm;
  244. };
  245. timer5: timer@48046000 {
  246. compatible = "ti,am335x-timer";
  247. reg = <0x48046000 0x400>;
  248. interrupts = <93>;
  249. ti,hwmods = "timer5";
  250. ti,timer-pwm;
  251. };
  252. timer6: timer@48048000 {
  253. compatible = "ti,am335x-timer";
  254. reg = <0x48048000 0x400>;
  255. interrupts = <94>;
  256. ti,hwmods = "timer6";
  257. ti,timer-pwm;
  258. };
  259. timer7: timer@4804a000 {
  260. compatible = "ti,am335x-timer";
  261. reg = <0x4804a000 0x400>;
  262. interrupts = <95>;
  263. ti,hwmods = "timer7";
  264. ti,timer-pwm;
  265. };
  266. rtc@44e3e000 {
  267. compatible = "ti,da830-rtc";
  268. reg = <0x44e3e000 0x1000>;
  269. interrupts = <75
  270. 76>;
  271. ti,hwmods = "rtc";
  272. };
  273. spi0: spi@48030000 {
  274. compatible = "ti,omap4-mcspi";
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. reg = <0x48030000 0x400>;
  278. interrupts = <65>;
  279. ti,spi-num-cs = <2>;
  280. ti,hwmods = "spi0";
  281. status = "disabled";
  282. };
  283. spi1: spi@481a0000 {
  284. compatible = "ti,omap4-mcspi";
  285. #address-cells = <1>;
  286. #size-cells = <0>;
  287. reg = <0x481a0000 0x400>;
  288. interrupts = <125>;
  289. ti,spi-num-cs = <2>;
  290. ti,hwmods = "spi1";
  291. status = "disabled";
  292. };
  293. usb@47400000 {
  294. compatible = "ti,musb-am33xx";
  295. reg = <0x47400000 0x1000 /* usbss */
  296. 0x47401000 0x800 /* musb instance 0 */
  297. 0x47401800 0x800>; /* musb instance 1 */
  298. interrupts = <17 /* usbss */
  299. 18 /* musb instance 0 */
  300. 19>; /* musb instance 1 */
  301. multipoint = <1>;
  302. num-eps = <16>;
  303. ram-bits = <12>;
  304. port0-mode = <3>;
  305. port1-mode = <3>;
  306. power = <250>;
  307. ti,hwmods = "usb_otg_hs";
  308. };
  309. mac: ethernet@4a100000 {
  310. compatible = "ti,cpsw";
  311. ti,hwmods = "cpgmac0";
  312. cpdma_channels = <8>;
  313. ale_entries = <1024>;
  314. bd_ram_size = <0x2000>;
  315. no_bd_ram = <0>;
  316. rx_descs = <64>;
  317. mac_control = <0x20>;
  318. slaves = <2>;
  319. active_slave = <0>;
  320. cpts_clock_mult = <0x80000000>;
  321. cpts_clock_shift = <29>;
  322. reg = <0x4a100000 0x800
  323. 0x4a101200 0x100>;
  324. #address-cells = <1>;
  325. #size-cells = <1>;
  326. interrupt-parent = <&intc>;
  327. /*
  328. * c0_rx_thresh_pend
  329. * c0_rx_pend
  330. * c0_tx_pend
  331. * c0_misc_pend
  332. */
  333. interrupts = <40 41 42 43>;
  334. ranges;
  335. davinci_mdio: mdio@4a101000 {
  336. compatible = "ti,davinci_mdio";
  337. #address-cells = <1>;
  338. #size-cells = <0>;
  339. ti,hwmods = "davinci_mdio";
  340. bus_freq = <1000000>;
  341. reg = <0x4a101000 0x100>;
  342. };
  343. cpsw_emac0: slave@4a100200 {
  344. /* Filled in by U-Boot */
  345. mac-address = [ 00 00 00 00 00 00 ];
  346. };
  347. cpsw_emac1: slave@4a100300 {
  348. /* Filled in by U-Boot */
  349. mac-address = [ 00 00 00 00 00 00 ];
  350. };
  351. };
  352. ocmcram: ocmcram@40300000 {
  353. compatible = "ti,am3352-ocmcram";
  354. reg = <0x40300000 0x10000>;
  355. ti,hwmods = "ocmcram";
  356. ti,no_idle_on_suspend;
  357. };
  358. wkup_m3: wkup_m3@44d00000 {
  359. compatible = "ti,am3353-wkup-m3";
  360. reg = <0x44d00000 0x4000 /* M3 UMEM */
  361. 0x44d80000 0x2000>; /* M3 DMEM */
  362. ti,hwmods = "wkup_m3";
  363. };
  364. gpmc: gpmc@50000000 {
  365. compatible = "ti,am3352-gpmc";
  366. ti,hwmods = "gpmc";
  367. reg = <0x50000000 0x2000>;
  368. interrupts = <100>;
  369. num-cs = <7>;
  370. num-waitpins = <2>;
  371. #address-cells = <2>;
  372. #size-cells = <1>;
  373. status = "disabled";
  374. };
  375. };
  376. };