abilis_tb10x.dtsi 6.1 KB

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  1. /*
  2. * Abilis Systems TB10X SOC device tree
  3. *
  4. * Copyright (C) Abilis Systems 2013
  5. *
  6. * Author: Christian Ruppert <christian.ruppert@abilis.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. /* interrupt specifiers
  22. * --------------------
  23. * 0: rising, 1: low, 2: high, 3: falling,
  24. */
  25. / {
  26. compatible = "abilis,arc-tb10x";
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. cpus {
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32. cpu@0 {
  33. device_type = "cpu";
  34. compatible = "snps,arc770d";
  35. reg = <0>;
  36. };
  37. };
  38. soc100 {
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. device_type = "soc";
  42. ranges = <0xfe000000 0xfe000000 0x02000000
  43. 0x000F0000 0x000F0000 0x00010000>;
  44. compatible = "abilis,tb10x", "simple-bus";
  45. pll0: oscillator {
  46. compatible = "fixed-clock";
  47. #clock-cells = <0>;
  48. clock-output-names = "pll0";
  49. };
  50. cpu_clk: clkdiv_cpu {
  51. compatible = "fixed-factor-clock";
  52. #clock-cells = <0>;
  53. clocks = <&pll0>;
  54. clock-output-names = "cpu_clk";
  55. };
  56. ahb_clk: clkdiv_ahb {
  57. compatible = "fixed-factor-clock";
  58. #clock-cells = <0>;
  59. clocks = <&pll0>;
  60. clock-output-names = "ahb_clk";
  61. };
  62. iomux: iomux@FF10601c {
  63. #address-cells = <1>;
  64. #size-cells = <1>;
  65. compatible = "abilis,tb10x-iomux";
  66. reg = <0xFF10601c 0x4>;
  67. };
  68. intc: interrupt-controller {
  69. compatible = "snps,arc700-intc";
  70. interrupt-controller;
  71. #interrupt-cells = <1>;
  72. };
  73. tb10x_ictl: pic@fe002000 {
  74. compatible = "abilis,tb10x_ictl";
  75. reg = <0xFE002000 0x20>;
  76. interrupt-controller;
  77. #interrupt-cells = <2>;
  78. interrupt-parent = <&intc>;
  79. interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
  80. 20 21 22 23 24 25 26 27 28 29 30 31>;
  81. };
  82. uart@FF100000 {
  83. compatible = "snps,dw-apb-uart",
  84. "abilis,simple-pinctrl";
  85. reg = <0xFF100000 0x100>;
  86. clock-frequency = <166666666>;
  87. interrupts = <25 1>;
  88. reg-shift = <2>;
  89. reg-io-width = <4>;
  90. interrupt-parent = <&tb10x_ictl>;
  91. };
  92. ethernet@FE100000 {
  93. compatible = "snps,dwmac-3.70a","snps,dwmac";
  94. reg = <0xFE100000 0x1058>;
  95. interrupt-parent = <&tb10x_ictl>;
  96. interrupts = <6 1>;
  97. interrupt-names = "macirq";
  98. clocks = <&ahb_clk>;
  99. clock-names = "stmmaceth";
  100. };
  101. dma@FE000000 {
  102. compatible = "snps,dma-spear1340";
  103. reg = <0xFE000000 0x400>;
  104. interrupt-parent = <&tb10x_ictl>;
  105. interrupts = <14 1>;
  106. dma-channels = <6>;
  107. dma-requests = <0>;
  108. dma-masters = <1>;
  109. #dma-cells = <3>;
  110. chan_allocation_order = <0>;
  111. chan_priority = <1>;
  112. block_size = <0x7ff>;
  113. data_width = <2 0 0 0>;
  114. clocks = <&ahb_clk>;
  115. clock-names = "hclk";
  116. };
  117. i2c0: i2c@FF120000 {
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. compatible = "snps,designware-i2c";
  121. reg = <0xFF120000 0x1000>;
  122. interrupt-parent = <&tb10x_ictl>;
  123. interrupts = <12 1>;
  124. clocks = <&ahb_clk>;
  125. };
  126. i2c1: i2c@FF121000 {
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. compatible = "snps,designware-i2c";
  130. reg = <0xFF121000 0x1000>;
  131. interrupt-parent = <&tb10x_ictl>;
  132. interrupts = <12 1>;
  133. clocks = <&ahb_clk>;
  134. };
  135. i2c2: i2c@FF122000 {
  136. #address-cells = <1>;
  137. #size-cells = <0>;
  138. compatible = "snps,designware-i2c";
  139. reg = <0xFF122000 0x1000>;
  140. interrupt-parent = <&tb10x_ictl>;
  141. interrupts = <12 1>;
  142. clocks = <&ahb_clk>;
  143. };
  144. i2c3: i2c@FF123000 {
  145. #address-cells = <1>;
  146. #size-cells = <0>;
  147. compatible = "snps,designware-i2c";
  148. reg = <0xFF123000 0x1000>;
  149. interrupt-parent = <&tb10x_ictl>;
  150. interrupts = <12 1>;
  151. clocks = <&ahb_clk>;
  152. };
  153. i2c4: i2c@FF124000 {
  154. #address-cells = <1>;
  155. #size-cells = <0>;
  156. compatible = "snps,designware-i2c";
  157. reg = <0xFF124000 0x1000>;
  158. interrupt-parent = <&tb10x_ictl>;
  159. interrupts = <12 1>;
  160. clocks = <&ahb_clk>;
  161. };
  162. spi0: spi@0xFE010000 {
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. cell-index = <0>;
  166. compatible = "abilis,tb100-spi";
  167. num-cs = <1>;
  168. reg = <0xFE010000 0x20>;
  169. interrupt-parent = <&tb10x_ictl>;
  170. interrupts = <26 1>;
  171. clocks = <&ahb_clk>;
  172. };
  173. spi1: spi@0xFE011000 {
  174. #address-cells = <1>;
  175. #size-cells = <0>;
  176. cell-index = <1>;
  177. compatible = "abilis,tb100-spi",
  178. "abilis,simple-pinctrl";
  179. num-cs = <2>;
  180. reg = <0xFE011000 0x20>;
  181. interrupt-parent = <&tb10x_ictl>;
  182. interrupts = <10 1>;
  183. clocks = <&ahb_clk>;
  184. };
  185. tb10x_tsm: tb10x-tsm@ff316000 {
  186. compatible = "abilis,tb100-tsm";
  187. reg = <0xff316000 0x400>;
  188. interrupt-parent = <&tb10x_ictl>;
  189. interrupts = <17 1>;
  190. output-clkdiv = <4>;
  191. global-packet-delay = <0x21>;
  192. port-packet-delay = <0>;
  193. };
  194. tb10x_stream_proc: tb10x-stream-proc {
  195. compatible = "abilis,tb100-streamproc";
  196. reg = <0xfff00000 0x200>,
  197. <0x000f0000 0x10000>,
  198. <0xfff00200 0x105>,
  199. <0xff10600c 0x1>,
  200. <0xfe001018 0x1>;
  201. reg-names = "mbox",
  202. "sp_iccm",
  203. "mbox_irq",
  204. "cpuctrl",
  205. "a6it_int_force";
  206. interrupt-parent = <&tb10x_ictl>;
  207. interrupts = <20 1>, <19 1>;
  208. interrupt-names = "cmd_irq", "event_irq";
  209. };
  210. tb10x_mdsc0: tb10x-mdscr@FF300000 {
  211. compatible = "abilis,tb100-mdscr";
  212. reg = <0xFF300000 0x7000>;
  213. tb100-mdscr-manage-tsin;
  214. };
  215. tb10x_mscr0: tb10x-mdscr@FF307000 {
  216. compatible = "abilis,tb100-mdscr";
  217. reg = <0xFF307000 0x7000>;
  218. };
  219. tb10x_scr0: tb10x-mdscr@ff30e000 {
  220. compatible = "abilis,tb100-mdscr";
  221. reg = <0xFF30e000 0x4000>;
  222. tb100-mdscr-manage-tsin;
  223. };
  224. tb10x_scr1: tb10x-mdscr@ff312000 {
  225. compatible = "abilis,tb100-mdscr";
  226. reg = <0xFF312000 0x4000>;
  227. tb100-mdscr-manage-tsin;
  228. };
  229. tb10x_wfb: tb10x-wfb@ff319000 {
  230. compatible = "abilis,tb100-wfb";
  231. reg = <0xff319000 0x1000>;
  232. interrupt-parent = <&tb10x_ictl>;
  233. interrupts = <16 1>;
  234. };
  235. };
  236. };