scc_pata.c 21 KB

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  1. /*
  2. * Support for IDE interfaces on Celleb platform
  3. *
  4. * (C) Copyright 2006 TOSHIBA CORPORATION
  5. *
  6. * This code is based on drivers/ide/pci/siimage.c:
  7. * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
  8. * Copyright (C) 2003 Red Hat <alan@redhat.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License along
  21. * with this program; if not, write to the Free Software Foundation, Inc.,
  22. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23. */
  24. #include <linux/types.h>
  25. #include <linux/module.h>
  26. #include <linux/pci.h>
  27. #include <linux/delay.h>
  28. #include <linux/hdreg.h>
  29. #include <linux/ide.h>
  30. #include <linux/init.h>
  31. #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
  32. #define SCC_PATA_NAME "scc IDE"
  33. #define TDVHSEL_MASTER 0x00000001
  34. #define TDVHSEL_SLAVE 0x00000004
  35. #define MODE_JCUSFEN 0x00000080
  36. #define CCKCTRL_ATARESET 0x00040000
  37. #define CCKCTRL_BUFCNT 0x00020000
  38. #define CCKCTRL_CRST 0x00010000
  39. #define CCKCTRL_OCLKEN 0x00000100
  40. #define CCKCTRL_ATACLKOEN 0x00000002
  41. #define CCKCTRL_LCLKEN 0x00000001
  42. #define QCHCD_IOS_SS 0x00000001
  43. #define QCHSD_STPDIAG 0x00020000
  44. #define INTMASK_MSK 0xD1000012
  45. #define INTSTS_SERROR 0x80000000
  46. #define INTSTS_PRERR 0x40000000
  47. #define INTSTS_RERR 0x10000000
  48. #define INTSTS_ICERR 0x01000000
  49. #define INTSTS_BMSINT 0x00000010
  50. #define INTSTS_BMHE 0x00000008
  51. #define INTSTS_IOIRQS 0x00000004
  52. #define INTSTS_INTRQ 0x00000002
  53. #define INTSTS_ACTEINT 0x00000001
  54. #define ECMODE_VALUE 0x01
  55. static struct scc_ports {
  56. unsigned long ctl, dma;
  57. unsigned char hwif_id; /* for removing hwif from system */
  58. } scc_ports[MAX_HWIFS];
  59. /* PIO transfer mode table */
  60. /* JCHST */
  61. static unsigned long JCHSTtbl[2][7] = {
  62. {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
  63. {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
  64. };
  65. /* JCHHT */
  66. static unsigned long JCHHTtbl[2][7] = {
  67. {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
  68. {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
  69. };
  70. /* JCHCT */
  71. static unsigned long JCHCTtbl[2][7] = {
  72. {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
  73. {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
  74. };
  75. /* DMA transfer mode table */
  76. /* JCHDCTM/JCHDCTS */
  77. static unsigned long JCHDCTxtbl[2][7] = {
  78. {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
  79. {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
  80. };
  81. /* JCSTWTM/JCSTWTS */
  82. static unsigned long JCSTWTxtbl[2][7] = {
  83. {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
  84. {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
  85. };
  86. /* JCTSS */
  87. static unsigned long JCTSStbl[2][7] = {
  88. {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
  89. {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
  90. };
  91. /* JCENVT */
  92. static unsigned long JCENVTtbl[2][7] = {
  93. {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
  94. {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
  95. };
  96. /* JCACTSELS/JCACTSELM */
  97. static unsigned long JCACTSELtbl[2][7] = {
  98. {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
  99. {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
  100. };
  101. static u8 scc_ide_inb(unsigned long port)
  102. {
  103. u32 data = in_be32((void*)port);
  104. return (u8)data;
  105. }
  106. static u16 scc_ide_inw(unsigned long port)
  107. {
  108. u32 data = in_be32((void*)port);
  109. return (u16)data;
  110. }
  111. static void scc_ide_insw(unsigned long port, void *addr, u32 count)
  112. {
  113. u16 *ptr = (u16 *)addr;
  114. while (count--) {
  115. *ptr++ = le16_to_cpu(in_be32((void*)port));
  116. }
  117. }
  118. static void scc_ide_insl(unsigned long port, void *addr, u32 count)
  119. {
  120. u16 *ptr = (u16 *)addr;
  121. while (count--) {
  122. *ptr++ = le16_to_cpu(in_be32((void*)port));
  123. *ptr++ = le16_to_cpu(in_be32((void*)port));
  124. }
  125. }
  126. static void scc_ide_outb(u8 addr, unsigned long port)
  127. {
  128. out_be32((void*)port, addr);
  129. }
  130. static void scc_ide_outw(u16 addr, unsigned long port)
  131. {
  132. out_be32((void*)port, addr);
  133. }
  134. static void
  135. scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
  136. {
  137. ide_hwif_t *hwif = HWIF(drive);
  138. out_be32((void*)port, addr);
  139. eieio();
  140. in_be32((void*)(hwif->dma_base + 0x01c));
  141. eieio();
  142. }
  143. static void
  144. scc_ide_outsw(unsigned long port, void *addr, u32 count)
  145. {
  146. u16 *ptr = (u16 *)addr;
  147. while (count--) {
  148. out_be32((void*)port, cpu_to_le16(*ptr++));
  149. }
  150. }
  151. static void
  152. scc_ide_outsl(unsigned long port, void *addr, u32 count)
  153. {
  154. u16 *ptr = (u16 *)addr;
  155. while (count--) {
  156. out_be32((void*)port, cpu_to_le16(*ptr++));
  157. out_be32((void*)port, cpu_to_le16(*ptr++));
  158. }
  159. }
  160. /**
  161. * scc_tune_pio - tune a drive PIO mode
  162. * @drive: drive to tune
  163. * @mode_wanted: the target operating mode
  164. *
  165. * Load the timing settings for this device mode into the
  166. * controller.
  167. */
  168. static void scc_tune_pio(ide_drive_t *drive, const u8 pio)
  169. {
  170. ide_hwif_t *hwif = HWIF(drive);
  171. struct scc_ports *ports = ide_get_hwifdata(hwif);
  172. unsigned long ctl_base = ports->ctl;
  173. unsigned long cckctrl_port = ctl_base + 0xff0;
  174. unsigned long piosht_port = ctl_base + 0x000;
  175. unsigned long pioct_port = ctl_base + 0x004;
  176. unsigned long reg;
  177. int offset;
  178. reg = in_be32((void __iomem *)cckctrl_port);
  179. if (reg & CCKCTRL_ATACLKOEN) {
  180. offset = 1; /* 133MHz */
  181. } else {
  182. offset = 0; /* 100MHz */
  183. }
  184. reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
  185. out_be32((void __iomem *)piosht_port, reg);
  186. reg = JCHCTtbl[offset][pio];
  187. out_be32((void __iomem *)pioct_port, reg);
  188. }
  189. static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
  190. {
  191. scc_tune_pio(drive, pio);
  192. ide_config_drive_speed(drive, XFER_PIO_0 + pio);
  193. }
  194. /**
  195. * scc_tune_chipset - tune a drive DMA mode
  196. * @drive: Drive to set up
  197. * @speed: speed we want to achieve
  198. *
  199. * Load the timing settings for this device mode into the
  200. * controller.
  201. */
  202. static int scc_tune_chipset(ide_drive_t *drive, const u8 speed)
  203. {
  204. ide_hwif_t *hwif = HWIF(drive);
  205. struct scc_ports *ports = ide_get_hwifdata(hwif);
  206. unsigned long ctl_base = ports->ctl;
  207. unsigned long cckctrl_port = ctl_base + 0xff0;
  208. unsigned long mdmact_port = ctl_base + 0x008;
  209. unsigned long mcrcst_port = ctl_base + 0x00c;
  210. unsigned long sdmact_port = ctl_base + 0x010;
  211. unsigned long scrcst_port = ctl_base + 0x014;
  212. unsigned long udenvt_port = ctl_base + 0x018;
  213. unsigned long tdvhsel_port = ctl_base + 0x020;
  214. int is_slave = (&hwif->drives[1] == drive);
  215. int offset, idx;
  216. unsigned long reg;
  217. unsigned long jcactsel;
  218. reg = in_be32((void __iomem *)cckctrl_port);
  219. if (reg & CCKCTRL_ATACLKOEN) {
  220. offset = 1; /* 133MHz */
  221. } else {
  222. offset = 0; /* 100MHz */
  223. }
  224. switch (speed) {
  225. case XFER_UDMA_6:
  226. case XFER_UDMA_5:
  227. case XFER_UDMA_4:
  228. case XFER_UDMA_3:
  229. case XFER_UDMA_2:
  230. case XFER_UDMA_1:
  231. case XFER_UDMA_0:
  232. idx = speed - XFER_UDMA_0;
  233. break;
  234. default:
  235. return 1;
  236. }
  237. jcactsel = JCACTSELtbl[offset][idx];
  238. if (is_slave) {
  239. out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
  240. out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
  241. jcactsel = jcactsel << 2;
  242. out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
  243. } else {
  244. out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
  245. out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
  246. out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
  247. }
  248. reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
  249. out_be32((void __iomem *)udenvt_port, reg);
  250. return ide_config_drive_speed(drive, speed);
  251. }
  252. /**
  253. * scc_configure_drive_for_dma - set up for DMA transfers
  254. * @drive: drive we are going to set up
  255. *
  256. * Set up the drive for DMA, tune the controller and drive as
  257. * required.
  258. * If the drive isn't suitable for DMA or we hit other problems
  259. * then we will drop down to PIO and set up PIO appropriately.
  260. * (return -1)
  261. */
  262. static int scc_config_drive_for_dma(ide_drive_t *drive)
  263. {
  264. if (ide_tune_dma(drive))
  265. return 0;
  266. if (ide_use_fast_pio(drive))
  267. ide_set_max_pio(drive);
  268. return -1;
  269. }
  270. /**
  271. * scc_ide_dma_setup - begin a DMA phase
  272. * @drive: target device
  273. *
  274. * Build an IDE DMA PRD (IDE speak for scatter gather table)
  275. * and then set up the DMA transfer registers.
  276. *
  277. * Returns 0 on success. If a PIO fallback is required then 1
  278. * is returned.
  279. */
  280. static int scc_dma_setup(ide_drive_t *drive)
  281. {
  282. ide_hwif_t *hwif = drive->hwif;
  283. struct request *rq = HWGROUP(drive)->rq;
  284. unsigned int reading;
  285. u8 dma_stat;
  286. if (rq_data_dir(rq))
  287. reading = 0;
  288. else
  289. reading = 1 << 3;
  290. /* fall back to pio! */
  291. if (!ide_build_dmatable(drive, rq)) {
  292. ide_map_sg(drive, rq);
  293. return 1;
  294. }
  295. /* PRD table */
  296. out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
  297. /* specify r/w */
  298. out_be32((void __iomem *)hwif->dma_command, reading);
  299. /* read dma_status for INTR & ERROR flags */
  300. dma_stat = in_be32((void __iomem *)hwif->dma_status);
  301. /* clear INTR & ERROR flags */
  302. out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
  303. drive->waiting_for_dma = 1;
  304. return 0;
  305. }
  306. /**
  307. * scc_ide_dma_end - Stop DMA
  308. * @drive: IDE drive
  309. *
  310. * Check and clear INT Status register.
  311. * Then call __ide_dma_end().
  312. */
  313. static int scc_ide_dma_end(ide_drive_t * drive)
  314. {
  315. ide_hwif_t *hwif = HWIF(drive);
  316. unsigned long intsts_port = hwif->dma_base + 0x014;
  317. u32 reg;
  318. int dma_stat, data_loss = 0;
  319. static int retry = 0;
  320. /* errata A308 workaround: Step5 (check data loss) */
  321. /* We don't check non ide_disk because it is limited to UDMA4 */
  322. if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
  323. drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
  324. reg = in_be32((void __iomem *)intsts_port);
  325. if (!(reg & INTSTS_ACTEINT)) {
  326. printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
  327. drive->name);
  328. data_loss = 1;
  329. if (retry++) {
  330. struct request *rq = HWGROUP(drive)->rq;
  331. int unit;
  332. /* ERROR_RESET and drive->crc_count are needed
  333. * to reduce DMA transfer mode in retry process.
  334. */
  335. if (rq)
  336. rq->errors |= ERROR_RESET;
  337. for (unit = 0; unit < MAX_DRIVES; unit++) {
  338. ide_drive_t *drive = &hwif->drives[unit];
  339. drive->crc_count++;
  340. }
  341. }
  342. }
  343. }
  344. while (1) {
  345. reg = in_be32((void __iomem *)intsts_port);
  346. if (reg & INTSTS_SERROR) {
  347. printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
  348. out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
  349. out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
  350. continue;
  351. }
  352. if (reg & INTSTS_PRERR) {
  353. u32 maea0, maec0;
  354. unsigned long ctl_base = hwif->config_data;
  355. maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
  356. maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
  357. printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
  358. out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
  359. out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
  360. continue;
  361. }
  362. if (reg & INTSTS_RERR) {
  363. printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
  364. out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
  365. out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
  366. continue;
  367. }
  368. if (reg & INTSTS_ICERR) {
  369. out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
  370. printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
  371. out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
  372. continue;
  373. }
  374. if (reg & INTSTS_BMSINT) {
  375. printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
  376. out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
  377. ide_do_reset(drive);
  378. continue;
  379. }
  380. if (reg & INTSTS_BMHE) {
  381. out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
  382. continue;
  383. }
  384. if (reg & INTSTS_ACTEINT) {
  385. out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
  386. continue;
  387. }
  388. if (reg & INTSTS_IOIRQS) {
  389. out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
  390. continue;
  391. }
  392. break;
  393. }
  394. dma_stat = __ide_dma_end(drive);
  395. if (data_loss)
  396. dma_stat |= 2; /* emulate DMA error (to retry command) */
  397. return dma_stat;
  398. }
  399. /* returns 1 if dma irq issued, 0 otherwise */
  400. static int scc_dma_test_irq(ide_drive_t *drive)
  401. {
  402. ide_hwif_t *hwif = HWIF(drive);
  403. u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
  404. /* SCC errata A252,A308 workaround: Step4 */
  405. if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
  406. (int_stat & INTSTS_INTRQ))
  407. return 1;
  408. /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
  409. if (int_stat & INTSTS_IOIRQS)
  410. return 1;
  411. if (!drive->waiting_for_dma)
  412. printk(KERN_WARNING "%s: (%s) called while not waiting\n",
  413. drive->name, __FUNCTION__);
  414. return 0;
  415. }
  416. static u8 scc_udma_filter(ide_drive_t *drive)
  417. {
  418. ide_hwif_t *hwif = drive->hwif;
  419. u8 mask = hwif->ultra_mask;
  420. /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
  421. if ((drive->media != ide_disk) && (mask & 0xE0)) {
  422. printk(KERN_INFO "%s: limit %s to UDMA4\n",
  423. SCC_PATA_NAME, drive->name);
  424. mask = 0x1F;
  425. }
  426. return mask;
  427. }
  428. /**
  429. * setup_mmio_scc - map CTRL/BMID region
  430. * @dev: PCI device we are configuring
  431. * @name: device name
  432. *
  433. */
  434. static int setup_mmio_scc (struct pci_dev *dev, const char *name)
  435. {
  436. unsigned long ctl_base = pci_resource_start(dev, 0);
  437. unsigned long dma_base = pci_resource_start(dev, 1);
  438. unsigned long ctl_size = pci_resource_len(dev, 0);
  439. unsigned long dma_size = pci_resource_len(dev, 1);
  440. void __iomem *ctl_addr;
  441. void __iomem *dma_addr;
  442. int i;
  443. for (i = 0; i < MAX_HWIFS; i++) {
  444. if (scc_ports[i].ctl == 0)
  445. break;
  446. }
  447. if (i >= MAX_HWIFS)
  448. return -ENOMEM;
  449. if (!request_mem_region(ctl_base, ctl_size, name)) {
  450. printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
  451. goto fail_0;
  452. }
  453. if (!request_mem_region(dma_base, dma_size, name)) {
  454. printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
  455. goto fail_1;
  456. }
  457. if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
  458. goto fail_2;
  459. if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
  460. goto fail_3;
  461. pci_set_master(dev);
  462. scc_ports[i].ctl = (unsigned long)ctl_addr;
  463. scc_ports[i].dma = (unsigned long)dma_addr;
  464. pci_set_drvdata(dev, (void *) &scc_ports[i]);
  465. return 1;
  466. fail_3:
  467. iounmap(ctl_addr);
  468. fail_2:
  469. release_mem_region(dma_base, dma_size);
  470. fail_1:
  471. release_mem_region(ctl_base, ctl_size);
  472. fail_0:
  473. return -ENOMEM;
  474. }
  475. /**
  476. * init_setup_scc - set up an SCC PATA Controller
  477. * @dev: PCI device
  478. * @d: IDE PCI device
  479. *
  480. * Perform the initial set up for this device.
  481. */
  482. static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d)
  483. {
  484. unsigned long ctl_base;
  485. unsigned long dma_base;
  486. unsigned long cckctrl_port;
  487. unsigned long intmask_port;
  488. unsigned long mode_port;
  489. unsigned long ecmode_port;
  490. unsigned long dma_status_port;
  491. u32 reg = 0;
  492. struct scc_ports *ports;
  493. int rc;
  494. rc = setup_mmio_scc(dev, d->name);
  495. if (rc < 0) {
  496. return rc;
  497. }
  498. ports = pci_get_drvdata(dev);
  499. ctl_base = ports->ctl;
  500. dma_base = ports->dma;
  501. cckctrl_port = ctl_base + 0xff0;
  502. intmask_port = dma_base + 0x010;
  503. mode_port = ctl_base + 0x024;
  504. ecmode_port = ctl_base + 0xf00;
  505. dma_status_port = dma_base + 0x004;
  506. /* controller initialization */
  507. reg = 0;
  508. out_be32((void*)cckctrl_port, reg);
  509. reg |= CCKCTRL_ATACLKOEN;
  510. out_be32((void*)cckctrl_port, reg);
  511. reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
  512. out_be32((void*)cckctrl_port, reg);
  513. reg |= CCKCTRL_CRST;
  514. out_be32((void*)cckctrl_port, reg);
  515. for (;;) {
  516. reg = in_be32((void*)cckctrl_port);
  517. if (reg & CCKCTRL_CRST)
  518. break;
  519. udelay(5000);
  520. }
  521. reg |= CCKCTRL_ATARESET;
  522. out_be32((void*)cckctrl_port, reg);
  523. out_be32((void*)ecmode_port, ECMODE_VALUE);
  524. out_be32((void*)mode_port, MODE_JCUSFEN);
  525. out_be32((void*)intmask_port, INTMASK_MSK);
  526. return ide_setup_pci_device(dev, d);
  527. }
  528. /**
  529. * init_mmio_iops_scc - set up the iops for MMIO
  530. * @hwif: interface to set up
  531. *
  532. */
  533. static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
  534. {
  535. struct pci_dev *dev = hwif->pci_dev;
  536. struct scc_ports *ports = pci_get_drvdata(dev);
  537. unsigned long dma_base = ports->dma;
  538. ide_set_hwifdata(hwif, ports);
  539. hwif->INB = scc_ide_inb;
  540. hwif->INW = scc_ide_inw;
  541. hwif->INSW = scc_ide_insw;
  542. hwif->INSL = scc_ide_insl;
  543. hwif->OUTB = scc_ide_outb;
  544. hwif->OUTBSYNC = scc_ide_outbsync;
  545. hwif->OUTW = scc_ide_outw;
  546. hwif->OUTSW = scc_ide_outsw;
  547. hwif->OUTSL = scc_ide_outsl;
  548. hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
  549. hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
  550. hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
  551. hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
  552. hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
  553. hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
  554. hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
  555. hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
  556. hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
  557. hwif->irq = hwif->pci_dev->irq;
  558. hwif->dma_base = dma_base;
  559. hwif->config_data = ports->ctl;
  560. hwif->mmio = 1;
  561. }
  562. /**
  563. * init_iops_scc - set up iops
  564. * @hwif: interface to set up
  565. *
  566. * Do the basic setup for the SCC hardware interface
  567. * and then do the MMIO setup.
  568. */
  569. static void __devinit init_iops_scc(ide_hwif_t *hwif)
  570. {
  571. struct pci_dev *dev = hwif->pci_dev;
  572. hwif->hwif_data = NULL;
  573. if (pci_get_drvdata(dev) == NULL)
  574. return;
  575. init_mmio_iops_scc(hwif);
  576. }
  577. /**
  578. * init_hwif_scc - set up hwif
  579. * @hwif: interface to set up
  580. *
  581. * We do the basic set up of the interface structure. The SCC
  582. * requires several custom handlers so we override the default
  583. * ide DMA handlers appropriately.
  584. */
  585. static void __devinit init_hwif_scc(ide_hwif_t *hwif)
  586. {
  587. struct scc_ports *ports = ide_get_hwifdata(hwif);
  588. ports->hwif_id = hwif->index;
  589. hwif->dma_command = hwif->dma_base;
  590. hwif->dma_status = hwif->dma_base + 0x04;
  591. hwif->dma_prdtable = hwif->dma_base + 0x08;
  592. /* PTERADD */
  593. out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
  594. hwif->dma_setup = scc_dma_setup;
  595. hwif->ide_dma_end = scc_ide_dma_end;
  596. hwif->speedproc = scc_tune_chipset;
  597. hwif->set_pio_mode = scc_set_pio_mode;
  598. hwif->ide_dma_check = scc_config_drive_for_dma;
  599. hwif->ide_dma_test_irq = scc_dma_test_irq;
  600. hwif->udma_filter = scc_udma_filter;
  601. hwif->drives[0].autotune = IDE_TUNE_AUTO;
  602. hwif->drives[1].autotune = IDE_TUNE_AUTO;
  603. if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
  604. hwif->ultra_mask = 0x7f; /* 133MHz */
  605. } else {
  606. hwif->ultra_mask = 0x3f; /* 100MHz */
  607. }
  608. hwif->mwdma_mask = 0x00;
  609. hwif->swdma_mask = 0x00;
  610. hwif->atapi_dma = 1;
  611. /* we support 80c cable only. */
  612. hwif->cbl = ATA_CBL_PATA80;
  613. hwif->autodma = 0;
  614. if (!noautodma)
  615. hwif->autodma = 1;
  616. hwif->drives[0].autodma = hwif->autodma;
  617. hwif->drives[1].autodma = hwif->autodma;
  618. }
  619. #define DECLARE_SCC_DEV(name_str) \
  620. { \
  621. .name = name_str, \
  622. .init_setup = init_setup_scc, \
  623. .init_iops = init_iops_scc, \
  624. .init_hwif = init_hwif_scc, \
  625. .autodma = AUTODMA, \
  626. .bootable = ON_BOARD, \
  627. .host_flags = IDE_HFLAG_SINGLE, \
  628. .pio_mask = ATA_PIO4, \
  629. }
  630. static ide_pci_device_t scc_chipsets[] __devinitdata = {
  631. /* 0 */ DECLARE_SCC_DEV("sccIDE"),
  632. };
  633. /**
  634. * scc_init_one - pci layer discovery entry
  635. * @dev: PCI device
  636. * @id: ident table entry
  637. *
  638. * Called by the PCI code when it finds an SCC PATA controller.
  639. * We then use the IDE PCI generic helper to do most of the work.
  640. */
  641. static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  642. {
  643. ide_pci_device_t *d = &scc_chipsets[id->driver_data];
  644. return d->init_setup(dev, d);
  645. }
  646. /**
  647. * scc_remove - pci layer remove entry
  648. * @dev: PCI device
  649. *
  650. * Called by the PCI code when it removes an SCC PATA controller.
  651. */
  652. static void __devexit scc_remove(struct pci_dev *dev)
  653. {
  654. struct scc_ports *ports = pci_get_drvdata(dev);
  655. ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
  656. unsigned long ctl_base = pci_resource_start(dev, 0);
  657. unsigned long dma_base = pci_resource_start(dev, 1);
  658. unsigned long ctl_size = pci_resource_len(dev, 0);
  659. unsigned long dma_size = pci_resource_len(dev, 1);
  660. if (hwif->dmatable_cpu) {
  661. pci_free_consistent(hwif->pci_dev,
  662. PRD_ENTRIES * PRD_BYTES,
  663. hwif->dmatable_cpu,
  664. hwif->dmatable_dma);
  665. hwif->dmatable_cpu = NULL;
  666. }
  667. ide_unregister(hwif->index);
  668. hwif->chipset = ide_unknown;
  669. iounmap((void*)ports->dma);
  670. iounmap((void*)ports->ctl);
  671. release_mem_region(dma_base, dma_size);
  672. release_mem_region(ctl_base, ctl_size);
  673. memset(ports, 0, sizeof(*ports));
  674. }
  675. static struct pci_device_id scc_pci_tbl[] = {
  676. { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  677. { 0, },
  678. };
  679. MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
  680. static struct pci_driver driver = {
  681. .name = "SCC IDE",
  682. .id_table = scc_pci_tbl,
  683. .probe = scc_init_one,
  684. .remove = scc_remove,
  685. };
  686. static int scc_ide_init(void)
  687. {
  688. return ide_pci_register_driver(&driver);
  689. }
  690. module_init(scc_ide_init);
  691. /* -- No exit code?
  692. static void scc_ide_exit(void)
  693. {
  694. ide_pci_unregister_driver(&driver);
  695. }
  696. module_exit(scc_ide_exit);
  697. */
  698. MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
  699. MODULE_LICENSE("GPL");