clock34xx.h 85 KB

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  1. /*
  2. * OMAP3 clock framework
  3. *
  4. * Copyright (C) 2007-2008 Texas Instruments, Inc.
  5. * Copyright (C) 2007-2008 Nokia Corporation
  6. *
  7. * Written by Paul Walmsley
  8. * With many device clock fixes by Kevin Hilman and Jouni Högander
  9. * DPLL bypass clock support added by Roman Tereshonkov
  10. *
  11. */
  12. /*
  13. * Virtual clocks are introduced as convenient tools.
  14. * They are sources for other clocks and not supposed
  15. * to be requested from drivers directly.
  16. */
  17. #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  18. #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  19. #include <mach/control.h>
  20. #include "clock.h"
  21. #include "cm.h"
  22. #include "cm-regbits-34xx.h"
  23. #include "prm.h"
  24. #include "prm-regbits-34xx.h"
  25. #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
  26. static unsigned long omap3_dpll_recalc(struct clk *clk);
  27. static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
  28. static void omap3_dpll_allow_idle(struct clk *clk);
  29. static void omap3_dpll_deny_idle(struct clk *clk);
  30. static u32 omap3_dpll_autoidle_read(struct clk *clk);
  31. static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
  32. static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
  33. static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
  34. /* Maximum DPLL multiplier, divider values for OMAP3 */
  35. #define OMAP3_MAX_DPLL_MULT 2048
  36. #define OMAP3_MAX_DPLL_DIV 128
  37. /*
  38. * DPLL1 supplies clock to the MPU.
  39. * DPLL2 supplies clock to the IVA2.
  40. * DPLL3 supplies CORE domain clocks.
  41. * DPLL4 supplies peripheral clocks.
  42. * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  43. */
  44. /* Forward declarations for DPLL bypass clocks */
  45. static struct clk dpll1_fck;
  46. static struct clk dpll2_fck;
  47. /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
  48. #define DPLL_LOW_POWER_STOP 0x1
  49. #define DPLL_LOW_POWER_BYPASS 0x5
  50. #define DPLL_LOCKED 0x7
  51. /* PRM CLOCKS */
  52. /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  53. static struct clk omap_32k_fck = {
  54. .name = "omap_32k_fck",
  55. .ops = &clkops_null,
  56. .rate = 32768,
  57. .flags = RATE_FIXED,
  58. };
  59. static struct clk secure_32k_fck = {
  60. .name = "secure_32k_fck",
  61. .ops = &clkops_null,
  62. .rate = 32768,
  63. .flags = RATE_FIXED,
  64. };
  65. /* Virtual source clocks for osc_sys_ck */
  66. static struct clk virt_12m_ck = {
  67. .name = "virt_12m_ck",
  68. .ops = &clkops_null,
  69. .rate = 12000000,
  70. .flags = RATE_FIXED,
  71. };
  72. static struct clk virt_13m_ck = {
  73. .name = "virt_13m_ck",
  74. .ops = &clkops_null,
  75. .rate = 13000000,
  76. .flags = RATE_FIXED,
  77. };
  78. static struct clk virt_16_8m_ck = {
  79. .name = "virt_16_8m_ck",
  80. .ops = &clkops_null,
  81. .rate = 16800000,
  82. .flags = RATE_FIXED,
  83. };
  84. static struct clk virt_19_2m_ck = {
  85. .name = "virt_19_2m_ck",
  86. .ops = &clkops_null,
  87. .rate = 19200000,
  88. .flags = RATE_FIXED,
  89. };
  90. static struct clk virt_26m_ck = {
  91. .name = "virt_26m_ck",
  92. .ops = &clkops_null,
  93. .rate = 26000000,
  94. .flags = RATE_FIXED,
  95. };
  96. static struct clk virt_38_4m_ck = {
  97. .name = "virt_38_4m_ck",
  98. .ops = &clkops_null,
  99. .rate = 38400000,
  100. .flags = RATE_FIXED,
  101. };
  102. static const struct clksel_rate osc_sys_12m_rates[] = {
  103. { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
  104. { .div = 0 }
  105. };
  106. static const struct clksel_rate osc_sys_13m_rates[] = {
  107. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  108. { .div = 0 }
  109. };
  110. static const struct clksel_rate osc_sys_16_8m_rates[] = {
  111. { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
  112. { .div = 0 }
  113. };
  114. static const struct clksel_rate osc_sys_19_2m_rates[] = {
  115. { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
  116. { .div = 0 }
  117. };
  118. static const struct clksel_rate osc_sys_26m_rates[] = {
  119. { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
  120. { .div = 0 }
  121. };
  122. static const struct clksel_rate osc_sys_38_4m_rates[] = {
  123. { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
  124. { .div = 0 }
  125. };
  126. static const struct clksel osc_sys_clksel[] = {
  127. { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
  128. { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
  129. { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
  130. { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
  131. { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
  132. { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
  133. { .parent = NULL },
  134. };
  135. /* Oscillator clock */
  136. /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
  137. static struct clk osc_sys_ck = {
  138. .name = "osc_sys_ck",
  139. .ops = &clkops_null,
  140. .init = &omap2_init_clksel_parent,
  141. .clksel_reg = OMAP3430_PRM_CLKSEL,
  142. .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
  143. .clksel = osc_sys_clksel,
  144. /* REVISIT: deal with autoextclkmode? */
  145. .flags = RATE_FIXED,
  146. .recalc = &omap2_clksel_recalc,
  147. };
  148. static const struct clksel_rate div2_rates[] = {
  149. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  150. { .div = 2, .val = 2, .flags = RATE_IN_343X },
  151. { .div = 0 }
  152. };
  153. static const struct clksel sys_clksel[] = {
  154. { .parent = &osc_sys_ck, .rates = div2_rates },
  155. { .parent = NULL }
  156. };
  157. /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
  158. /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
  159. static struct clk sys_ck = {
  160. .name = "sys_ck",
  161. .ops = &clkops_null,
  162. .parent = &osc_sys_ck,
  163. .init = &omap2_init_clksel_parent,
  164. .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
  165. .clksel_mask = OMAP_SYSCLKDIV_MASK,
  166. .clksel = sys_clksel,
  167. .recalc = &omap2_clksel_recalc,
  168. };
  169. static struct clk sys_altclk = {
  170. .name = "sys_altclk",
  171. .ops = &clkops_null,
  172. };
  173. /* Optional external clock input for some McBSPs */
  174. static struct clk mcbsp_clks = {
  175. .name = "mcbsp_clks",
  176. .ops = &clkops_null,
  177. };
  178. /* PRM EXTERNAL CLOCK OUTPUT */
  179. static struct clk sys_clkout1 = {
  180. .name = "sys_clkout1",
  181. .ops = &clkops_omap2_dflt,
  182. .parent = &osc_sys_ck,
  183. .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
  184. .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
  185. .recalc = &followparent_recalc,
  186. };
  187. /* DPLLS */
  188. /* CM CLOCKS */
  189. static const struct clksel_rate div16_dpll_rates[] = {
  190. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  191. { .div = 2, .val = 2, .flags = RATE_IN_343X },
  192. { .div = 3, .val = 3, .flags = RATE_IN_343X },
  193. { .div = 4, .val = 4, .flags = RATE_IN_343X },
  194. { .div = 5, .val = 5, .flags = RATE_IN_343X },
  195. { .div = 6, .val = 6, .flags = RATE_IN_343X },
  196. { .div = 7, .val = 7, .flags = RATE_IN_343X },
  197. { .div = 8, .val = 8, .flags = RATE_IN_343X },
  198. { .div = 9, .val = 9, .flags = RATE_IN_343X },
  199. { .div = 10, .val = 10, .flags = RATE_IN_343X },
  200. { .div = 11, .val = 11, .flags = RATE_IN_343X },
  201. { .div = 12, .val = 12, .flags = RATE_IN_343X },
  202. { .div = 13, .val = 13, .flags = RATE_IN_343X },
  203. { .div = 14, .val = 14, .flags = RATE_IN_343X },
  204. { .div = 15, .val = 15, .flags = RATE_IN_343X },
  205. { .div = 16, .val = 16, .flags = RATE_IN_343X },
  206. { .div = 0 }
  207. };
  208. /* DPLL1 */
  209. /* MPU clock source */
  210. /* Type: DPLL */
  211. static struct dpll_data dpll1_dd = {
  212. .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
  213. .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
  214. .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
  215. .clk_bypass = &dpll1_fck,
  216. .clk_ref = &sys_ck,
  217. .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
  218. .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
  219. .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
  220. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  221. .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
  222. .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
  223. .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
  224. .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
  225. .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
  226. .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
  227. .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
  228. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  229. .min_divider = 1,
  230. .max_divider = OMAP3_MAX_DPLL_DIV,
  231. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  232. };
  233. static struct clk dpll1_ck = {
  234. .name = "dpll1_ck",
  235. .ops = &clkops_null,
  236. .parent = &sys_ck,
  237. .dpll_data = &dpll1_dd,
  238. .round_rate = &omap2_dpll_round_rate,
  239. .set_rate = &omap3_noncore_dpll_set_rate,
  240. .clkdm_name = "dpll1_clkdm",
  241. .recalc = &omap3_dpll_recalc,
  242. };
  243. /*
  244. * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  245. * DPLL isn't bypassed.
  246. */
  247. static struct clk dpll1_x2_ck = {
  248. .name = "dpll1_x2_ck",
  249. .ops = &clkops_null,
  250. .parent = &dpll1_ck,
  251. .clkdm_name = "dpll1_clkdm",
  252. .recalc = &omap3_clkoutx2_recalc,
  253. };
  254. /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
  255. static const struct clksel div16_dpll1_x2m2_clksel[] = {
  256. { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
  257. { .parent = NULL }
  258. };
  259. /*
  260. * Does not exist in the TRM - needed to separate the M2 divider from
  261. * bypass selection in mpu_ck
  262. */
  263. static struct clk dpll1_x2m2_ck = {
  264. .name = "dpll1_x2m2_ck",
  265. .ops = &clkops_null,
  266. .parent = &dpll1_x2_ck,
  267. .init = &omap2_init_clksel_parent,
  268. .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
  269. .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
  270. .clksel = div16_dpll1_x2m2_clksel,
  271. .clkdm_name = "dpll1_clkdm",
  272. .recalc = &omap2_clksel_recalc,
  273. };
  274. /* DPLL2 */
  275. /* IVA2 clock source */
  276. /* Type: DPLL */
  277. static struct dpll_data dpll2_dd = {
  278. .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
  279. .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
  280. .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
  281. .clk_bypass = &dpll2_fck,
  282. .clk_ref = &sys_ck,
  283. .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
  284. .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
  285. .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
  286. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
  287. (1 << DPLL_LOW_POWER_BYPASS),
  288. .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
  289. .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
  290. .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
  291. .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
  292. .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
  293. .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
  294. .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
  295. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  296. .min_divider = 1,
  297. .max_divider = OMAP3_MAX_DPLL_DIV,
  298. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  299. };
  300. static struct clk dpll2_ck = {
  301. .name = "dpll2_ck",
  302. .ops = &clkops_noncore_dpll_ops,
  303. .parent = &sys_ck,
  304. .dpll_data = &dpll2_dd,
  305. .round_rate = &omap2_dpll_round_rate,
  306. .set_rate = &omap3_noncore_dpll_set_rate,
  307. .clkdm_name = "dpll2_clkdm",
  308. .recalc = &omap3_dpll_recalc,
  309. };
  310. static const struct clksel div16_dpll2_m2x2_clksel[] = {
  311. { .parent = &dpll2_ck, .rates = div16_dpll_rates },
  312. { .parent = NULL }
  313. };
  314. /*
  315. * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
  316. * or CLKOUTX2. CLKOUT seems most plausible.
  317. */
  318. static struct clk dpll2_m2_ck = {
  319. .name = "dpll2_m2_ck",
  320. .ops = &clkops_null,
  321. .parent = &dpll2_ck,
  322. .init = &omap2_init_clksel_parent,
  323. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
  324. OMAP3430_CM_CLKSEL2_PLL),
  325. .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
  326. .clksel = div16_dpll2_m2x2_clksel,
  327. .clkdm_name = "dpll2_clkdm",
  328. .recalc = &omap2_clksel_recalc,
  329. };
  330. /*
  331. * DPLL3
  332. * Source clock for all interfaces and for some device fclks
  333. * REVISIT: Also supports fast relock bypass - not included below
  334. */
  335. static struct dpll_data dpll3_dd = {
  336. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  337. .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
  338. .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
  339. .clk_bypass = &sys_ck,
  340. .clk_ref = &sys_ck,
  341. .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
  342. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  343. .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
  344. .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
  345. .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
  346. .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
  347. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  348. .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
  349. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  350. .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
  351. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  352. .min_divider = 1,
  353. .max_divider = OMAP3_MAX_DPLL_DIV,
  354. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  355. };
  356. static struct clk dpll3_ck = {
  357. .name = "dpll3_ck",
  358. .ops = &clkops_null,
  359. .parent = &sys_ck,
  360. .dpll_data = &dpll3_dd,
  361. .round_rate = &omap2_dpll_round_rate,
  362. .clkdm_name = "dpll3_clkdm",
  363. .recalc = &omap3_dpll_recalc,
  364. };
  365. /*
  366. * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  367. * DPLL isn't bypassed
  368. */
  369. static struct clk dpll3_x2_ck = {
  370. .name = "dpll3_x2_ck",
  371. .ops = &clkops_null,
  372. .parent = &dpll3_ck,
  373. .clkdm_name = "dpll3_clkdm",
  374. .recalc = &omap3_clkoutx2_recalc,
  375. };
  376. static const struct clksel_rate div31_dpll3_rates[] = {
  377. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  378. { .div = 2, .val = 2, .flags = RATE_IN_343X },
  379. { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
  380. { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
  381. { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
  382. { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
  383. { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
  384. { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
  385. { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
  386. { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
  387. { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
  388. { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
  389. { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
  390. { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
  391. { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
  392. { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
  393. { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
  394. { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
  395. { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
  396. { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
  397. { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
  398. { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
  399. { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
  400. { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
  401. { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
  402. { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
  403. { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
  404. { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
  405. { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
  406. { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
  407. { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
  408. { .div = 0 },
  409. };
  410. static const struct clksel div31_dpll3m2_clksel[] = {
  411. { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
  412. { .parent = NULL }
  413. };
  414. /* DPLL3 output M2 - primary control point for CORE speed */
  415. static struct clk dpll3_m2_ck = {
  416. .name = "dpll3_m2_ck",
  417. .ops = &clkops_null,
  418. .parent = &dpll3_ck,
  419. .init = &omap2_init_clksel_parent,
  420. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  421. .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
  422. .clksel = div31_dpll3m2_clksel,
  423. .clkdm_name = "dpll3_clkdm",
  424. .round_rate = &omap2_clksel_round_rate,
  425. .set_rate = &omap3_core_dpll_m2_set_rate,
  426. .recalc = &omap2_clksel_recalc,
  427. };
  428. static struct clk core_ck = {
  429. .name = "core_ck",
  430. .ops = &clkops_null,
  431. .parent = &dpll3_m2_ck,
  432. .recalc = &followparent_recalc,
  433. };
  434. static struct clk dpll3_m2x2_ck = {
  435. .name = "dpll3_m2x2_ck",
  436. .ops = &clkops_null,
  437. .parent = &dpll3_x2_ck,
  438. .clkdm_name = "dpll3_clkdm",
  439. .recalc = &followparent_recalc,
  440. };
  441. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  442. static const struct clksel div16_dpll3_clksel[] = {
  443. { .parent = &dpll3_ck, .rates = div16_dpll_rates },
  444. { .parent = NULL }
  445. };
  446. /* This virtual clock is the source for dpll3_m3x2_ck */
  447. static struct clk dpll3_m3_ck = {
  448. .name = "dpll3_m3_ck",
  449. .ops = &clkops_null,
  450. .parent = &dpll3_ck,
  451. .init = &omap2_init_clksel_parent,
  452. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  453. .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
  454. .clksel = div16_dpll3_clksel,
  455. .clkdm_name = "dpll3_clkdm",
  456. .recalc = &omap2_clksel_recalc,
  457. };
  458. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  459. static struct clk dpll3_m3x2_ck = {
  460. .name = "dpll3_m3x2_ck",
  461. .ops = &clkops_omap2_dflt_wait,
  462. .parent = &dpll3_m3_ck,
  463. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  464. .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
  465. .flags = INVERT_ENABLE,
  466. .clkdm_name = "dpll3_clkdm",
  467. .recalc = &omap3_clkoutx2_recalc,
  468. };
  469. static struct clk emu_core_alwon_ck = {
  470. .name = "emu_core_alwon_ck",
  471. .ops = &clkops_null,
  472. .parent = &dpll3_m3x2_ck,
  473. .clkdm_name = "dpll3_clkdm",
  474. .recalc = &followparent_recalc,
  475. };
  476. /* DPLL4 */
  477. /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
  478. /* Type: DPLL */
  479. static struct dpll_data dpll4_dd = {
  480. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
  481. .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
  482. .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
  483. .clk_bypass = &sys_ck,
  484. .clk_ref = &sys_ck,
  485. .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
  486. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  487. .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
  488. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  489. .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
  490. .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
  491. .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
  492. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  493. .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
  494. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  495. .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
  496. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  497. .min_divider = 1,
  498. .max_divider = OMAP3_MAX_DPLL_DIV,
  499. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  500. };
  501. static struct clk dpll4_ck = {
  502. .name = "dpll4_ck",
  503. .ops = &clkops_noncore_dpll_ops,
  504. .parent = &sys_ck,
  505. .dpll_data = &dpll4_dd,
  506. .round_rate = &omap2_dpll_round_rate,
  507. .set_rate = &omap3_dpll4_set_rate,
  508. .clkdm_name = "dpll4_clkdm",
  509. .recalc = &omap3_dpll_recalc,
  510. };
  511. /*
  512. * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  513. * DPLL isn't bypassed --
  514. * XXX does this serve any downstream clocks?
  515. */
  516. static struct clk dpll4_x2_ck = {
  517. .name = "dpll4_x2_ck",
  518. .ops = &clkops_null,
  519. .parent = &dpll4_ck,
  520. .clkdm_name = "dpll4_clkdm",
  521. .recalc = &omap3_clkoutx2_recalc,
  522. };
  523. static const struct clksel div16_dpll4_clksel[] = {
  524. { .parent = &dpll4_ck, .rates = div16_dpll_rates },
  525. { .parent = NULL }
  526. };
  527. /* This virtual clock is the source for dpll4_m2x2_ck */
  528. static struct clk dpll4_m2_ck = {
  529. .name = "dpll4_m2_ck",
  530. .ops = &clkops_null,
  531. .parent = &dpll4_ck,
  532. .init = &omap2_init_clksel_parent,
  533. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
  534. .clksel_mask = OMAP3430_DIV_96M_MASK,
  535. .clksel = div16_dpll4_clksel,
  536. .clkdm_name = "dpll4_clkdm",
  537. .recalc = &omap2_clksel_recalc,
  538. };
  539. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  540. static struct clk dpll4_m2x2_ck = {
  541. .name = "dpll4_m2x2_ck",
  542. .ops = &clkops_omap2_dflt_wait,
  543. .parent = &dpll4_m2_ck,
  544. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  545. .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
  546. .flags = INVERT_ENABLE,
  547. .clkdm_name = "dpll4_clkdm",
  548. .recalc = &omap3_clkoutx2_recalc,
  549. };
  550. /*
  551. * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
  552. * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
  553. * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
  554. * CM_96K_(F)CLK.
  555. */
  556. static struct clk omap_96m_alwon_fck = {
  557. .name = "omap_96m_alwon_fck",
  558. .ops = &clkops_null,
  559. .parent = &dpll4_m2x2_ck,
  560. .recalc = &followparent_recalc,
  561. };
  562. static struct clk cm_96m_fck = {
  563. .name = "cm_96m_fck",
  564. .ops = &clkops_null,
  565. .parent = &omap_96m_alwon_fck,
  566. .recalc = &followparent_recalc,
  567. };
  568. static const struct clksel_rate omap_96m_dpll_rates[] = {
  569. { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
  570. { .div = 0 }
  571. };
  572. static const struct clksel_rate omap_96m_sys_rates[] = {
  573. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  574. { .div = 0 }
  575. };
  576. static const struct clksel omap_96m_fck_clksel[] = {
  577. { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
  578. { .parent = &sys_ck, .rates = omap_96m_sys_rates },
  579. { .parent = NULL }
  580. };
  581. static struct clk omap_96m_fck = {
  582. .name = "omap_96m_fck",
  583. .ops = &clkops_null,
  584. .parent = &sys_ck,
  585. .init = &omap2_init_clksel_parent,
  586. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  587. .clksel_mask = OMAP3430_SOURCE_96M_MASK,
  588. .clksel = omap_96m_fck_clksel,
  589. .recalc = &omap2_clksel_recalc,
  590. };
  591. /* This virtual clock is the source for dpll4_m3x2_ck */
  592. static struct clk dpll4_m3_ck = {
  593. .name = "dpll4_m3_ck",
  594. .ops = &clkops_null,
  595. .parent = &dpll4_ck,
  596. .init = &omap2_init_clksel_parent,
  597. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
  598. .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
  599. .clksel = div16_dpll4_clksel,
  600. .clkdm_name = "dpll4_clkdm",
  601. .recalc = &omap2_clksel_recalc,
  602. };
  603. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  604. static struct clk dpll4_m3x2_ck = {
  605. .name = "dpll4_m3x2_ck",
  606. .ops = &clkops_omap2_dflt_wait,
  607. .parent = &dpll4_m3_ck,
  608. .init = &omap2_init_clksel_parent,
  609. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  610. .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
  611. .flags = INVERT_ENABLE,
  612. .clkdm_name = "dpll4_clkdm",
  613. .recalc = &omap3_clkoutx2_recalc,
  614. };
  615. static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
  616. { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
  617. { .div = 0 }
  618. };
  619. static const struct clksel_rate omap_54m_alt_rates[] = {
  620. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  621. { .div = 0 }
  622. };
  623. static const struct clksel omap_54m_clksel[] = {
  624. { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
  625. { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
  626. { .parent = NULL }
  627. };
  628. static struct clk omap_54m_fck = {
  629. .name = "omap_54m_fck",
  630. .ops = &clkops_null,
  631. .init = &omap2_init_clksel_parent,
  632. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  633. .clksel_mask = OMAP3430_SOURCE_54M_MASK,
  634. .clksel = omap_54m_clksel,
  635. .recalc = &omap2_clksel_recalc,
  636. };
  637. static const struct clksel_rate omap_48m_cm96m_rates[] = {
  638. { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
  639. { .div = 0 }
  640. };
  641. static const struct clksel_rate omap_48m_alt_rates[] = {
  642. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  643. { .div = 0 }
  644. };
  645. static const struct clksel omap_48m_clksel[] = {
  646. { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
  647. { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
  648. { .parent = NULL }
  649. };
  650. static struct clk omap_48m_fck = {
  651. .name = "omap_48m_fck",
  652. .ops = &clkops_null,
  653. .init = &omap2_init_clksel_parent,
  654. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  655. .clksel_mask = OMAP3430_SOURCE_48M_MASK,
  656. .clksel = omap_48m_clksel,
  657. .recalc = &omap2_clksel_recalc,
  658. };
  659. static struct clk omap_12m_fck = {
  660. .name = "omap_12m_fck",
  661. .ops = &clkops_null,
  662. .parent = &omap_48m_fck,
  663. .fixed_div = 4,
  664. .recalc = &omap2_fixed_divisor_recalc,
  665. };
  666. /* This virstual clock is the source for dpll4_m4x2_ck */
  667. static struct clk dpll4_m4_ck = {
  668. .name = "dpll4_m4_ck",
  669. .ops = &clkops_null,
  670. .parent = &dpll4_ck,
  671. .init = &omap2_init_clksel_parent,
  672. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
  673. .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
  674. .clksel = div16_dpll4_clksel,
  675. .clkdm_name = "dpll4_clkdm",
  676. .recalc = &omap2_clksel_recalc,
  677. .set_rate = &omap2_clksel_set_rate,
  678. .round_rate = &omap2_clksel_round_rate,
  679. };
  680. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  681. static struct clk dpll4_m4x2_ck = {
  682. .name = "dpll4_m4x2_ck",
  683. .ops = &clkops_omap2_dflt_wait,
  684. .parent = &dpll4_m4_ck,
  685. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  686. .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
  687. .flags = INVERT_ENABLE,
  688. .clkdm_name = "dpll4_clkdm",
  689. .recalc = &omap3_clkoutx2_recalc,
  690. };
  691. /* This virtual clock is the source for dpll4_m5x2_ck */
  692. static struct clk dpll4_m5_ck = {
  693. .name = "dpll4_m5_ck",
  694. .ops = &clkops_null,
  695. .parent = &dpll4_ck,
  696. .init = &omap2_init_clksel_parent,
  697. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
  698. .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
  699. .clksel = div16_dpll4_clksel,
  700. .clkdm_name = "dpll4_clkdm",
  701. .recalc = &omap2_clksel_recalc,
  702. };
  703. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  704. static struct clk dpll4_m5x2_ck = {
  705. .name = "dpll4_m5x2_ck",
  706. .ops = &clkops_omap2_dflt_wait,
  707. .parent = &dpll4_m5_ck,
  708. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  709. .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
  710. .flags = INVERT_ENABLE,
  711. .clkdm_name = "dpll4_clkdm",
  712. .recalc = &omap3_clkoutx2_recalc,
  713. };
  714. /* This virtual clock is the source for dpll4_m6x2_ck */
  715. static struct clk dpll4_m6_ck = {
  716. .name = "dpll4_m6_ck",
  717. .ops = &clkops_null,
  718. .parent = &dpll4_ck,
  719. .init = &omap2_init_clksel_parent,
  720. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  721. .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
  722. .clksel = div16_dpll4_clksel,
  723. .clkdm_name = "dpll4_clkdm",
  724. .recalc = &omap2_clksel_recalc,
  725. };
  726. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  727. static struct clk dpll4_m6x2_ck = {
  728. .name = "dpll4_m6x2_ck",
  729. .ops = &clkops_omap2_dflt_wait,
  730. .parent = &dpll4_m6_ck,
  731. .init = &omap2_init_clksel_parent,
  732. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  733. .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
  734. .flags = INVERT_ENABLE,
  735. .clkdm_name = "dpll4_clkdm",
  736. .recalc = &omap3_clkoutx2_recalc,
  737. };
  738. static struct clk emu_per_alwon_ck = {
  739. .name = "emu_per_alwon_ck",
  740. .ops = &clkops_null,
  741. .parent = &dpll4_m6x2_ck,
  742. .clkdm_name = "dpll4_clkdm",
  743. .recalc = &followparent_recalc,
  744. };
  745. /* DPLL5 */
  746. /* Supplies 120MHz clock, USIM source clock */
  747. /* Type: DPLL */
  748. /* 3430ES2 only */
  749. static struct dpll_data dpll5_dd = {
  750. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
  751. .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
  752. .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
  753. .clk_bypass = &sys_ck,
  754. .clk_ref = &sys_ck,
  755. .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
  756. .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
  757. .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
  758. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  759. .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
  760. .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
  761. .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
  762. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
  763. .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
  764. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
  765. .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
  766. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  767. .min_divider = 1,
  768. .max_divider = OMAP3_MAX_DPLL_DIV,
  769. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  770. };
  771. static struct clk dpll5_ck = {
  772. .name = "dpll5_ck",
  773. .ops = &clkops_noncore_dpll_ops,
  774. .parent = &sys_ck,
  775. .dpll_data = &dpll5_dd,
  776. .round_rate = &omap2_dpll_round_rate,
  777. .set_rate = &omap3_noncore_dpll_set_rate,
  778. .clkdm_name = "dpll5_clkdm",
  779. .recalc = &omap3_dpll_recalc,
  780. };
  781. static const struct clksel div16_dpll5_clksel[] = {
  782. { .parent = &dpll5_ck, .rates = div16_dpll_rates },
  783. { .parent = NULL }
  784. };
  785. static struct clk dpll5_m2_ck = {
  786. .name = "dpll5_m2_ck",
  787. .ops = &clkops_null,
  788. .parent = &dpll5_ck,
  789. .init = &omap2_init_clksel_parent,
  790. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
  791. .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
  792. .clksel = div16_dpll5_clksel,
  793. .clkdm_name = "dpll5_clkdm",
  794. .recalc = &omap2_clksel_recalc,
  795. };
  796. /* CM EXTERNAL CLOCK OUTPUTS */
  797. static const struct clksel_rate clkout2_src_core_rates[] = {
  798. { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
  799. { .div = 0 }
  800. };
  801. static const struct clksel_rate clkout2_src_sys_rates[] = {
  802. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  803. { .div = 0 }
  804. };
  805. static const struct clksel_rate clkout2_src_96m_rates[] = {
  806. { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
  807. { .div = 0 }
  808. };
  809. static const struct clksel_rate clkout2_src_54m_rates[] = {
  810. { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
  811. { .div = 0 }
  812. };
  813. static const struct clksel clkout2_src_clksel[] = {
  814. { .parent = &core_ck, .rates = clkout2_src_core_rates },
  815. { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
  816. { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
  817. { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
  818. { .parent = NULL }
  819. };
  820. static struct clk clkout2_src_ck = {
  821. .name = "clkout2_src_ck",
  822. .ops = &clkops_omap2_dflt,
  823. .init = &omap2_init_clksel_parent,
  824. .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
  825. .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
  826. .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
  827. .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
  828. .clksel = clkout2_src_clksel,
  829. .clkdm_name = "core_clkdm",
  830. .recalc = &omap2_clksel_recalc,
  831. };
  832. static const struct clksel_rate sys_clkout2_rates[] = {
  833. { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
  834. { .div = 2, .val = 1, .flags = RATE_IN_343X },
  835. { .div = 4, .val = 2, .flags = RATE_IN_343X },
  836. { .div = 8, .val = 3, .flags = RATE_IN_343X },
  837. { .div = 16, .val = 4, .flags = RATE_IN_343X },
  838. { .div = 0 },
  839. };
  840. static const struct clksel sys_clkout2_clksel[] = {
  841. { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
  842. { .parent = NULL },
  843. };
  844. static struct clk sys_clkout2 = {
  845. .name = "sys_clkout2",
  846. .ops = &clkops_null,
  847. .init = &omap2_init_clksel_parent,
  848. .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
  849. .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
  850. .clksel = sys_clkout2_clksel,
  851. .recalc = &omap2_clksel_recalc,
  852. };
  853. /* CM OUTPUT CLOCKS */
  854. static struct clk corex2_fck = {
  855. .name = "corex2_fck",
  856. .ops = &clkops_null,
  857. .parent = &dpll3_m2x2_ck,
  858. .recalc = &followparent_recalc,
  859. };
  860. /* DPLL power domain clock controls */
  861. static const struct clksel_rate div4_rates[] = {
  862. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  863. { .div = 2, .val = 2, .flags = RATE_IN_343X },
  864. { .div = 4, .val = 4, .flags = RATE_IN_343X },
  865. { .div = 0 }
  866. };
  867. static const struct clksel div4_core_clksel[] = {
  868. { .parent = &core_ck, .rates = div4_rates },
  869. { .parent = NULL }
  870. };
  871. /*
  872. * REVISIT: Are these in DPLL power domain or CM power domain? docs
  873. * may be inconsistent here?
  874. */
  875. static struct clk dpll1_fck = {
  876. .name = "dpll1_fck",
  877. .ops = &clkops_null,
  878. .parent = &core_ck,
  879. .init = &omap2_init_clksel_parent,
  880. .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
  881. .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
  882. .clksel = div4_core_clksel,
  883. .recalc = &omap2_clksel_recalc,
  884. };
  885. static struct clk mpu_ck = {
  886. .name = "mpu_ck",
  887. .ops = &clkops_null,
  888. .parent = &dpll1_x2m2_ck,
  889. .clkdm_name = "mpu_clkdm",
  890. .recalc = &followparent_recalc,
  891. };
  892. /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
  893. static const struct clksel_rate arm_fck_rates[] = {
  894. { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
  895. { .div = 2, .val = 1, .flags = RATE_IN_343X },
  896. { .div = 0 },
  897. };
  898. static const struct clksel arm_fck_clksel[] = {
  899. { .parent = &mpu_ck, .rates = arm_fck_rates },
  900. { .parent = NULL }
  901. };
  902. static struct clk arm_fck = {
  903. .name = "arm_fck",
  904. .ops = &clkops_null,
  905. .parent = &mpu_ck,
  906. .init = &omap2_init_clksel_parent,
  907. .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
  908. .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
  909. .clksel = arm_fck_clksel,
  910. .clkdm_name = "mpu_clkdm",
  911. .recalc = &omap2_clksel_recalc,
  912. };
  913. /* XXX What about neon_clkdm ? */
  914. /*
  915. * REVISIT: This clock is never specifically defined in the 3430 TRM,
  916. * although it is referenced - so this is a guess
  917. */
  918. static struct clk emu_mpu_alwon_ck = {
  919. .name = "emu_mpu_alwon_ck",
  920. .ops = &clkops_null,
  921. .parent = &mpu_ck,
  922. .recalc = &followparent_recalc,
  923. };
  924. static struct clk dpll2_fck = {
  925. .name = "dpll2_fck",
  926. .ops = &clkops_null,
  927. .parent = &core_ck,
  928. .init = &omap2_init_clksel_parent,
  929. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
  930. .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
  931. .clksel = div4_core_clksel,
  932. .recalc = &omap2_clksel_recalc,
  933. };
  934. static struct clk iva2_ck = {
  935. .name = "iva2_ck",
  936. .ops = &clkops_omap2_dflt_wait,
  937. .parent = &dpll2_m2_ck,
  938. .init = &omap2_init_clksel_parent,
  939. .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
  940. .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
  941. .clkdm_name = "iva2_clkdm",
  942. .recalc = &followparent_recalc,
  943. };
  944. /* Common interface clocks */
  945. static const struct clksel div2_core_clksel[] = {
  946. { .parent = &core_ck, .rates = div2_rates },
  947. { .parent = NULL }
  948. };
  949. static struct clk l3_ick = {
  950. .name = "l3_ick",
  951. .ops = &clkops_null,
  952. .parent = &core_ck,
  953. .init = &omap2_init_clksel_parent,
  954. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  955. .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
  956. .clksel = div2_core_clksel,
  957. .clkdm_name = "core_l3_clkdm",
  958. .recalc = &omap2_clksel_recalc,
  959. };
  960. static const struct clksel div2_l3_clksel[] = {
  961. { .parent = &l3_ick, .rates = div2_rates },
  962. { .parent = NULL }
  963. };
  964. static struct clk l4_ick = {
  965. .name = "l4_ick",
  966. .ops = &clkops_null,
  967. .parent = &l3_ick,
  968. .init = &omap2_init_clksel_parent,
  969. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  970. .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
  971. .clksel = div2_l3_clksel,
  972. .clkdm_name = "core_l4_clkdm",
  973. .recalc = &omap2_clksel_recalc,
  974. };
  975. static const struct clksel div2_l4_clksel[] = {
  976. { .parent = &l4_ick, .rates = div2_rates },
  977. { .parent = NULL }
  978. };
  979. static struct clk rm_ick = {
  980. .name = "rm_ick",
  981. .ops = &clkops_null,
  982. .parent = &l4_ick,
  983. .init = &omap2_init_clksel_parent,
  984. .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
  985. .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
  986. .clksel = div2_l4_clksel,
  987. .recalc = &omap2_clksel_recalc,
  988. };
  989. /* GFX power domain */
  990. /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
  991. static const struct clksel gfx_l3_clksel[] = {
  992. { .parent = &l3_ick, .rates = gfx_l3_rates },
  993. { .parent = NULL }
  994. };
  995. /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
  996. static struct clk gfx_l3_ck = {
  997. .name = "gfx_l3_ck",
  998. .ops = &clkops_omap2_dflt_wait,
  999. .parent = &l3_ick,
  1000. .init = &omap2_init_clksel_parent,
  1001. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
  1002. .enable_bit = OMAP_EN_GFX_SHIFT,
  1003. .recalc = &followparent_recalc,
  1004. };
  1005. static struct clk gfx_l3_fck = {
  1006. .name = "gfx_l3_fck",
  1007. .ops = &clkops_null,
  1008. .parent = &gfx_l3_ck,
  1009. .init = &omap2_init_clksel_parent,
  1010. .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
  1011. .clksel_mask = OMAP_CLKSEL_GFX_MASK,
  1012. .clksel = gfx_l3_clksel,
  1013. .clkdm_name = "gfx_3430es1_clkdm",
  1014. .recalc = &omap2_clksel_recalc,
  1015. };
  1016. static struct clk gfx_l3_ick = {
  1017. .name = "gfx_l3_ick",
  1018. .ops = &clkops_null,
  1019. .parent = &gfx_l3_ck,
  1020. .clkdm_name = "gfx_3430es1_clkdm",
  1021. .recalc = &followparent_recalc,
  1022. };
  1023. static struct clk gfx_cg1_ck = {
  1024. .name = "gfx_cg1_ck",
  1025. .ops = &clkops_omap2_dflt_wait,
  1026. .parent = &gfx_l3_fck, /* REVISIT: correct? */
  1027. .init = &omap2_init_clk_clkdm,
  1028. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
  1029. .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
  1030. .clkdm_name = "gfx_3430es1_clkdm",
  1031. .recalc = &followparent_recalc,
  1032. };
  1033. static struct clk gfx_cg2_ck = {
  1034. .name = "gfx_cg2_ck",
  1035. .ops = &clkops_omap2_dflt_wait,
  1036. .parent = &gfx_l3_fck, /* REVISIT: correct? */
  1037. .init = &omap2_init_clk_clkdm,
  1038. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
  1039. .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
  1040. .clkdm_name = "gfx_3430es1_clkdm",
  1041. .recalc = &followparent_recalc,
  1042. };
  1043. /* SGX power domain - 3430ES2 only */
  1044. static const struct clksel_rate sgx_core_rates[] = {
  1045. { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
  1046. { .div = 4, .val = 1, .flags = RATE_IN_343X },
  1047. { .div = 6, .val = 2, .flags = RATE_IN_343X },
  1048. { .div = 0 },
  1049. };
  1050. static const struct clksel_rate sgx_96m_rates[] = {
  1051. { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
  1052. { .div = 0 },
  1053. };
  1054. static const struct clksel sgx_clksel[] = {
  1055. { .parent = &core_ck, .rates = sgx_core_rates },
  1056. { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
  1057. { .parent = NULL },
  1058. };
  1059. static struct clk sgx_fck = {
  1060. .name = "sgx_fck",
  1061. .ops = &clkops_omap2_dflt_wait,
  1062. .init = &omap2_init_clksel_parent,
  1063. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
  1064. .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
  1065. .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
  1066. .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
  1067. .clksel = sgx_clksel,
  1068. .clkdm_name = "sgx_clkdm",
  1069. .recalc = &omap2_clksel_recalc,
  1070. };
  1071. static struct clk sgx_ick = {
  1072. .name = "sgx_ick",
  1073. .ops = &clkops_omap2_dflt_wait,
  1074. .parent = &l3_ick,
  1075. .init = &omap2_init_clk_clkdm,
  1076. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
  1077. .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
  1078. .clkdm_name = "sgx_clkdm",
  1079. .recalc = &followparent_recalc,
  1080. };
  1081. /* CORE power domain */
  1082. static struct clk d2d_26m_fck = {
  1083. .name = "d2d_26m_fck",
  1084. .ops = &clkops_omap2_dflt_wait,
  1085. .parent = &sys_ck,
  1086. .init = &omap2_init_clk_clkdm,
  1087. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1088. .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
  1089. .clkdm_name = "d2d_clkdm",
  1090. .recalc = &followparent_recalc,
  1091. };
  1092. static struct clk modem_fck = {
  1093. .name = "modem_fck",
  1094. .ops = &clkops_omap2_dflt_wait,
  1095. .parent = &sys_ck,
  1096. .init = &omap2_init_clk_clkdm,
  1097. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1098. .enable_bit = OMAP3430_EN_MODEM_SHIFT,
  1099. .clkdm_name = "d2d_clkdm",
  1100. .recalc = &followparent_recalc,
  1101. };
  1102. static struct clk sad2d_ick = {
  1103. .name = "sad2d_ick",
  1104. .ops = &clkops_omap2_dflt_wait,
  1105. .parent = &l3_ick,
  1106. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1107. .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
  1108. .clkdm_name = "d2d_clkdm",
  1109. .recalc = &followparent_recalc,
  1110. };
  1111. static struct clk mad2d_ick = {
  1112. .name = "mad2d_ick",
  1113. .ops = &clkops_omap2_dflt_wait,
  1114. .parent = &l3_ick,
  1115. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
  1116. .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
  1117. .clkdm_name = "d2d_clkdm",
  1118. .recalc = &followparent_recalc,
  1119. };
  1120. static const struct clksel omap343x_gpt_clksel[] = {
  1121. { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
  1122. { .parent = &sys_ck, .rates = gpt_sys_rates },
  1123. { .parent = NULL}
  1124. };
  1125. static struct clk gpt10_fck = {
  1126. .name = "gpt10_fck",
  1127. .ops = &clkops_omap2_dflt_wait,
  1128. .parent = &sys_ck,
  1129. .init = &omap2_init_clksel_parent,
  1130. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1131. .enable_bit = OMAP3430_EN_GPT10_SHIFT,
  1132. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1133. .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
  1134. .clksel = omap343x_gpt_clksel,
  1135. .clkdm_name = "core_l4_clkdm",
  1136. .recalc = &omap2_clksel_recalc,
  1137. };
  1138. static struct clk gpt11_fck = {
  1139. .name = "gpt11_fck",
  1140. .ops = &clkops_omap2_dflt_wait,
  1141. .parent = &sys_ck,
  1142. .init = &omap2_init_clksel_parent,
  1143. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1144. .enable_bit = OMAP3430_EN_GPT11_SHIFT,
  1145. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1146. .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
  1147. .clksel = omap343x_gpt_clksel,
  1148. .clkdm_name = "core_l4_clkdm",
  1149. .recalc = &omap2_clksel_recalc,
  1150. };
  1151. static struct clk cpefuse_fck = {
  1152. .name = "cpefuse_fck",
  1153. .ops = &clkops_omap2_dflt,
  1154. .parent = &sys_ck,
  1155. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  1156. .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
  1157. .recalc = &followparent_recalc,
  1158. };
  1159. static struct clk ts_fck = {
  1160. .name = "ts_fck",
  1161. .ops = &clkops_omap2_dflt,
  1162. .parent = &omap_32k_fck,
  1163. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  1164. .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
  1165. .recalc = &followparent_recalc,
  1166. };
  1167. static struct clk usbtll_fck = {
  1168. .name = "usbtll_fck",
  1169. .ops = &clkops_omap2_dflt,
  1170. .parent = &dpll5_m2_ck,
  1171. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  1172. .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
  1173. .recalc = &followparent_recalc,
  1174. };
  1175. /* CORE 96M FCLK-derived clocks */
  1176. static struct clk core_96m_fck = {
  1177. .name = "core_96m_fck",
  1178. .ops = &clkops_null,
  1179. .parent = &omap_96m_fck,
  1180. .clkdm_name = "core_l4_clkdm",
  1181. .recalc = &followparent_recalc,
  1182. };
  1183. static struct clk mmchs3_fck = {
  1184. .name = "mmchs_fck",
  1185. .ops = &clkops_omap2_dflt_wait,
  1186. .id = 2,
  1187. .parent = &core_96m_fck,
  1188. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1189. .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
  1190. .clkdm_name = "core_l4_clkdm",
  1191. .recalc = &followparent_recalc,
  1192. };
  1193. static struct clk mmchs2_fck = {
  1194. .name = "mmchs_fck",
  1195. .ops = &clkops_omap2_dflt_wait,
  1196. .id = 1,
  1197. .parent = &core_96m_fck,
  1198. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1199. .enable_bit = OMAP3430_EN_MMC2_SHIFT,
  1200. .clkdm_name = "core_l4_clkdm",
  1201. .recalc = &followparent_recalc,
  1202. };
  1203. static struct clk mspro_fck = {
  1204. .name = "mspro_fck",
  1205. .ops = &clkops_omap2_dflt_wait,
  1206. .parent = &core_96m_fck,
  1207. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1208. .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
  1209. .clkdm_name = "core_l4_clkdm",
  1210. .recalc = &followparent_recalc,
  1211. };
  1212. static struct clk mmchs1_fck = {
  1213. .name = "mmchs_fck",
  1214. .ops = &clkops_omap2_dflt_wait,
  1215. .parent = &core_96m_fck,
  1216. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1217. .enable_bit = OMAP3430_EN_MMC1_SHIFT,
  1218. .clkdm_name = "core_l4_clkdm",
  1219. .recalc = &followparent_recalc,
  1220. };
  1221. static struct clk i2c3_fck = {
  1222. .name = "i2c_fck",
  1223. .ops = &clkops_omap2_dflt_wait,
  1224. .id = 3,
  1225. .parent = &core_96m_fck,
  1226. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1227. .enable_bit = OMAP3430_EN_I2C3_SHIFT,
  1228. .clkdm_name = "core_l4_clkdm",
  1229. .recalc = &followparent_recalc,
  1230. };
  1231. static struct clk i2c2_fck = {
  1232. .name = "i2c_fck",
  1233. .ops = &clkops_omap2_dflt_wait,
  1234. .id = 2,
  1235. .parent = &core_96m_fck,
  1236. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1237. .enable_bit = OMAP3430_EN_I2C2_SHIFT,
  1238. .clkdm_name = "core_l4_clkdm",
  1239. .recalc = &followparent_recalc,
  1240. };
  1241. static struct clk i2c1_fck = {
  1242. .name = "i2c_fck",
  1243. .ops = &clkops_omap2_dflt_wait,
  1244. .id = 1,
  1245. .parent = &core_96m_fck,
  1246. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1247. .enable_bit = OMAP3430_EN_I2C1_SHIFT,
  1248. .clkdm_name = "core_l4_clkdm",
  1249. .recalc = &followparent_recalc,
  1250. };
  1251. /*
  1252. * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
  1253. * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
  1254. */
  1255. static const struct clksel_rate common_mcbsp_96m_rates[] = {
  1256. { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
  1257. { .div = 0 }
  1258. };
  1259. static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
  1260. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  1261. { .div = 0 }
  1262. };
  1263. static const struct clksel mcbsp_15_clksel[] = {
  1264. { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
  1265. { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
  1266. { .parent = NULL }
  1267. };
  1268. static struct clk mcbsp5_fck = {
  1269. .name = "mcbsp_fck",
  1270. .ops = &clkops_omap2_dflt_wait,
  1271. .id = 5,
  1272. .init = &omap2_init_clksel_parent,
  1273. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1274. .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
  1275. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
  1276. .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
  1277. .clksel = mcbsp_15_clksel,
  1278. .clkdm_name = "core_l4_clkdm",
  1279. .recalc = &omap2_clksel_recalc,
  1280. };
  1281. static struct clk mcbsp1_fck = {
  1282. .name = "mcbsp_fck",
  1283. .ops = &clkops_omap2_dflt_wait,
  1284. .id = 1,
  1285. .init = &omap2_init_clksel_parent,
  1286. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1287. .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
  1288. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
  1289. .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
  1290. .clksel = mcbsp_15_clksel,
  1291. .clkdm_name = "core_l4_clkdm",
  1292. .recalc = &omap2_clksel_recalc,
  1293. };
  1294. /* CORE_48M_FCK-derived clocks */
  1295. static struct clk core_48m_fck = {
  1296. .name = "core_48m_fck",
  1297. .ops = &clkops_null,
  1298. .parent = &omap_48m_fck,
  1299. .clkdm_name = "core_l4_clkdm",
  1300. .recalc = &followparent_recalc,
  1301. };
  1302. static struct clk mcspi4_fck = {
  1303. .name = "mcspi_fck",
  1304. .ops = &clkops_omap2_dflt_wait,
  1305. .id = 4,
  1306. .parent = &core_48m_fck,
  1307. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1308. .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
  1309. .recalc = &followparent_recalc,
  1310. };
  1311. static struct clk mcspi3_fck = {
  1312. .name = "mcspi_fck",
  1313. .ops = &clkops_omap2_dflt_wait,
  1314. .id = 3,
  1315. .parent = &core_48m_fck,
  1316. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1317. .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
  1318. .recalc = &followparent_recalc,
  1319. };
  1320. static struct clk mcspi2_fck = {
  1321. .name = "mcspi_fck",
  1322. .ops = &clkops_omap2_dflt_wait,
  1323. .id = 2,
  1324. .parent = &core_48m_fck,
  1325. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1326. .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
  1327. .recalc = &followparent_recalc,
  1328. };
  1329. static struct clk mcspi1_fck = {
  1330. .name = "mcspi_fck",
  1331. .ops = &clkops_omap2_dflt_wait,
  1332. .id = 1,
  1333. .parent = &core_48m_fck,
  1334. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1335. .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
  1336. .recalc = &followparent_recalc,
  1337. };
  1338. static struct clk uart2_fck = {
  1339. .name = "uart2_fck",
  1340. .ops = &clkops_omap2_dflt_wait,
  1341. .parent = &core_48m_fck,
  1342. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1343. .enable_bit = OMAP3430_EN_UART2_SHIFT,
  1344. .recalc = &followparent_recalc,
  1345. };
  1346. static struct clk uart1_fck = {
  1347. .name = "uart1_fck",
  1348. .ops = &clkops_omap2_dflt_wait,
  1349. .parent = &core_48m_fck,
  1350. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1351. .enable_bit = OMAP3430_EN_UART1_SHIFT,
  1352. .recalc = &followparent_recalc,
  1353. };
  1354. static struct clk fshostusb_fck = {
  1355. .name = "fshostusb_fck",
  1356. .ops = &clkops_omap2_dflt_wait,
  1357. .parent = &core_48m_fck,
  1358. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1359. .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
  1360. .recalc = &followparent_recalc,
  1361. };
  1362. /* CORE_12M_FCK based clocks */
  1363. static struct clk core_12m_fck = {
  1364. .name = "core_12m_fck",
  1365. .ops = &clkops_null,
  1366. .parent = &omap_12m_fck,
  1367. .clkdm_name = "core_l4_clkdm",
  1368. .recalc = &followparent_recalc,
  1369. };
  1370. static struct clk hdq_fck = {
  1371. .name = "hdq_fck",
  1372. .ops = &clkops_omap2_dflt_wait,
  1373. .parent = &core_12m_fck,
  1374. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1375. .enable_bit = OMAP3430_EN_HDQ_SHIFT,
  1376. .recalc = &followparent_recalc,
  1377. };
  1378. /* DPLL3-derived clock */
  1379. static const struct clksel_rate ssi_ssr_corex2_rates[] = {
  1380. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  1381. { .div = 2, .val = 2, .flags = RATE_IN_343X },
  1382. { .div = 3, .val = 3, .flags = RATE_IN_343X },
  1383. { .div = 4, .val = 4, .flags = RATE_IN_343X },
  1384. { .div = 6, .val = 6, .flags = RATE_IN_343X },
  1385. { .div = 8, .val = 8, .flags = RATE_IN_343X },
  1386. { .div = 0 }
  1387. };
  1388. static const struct clksel ssi_ssr_clksel[] = {
  1389. { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
  1390. { .parent = NULL }
  1391. };
  1392. static struct clk ssi_ssr_fck_3430es1 = {
  1393. .name = "ssi_ssr_fck",
  1394. .ops = &clkops_omap2_dflt,
  1395. .init = &omap2_init_clksel_parent,
  1396. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1397. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1398. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1399. .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
  1400. .clksel = ssi_ssr_clksel,
  1401. .clkdm_name = "core_l4_clkdm",
  1402. .recalc = &omap2_clksel_recalc,
  1403. };
  1404. static struct clk ssi_ssr_fck_3430es2 = {
  1405. .name = "ssi_ssr_fck",
  1406. .ops = &clkops_omap3430es2_ssi_wait,
  1407. .init = &omap2_init_clksel_parent,
  1408. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1409. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1410. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1411. .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
  1412. .clksel = ssi_ssr_clksel,
  1413. .clkdm_name = "core_l4_clkdm",
  1414. .recalc = &omap2_clksel_recalc,
  1415. };
  1416. static struct clk ssi_sst_fck_3430es1 = {
  1417. .name = "ssi_sst_fck",
  1418. .ops = &clkops_null,
  1419. .parent = &ssi_ssr_fck_3430es1,
  1420. .fixed_div = 2,
  1421. .recalc = &omap2_fixed_divisor_recalc,
  1422. };
  1423. static struct clk ssi_sst_fck_3430es2 = {
  1424. .name = "ssi_sst_fck",
  1425. .ops = &clkops_null,
  1426. .parent = &ssi_ssr_fck_3430es2,
  1427. .fixed_div = 2,
  1428. .recalc = &omap2_fixed_divisor_recalc,
  1429. };
  1430. /* CORE_L3_ICK based clocks */
  1431. /*
  1432. * XXX must add clk_enable/clk_disable for these if standard code won't
  1433. * handle it
  1434. */
  1435. static struct clk core_l3_ick = {
  1436. .name = "core_l3_ick",
  1437. .ops = &clkops_null,
  1438. .parent = &l3_ick,
  1439. .init = &omap2_init_clk_clkdm,
  1440. .clkdm_name = "core_l3_clkdm",
  1441. .recalc = &followparent_recalc,
  1442. };
  1443. static struct clk hsotgusb_ick_3430es1 = {
  1444. .name = "hsotgusb_ick",
  1445. .ops = &clkops_omap2_dflt,
  1446. .parent = &core_l3_ick,
  1447. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1448. .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
  1449. .clkdm_name = "core_l3_clkdm",
  1450. .recalc = &followparent_recalc,
  1451. };
  1452. static struct clk hsotgusb_ick_3430es2 = {
  1453. .name = "hsotgusb_ick",
  1454. .ops = &clkops_omap3430es2_hsotgusb_wait,
  1455. .parent = &core_l3_ick,
  1456. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1457. .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
  1458. .clkdm_name = "core_l3_clkdm",
  1459. .recalc = &followparent_recalc,
  1460. };
  1461. static struct clk sdrc_ick = {
  1462. .name = "sdrc_ick",
  1463. .ops = &clkops_omap2_dflt_wait,
  1464. .parent = &core_l3_ick,
  1465. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1466. .enable_bit = OMAP3430_EN_SDRC_SHIFT,
  1467. .flags = ENABLE_ON_INIT,
  1468. .clkdm_name = "core_l3_clkdm",
  1469. .recalc = &followparent_recalc,
  1470. };
  1471. static struct clk gpmc_fck = {
  1472. .name = "gpmc_fck",
  1473. .ops = &clkops_null,
  1474. .parent = &core_l3_ick,
  1475. .flags = ENABLE_ON_INIT, /* huh? */
  1476. .clkdm_name = "core_l3_clkdm",
  1477. .recalc = &followparent_recalc,
  1478. };
  1479. /* SECURITY_L3_ICK based clocks */
  1480. static struct clk security_l3_ick = {
  1481. .name = "security_l3_ick",
  1482. .ops = &clkops_null,
  1483. .parent = &l3_ick,
  1484. .recalc = &followparent_recalc,
  1485. };
  1486. static struct clk pka_ick = {
  1487. .name = "pka_ick",
  1488. .ops = &clkops_omap2_dflt_wait,
  1489. .parent = &security_l3_ick,
  1490. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1491. .enable_bit = OMAP3430_EN_PKA_SHIFT,
  1492. .recalc = &followparent_recalc,
  1493. };
  1494. /* CORE_L4_ICK based clocks */
  1495. static struct clk core_l4_ick = {
  1496. .name = "core_l4_ick",
  1497. .ops = &clkops_null,
  1498. .parent = &l4_ick,
  1499. .init = &omap2_init_clk_clkdm,
  1500. .clkdm_name = "core_l4_clkdm",
  1501. .recalc = &followparent_recalc,
  1502. };
  1503. static struct clk usbtll_ick = {
  1504. .name = "usbtll_ick",
  1505. .ops = &clkops_omap2_dflt_wait,
  1506. .parent = &core_l4_ick,
  1507. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
  1508. .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
  1509. .clkdm_name = "core_l4_clkdm",
  1510. .recalc = &followparent_recalc,
  1511. };
  1512. static struct clk mmchs3_ick = {
  1513. .name = "mmchs_ick",
  1514. .ops = &clkops_omap2_dflt_wait,
  1515. .id = 2,
  1516. .parent = &core_l4_ick,
  1517. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1518. .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
  1519. .clkdm_name = "core_l4_clkdm",
  1520. .recalc = &followparent_recalc,
  1521. };
  1522. /* Intersystem Communication Registers - chassis mode only */
  1523. static struct clk icr_ick = {
  1524. .name = "icr_ick",
  1525. .ops = &clkops_omap2_dflt_wait,
  1526. .parent = &core_l4_ick,
  1527. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1528. .enable_bit = OMAP3430_EN_ICR_SHIFT,
  1529. .clkdm_name = "core_l4_clkdm",
  1530. .recalc = &followparent_recalc,
  1531. };
  1532. static struct clk aes2_ick = {
  1533. .name = "aes2_ick",
  1534. .ops = &clkops_omap2_dflt_wait,
  1535. .parent = &core_l4_ick,
  1536. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1537. .enable_bit = OMAP3430_EN_AES2_SHIFT,
  1538. .clkdm_name = "core_l4_clkdm",
  1539. .recalc = &followparent_recalc,
  1540. };
  1541. static struct clk sha12_ick = {
  1542. .name = "sha12_ick",
  1543. .ops = &clkops_omap2_dflt_wait,
  1544. .parent = &core_l4_ick,
  1545. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1546. .enable_bit = OMAP3430_EN_SHA12_SHIFT,
  1547. .clkdm_name = "core_l4_clkdm",
  1548. .recalc = &followparent_recalc,
  1549. };
  1550. static struct clk des2_ick = {
  1551. .name = "des2_ick",
  1552. .ops = &clkops_omap2_dflt_wait,
  1553. .parent = &core_l4_ick,
  1554. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1555. .enable_bit = OMAP3430_EN_DES2_SHIFT,
  1556. .clkdm_name = "core_l4_clkdm",
  1557. .recalc = &followparent_recalc,
  1558. };
  1559. static struct clk mmchs2_ick = {
  1560. .name = "mmchs_ick",
  1561. .ops = &clkops_omap2_dflt_wait,
  1562. .id = 1,
  1563. .parent = &core_l4_ick,
  1564. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1565. .enable_bit = OMAP3430_EN_MMC2_SHIFT,
  1566. .clkdm_name = "core_l4_clkdm",
  1567. .recalc = &followparent_recalc,
  1568. };
  1569. static struct clk mmchs1_ick = {
  1570. .name = "mmchs_ick",
  1571. .ops = &clkops_omap2_dflt_wait,
  1572. .parent = &core_l4_ick,
  1573. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1574. .enable_bit = OMAP3430_EN_MMC1_SHIFT,
  1575. .clkdm_name = "core_l4_clkdm",
  1576. .recalc = &followparent_recalc,
  1577. };
  1578. static struct clk mspro_ick = {
  1579. .name = "mspro_ick",
  1580. .ops = &clkops_omap2_dflt_wait,
  1581. .parent = &core_l4_ick,
  1582. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1583. .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
  1584. .clkdm_name = "core_l4_clkdm",
  1585. .recalc = &followparent_recalc,
  1586. };
  1587. static struct clk hdq_ick = {
  1588. .name = "hdq_ick",
  1589. .ops = &clkops_omap2_dflt_wait,
  1590. .parent = &core_l4_ick,
  1591. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1592. .enable_bit = OMAP3430_EN_HDQ_SHIFT,
  1593. .clkdm_name = "core_l4_clkdm",
  1594. .recalc = &followparent_recalc,
  1595. };
  1596. static struct clk mcspi4_ick = {
  1597. .name = "mcspi_ick",
  1598. .ops = &clkops_omap2_dflt_wait,
  1599. .id = 4,
  1600. .parent = &core_l4_ick,
  1601. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1602. .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
  1603. .clkdm_name = "core_l4_clkdm",
  1604. .recalc = &followparent_recalc,
  1605. };
  1606. static struct clk mcspi3_ick = {
  1607. .name = "mcspi_ick",
  1608. .ops = &clkops_omap2_dflt_wait,
  1609. .id = 3,
  1610. .parent = &core_l4_ick,
  1611. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1612. .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
  1613. .clkdm_name = "core_l4_clkdm",
  1614. .recalc = &followparent_recalc,
  1615. };
  1616. static struct clk mcspi2_ick = {
  1617. .name = "mcspi_ick",
  1618. .ops = &clkops_omap2_dflt_wait,
  1619. .id = 2,
  1620. .parent = &core_l4_ick,
  1621. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1622. .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
  1623. .clkdm_name = "core_l4_clkdm",
  1624. .recalc = &followparent_recalc,
  1625. };
  1626. static struct clk mcspi1_ick = {
  1627. .name = "mcspi_ick",
  1628. .ops = &clkops_omap2_dflt_wait,
  1629. .id = 1,
  1630. .parent = &core_l4_ick,
  1631. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1632. .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
  1633. .clkdm_name = "core_l4_clkdm",
  1634. .recalc = &followparent_recalc,
  1635. };
  1636. static struct clk i2c3_ick = {
  1637. .name = "i2c_ick",
  1638. .ops = &clkops_omap2_dflt_wait,
  1639. .id = 3,
  1640. .parent = &core_l4_ick,
  1641. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1642. .enable_bit = OMAP3430_EN_I2C3_SHIFT,
  1643. .clkdm_name = "core_l4_clkdm",
  1644. .recalc = &followparent_recalc,
  1645. };
  1646. static struct clk i2c2_ick = {
  1647. .name = "i2c_ick",
  1648. .ops = &clkops_omap2_dflt_wait,
  1649. .id = 2,
  1650. .parent = &core_l4_ick,
  1651. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1652. .enable_bit = OMAP3430_EN_I2C2_SHIFT,
  1653. .clkdm_name = "core_l4_clkdm",
  1654. .recalc = &followparent_recalc,
  1655. };
  1656. static struct clk i2c1_ick = {
  1657. .name = "i2c_ick",
  1658. .ops = &clkops_omap2_dflt_wait,
  1659. .id = 1,
  1660. .parent = &core_l4_ick,
  1661. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1662. .enable_bit = OMAP3430_EN_I2C1_SHIFT,
  1663. .clkdm_name = "core_l4_clkdm",
  1664. .recalc = &followparent_recalc,
  1665. };
  1666. static struct clk uart2_ick = {
  1667. .name = "uart2_ick",
  1668. .ops = &clkops_omap2_dflt_wait,
  1669. .parent = &core_l4_ick,
  1670. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1671. .enable_bit = OMAP3430_EN_UART2_SHIFT,
  1672. .clkdm_name = "core_l4_clkdm",
  1673. .recalc = &followparent_recalc,
  1674. };
  1675. static struct clk uart1_ick = {
  1676. .name = "uart1_ick",
  1677. .ops = &clkops_omap2_dflt_wait,
  1678. .parent = &core_l4_ick,
  1679. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1680. .enable_bit = OMAP3430_EN_UART1_SHIFT,
  1681. .clkdm_name = "core_l4_clkdm",
  1682. .recalc = &followparent_recalc,
  1683. };
  1684. static struct clk gpt11_ick = {
  1685. .name = "gpt11_ick",
  1686. .ops = &clkops_omap2_dflt_wait,
  1687. .parent = &core_l4_ick,
  1688. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1689. .enable_bit = OMAP3430_EN_GPT11_SHIFT,
  1690. .clkdm_name = "core_l4_clkdm",
  1691. .recalc = &followparent_recalc,
  1692. };
  1693. static struct clk gpt10_ick = {
  1694. .name = "gpt10_ick",
  1695. .ops = &clkops_omap2_dflt_wait,
  1696. .parent = &core_l4_ick,
  1697. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1698. .enable_bit = OMAP3430_EN_GPT10_SHIFT,
  1699. .clkdm_name = "core_l4_clkdm",
  1700. .recalc = &followparent_recalc,
  1701. };
  1702. static struct clk mcbsp5_ick = {
  1703. .name = "mcbsp_ick",
  1704. .ops = &clkops_omap2_dflt_wait,
  1705. .id = 5,
  1706. .parent = &core_l4_ick,
  1707. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1708. .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
  1709. .clkdm_name = "core_l4_clkdm",
  1710. .recalc = &followparent_recalc,
  1711. };
  1712. static struct clk mcbsp1_ick = {
  1713. .name = "mcbsp_ick",
  1714. .ops = &clkops_omap2_dflt_wait,
  1715. .id = 1,
  1716. .parent = &core_l4_ick,
  1717. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1718. .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
  1719. .clkdm_name = "core_l4_clkdm",
  1720. .recalc = &followparent_recalc,
  1721. };
  1722. static struct clk fac_ick = {
  1723. .name = "fac_ick",
  1724. .ops = &clkops_omap2_dflt_wait,
  1725. .parent = &core_l4_ick,
  1726. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1727. .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
  1728. .clkdm_name = "core_l4_clkdm",
  1729. .recalc = &followparent_recalc,
  1730. };
  1731. static struct clk mailboxes_ick = {
  1732. .name = "mailboxes_ick",
  1733. .ops = &clkops_omap2_dflt_wait,
  1734. .parent = &core_l4_ick,
  1735. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1736. .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
  1737. .clkdm_name = "core_l4_clkdm",
  1738. .recalc = &followparent_recalc,
  1739. };
  1740. static struct clk omapctrl_ick = {
  1741. .name = "omapctrl_ick",
  1742. .ops = &clkops_omap2_dflt_wait,
  1743. .parent = &core_l4_ick,
  1744. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1745. .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
  1746. .flags = ENABLE_ON_INIT,
  1747. .recalc = &followparent_recalc,
  1748. };
  1749. /* SSI_L4_ICK based clocks */
  1750. static struct clk ssi_l4_ick = {
  1751. .name = "ssi_l4_ick",
  1752. .ops = &clkops_null,
  1753. .parent = &l4_ick,
  1754. .clkdm_name = "core_l4_clkdm",
  1755. .recalc = &followparent_recalc,
  1756. };
  1757. static struct clk ssi_ick_3430es1 = {
  1758. .name = "ssi_ick",
  1759. .ops = &clkops_omap2_dflt,
  1760. .parent = &ssi_l4_ick,
  1761. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1762. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1763. .clkdm_name = "core_l4_clkdm",
  1764. .recalc = &followparent_recalc,
  1765. };
  1766. static struct clk ssi_ick_3430es2 = {
  1767. .name = "ssi_ick",
  1768. .ops = &clkops_omap3430es2_ssi_wait,
  1769. .parent = &ssi_l4_ick,
  1770. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1771. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1772. .clkdm_name = "core_l4_clkdm",
  1773. .recalc = &followparent_recalc,
  1774. };
  1775. /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
  1776. * but l4_ick makes more sense to me */
  1777. static const struct clksel usb_l4_clksel[] = {
  1778. { .parent = &l4_ick, .rates = div2_rates },
  1779. { .parent = NULL },
  1780. };
  1781. static struct clk usb_l4_ick = {
  1782. .name = "usb_l4_ick",
  1783. .ops = &clkops_omap2_dflt_wait,
  1784. .parent = &l4_ick,
  1785. .init = &omap2_init_clksel_parent,
  1786. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1787. .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
  1788. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1789. .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
  1790. .clksel = usb_l4_clksel,
  1791. .recalc = &omap2_clksel_recalc,
  1792. };
  1793. /* SECURITY_L4_ICK2 based clocks */
  1794. static struct clk security_l4_ick2 = {
  1795. .name = "security_l4_ick2",
  1796. .ops = &clkops_null,
  1797. .parent = &l4_ick,
  1798. .recalc = &followparent_recalc,
  1799. };
  1800. static struct clk aes1_ick = {
  1801. .name = "aes1_ick",
  1802. .ops = &clkops_omap2_dflt_wait,
  1803. .parent = &security_l4_ick2,
  1804. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1805. .enable_bit = OMAP3430_EN_AES1_SHIFT,
  1806. .recalc = &followparent_recalc,
  1807. };
  1808. static struct clk rng_ick = {
  1809. .name = "rng_ick",
  1810. .ops = &clkops_omap2_dflt_wait,
  1811. .parent = &security_l4_ick2,
  1812. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1813. .enable_bit = OMAP3430_EN_RNG_SHIFT,
  1814. .recalc = &followparent_recalc,
  1815. };
  1816. static struct clk sha11_ick = {
  1817. .name = "sha11_ick",
  1818. .ops = &clkops_omap2_dflt_wait,
  1819. .parent = &security_l4_ick2,
  1820. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1821. .enable_bit = OMAP3430_EN_SHA11_SHIFT,
  1822. .recalc = &followparent_recalc,
  1823. };
  1824. static struct clk des1_ick = {
  1825. .name = "des1_ick",
  1826. .ops = &clkops_omap2_dflt_wait,
  1827. .parent = &security_l4_ick2,
  1828. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
  1829. .enable_bit = OMAP3430_EN_DES1_SHIFT,
  1830. .recalc = &followparent_recalc,
  1831. };
  1832. /* DSS */
  1833. static struct clk dss1_alwon_fck_3430es1 = {
  1834. .name = "dss1_alwon_fck",
  1835. .ops = &clkops_omap2_dflt,
  1836. .parent = &dpll4_m4x2_ck,
  1837. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  1838. .enable_bit = OMAP3430_EN_DSS1_SHIFT,
  1839. .clkdm_name = "dss_clkdm",
  1840. .recalc = &followparent_recalc,
  1841. };
  1842. static struct clk dss1_alwon_fck_3430es2 = {
  1843. .name = "dss1_alwon_fck",
  1844. .ops = &clkops_omap3430es2_dss_usbhost_wait,
  1845. .parent = &dpll4_m4x2_ck,
  1846. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  1847. .enable_bit = OMAP3430_EN_DSS1_SHIFT,
  1848. .clkdm_name = "dss_clkdm",
  1849. .recalc = &followparent_recalc,
  1850. };
  1851. static struct clk dss_tv_fck = {
  1852. .name = "dss_tv_fck",
  1853. .ops = &clkops_omap2_dflt,
  1854. .parent = &omap_54m_fck,
  1855. .init = &omap2_init_clk_clkdm,
  1856. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  1857. .enable_bit = OMAP3430_EN_TV_SHIFT,
  1858. .clkdm_name = "dss_clkdm",
  1859. .recalc = &followparent_recalc,
  1860. };
  1861. static struct clk dss_96m_fck = {
  1862. .name = "dss_96m_fck",
  1863. .ops = &clkops_omap2_dflt,
  1864. .parent = &omap_96m_fck,
  1865. .init = &omap2_init_clk_clkdm,
  1866. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  1867. .enable_bit = OMAP3430_EN_TV_SHIFT,
  1868. .clkdm_name = "dss_clkdm",
  1869. .recalc = &followparent_recalc,
  1870. };
  1871. static struct clk dss2_alwon_fck = {
  1872. .name = "dss2_alwon_fck",
  1873. .ops = &clkops_omap2_dflt,
  1874. .parent = &sys_ck,
  1875. .init = &omap2_init_clk_clkdm,
  1876. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
  1877. .enable_bit = OMAP3430_EN_DSS2_SHIFT,
  1878. .clkdm_name = "dss_clkdm",
  1879. .recalc = &followparent_recalc,
  1880. };
  1881. static struct clk dss_ick_3430es1 = {
  1882. /* Handles both L3 and L4 clocks */
  1883. .name = "dss_ick",
  1884. .ops = &clkops_omap2_dflt,
  1885. .parent = &l4_ick,
  1886. .init = &omap2_init_clk_clkdm,
  1887. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
  1888. .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
  1889. .clkdm_name = "dss_clkdm",
  1890. .recalc = &followparent_recalc,
  1891. };
  1892. static struct clk dss_ick_3430es2 = {
  1893. /* Handles both L3 and L4 clocks */
  1894. .name = "dss_ick",
  1895. .ops = &clkops_omap3430es2_dss_usbhost_wait,
  1896. .parent = &l4_ick,
  1897. .init = &omap2_init_clk_clkdm,
  1898. .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
  1899. .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
  1900. .clkdm_name = "dss_clkdm",
  1901. .recalc = &followparent_recalc,
  1902. };
  1903. /* CAM */
  1904. static struct clk cam_mclk = {
  1905. .name = "cam_mclk",
  1906. .ops = &clkops_omap2_dflt,
  1907. .parent = &dpll4_m5x2_ck,
  1908. .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
  1909. .enable_bit = OMAP3430_EN_CAM_SHIFT,
  1910. .clkdm_name = "cam_clkdm",
  1911. .recalc = &followparent_recalc,
  1912. };
  1913. static struct clk cam_ick = {
  1914. /* Handles both L3 and L4 clocks */
  1915. .name = "cam_ick",
  1916. .ops = &clkops_omap2_dflt,
  1917. .parent = &l4_ick,
  1918. .init = &omap2_init_clk_clkdm,
  1919. .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
  1920. .enable_bit = OMAP3430_EN_CAM_SHIFT,
  1921. .clkdm_name = "cam_clkdm",
  1922. .recalc = &followparent_recalc,
  1923. };
  1924. static struct clk csi2_96m_fck = {
  1925. .name = "csi2_96m_fck",
  1926. .ops = &clkops_omap2_dflt,
  1927. .parent = &core_96m_fck,
  1928. .init = &omap2_init_clk_clkdm,
  1929. .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
  1930. .enable_bit = OMAP3430_EN_CSI2_SHIFT,
  1931. .clkdm_name = "cam_clkdm",
  1932. .recalc = &followparent_recalc,
  1933. };
  1934. /* USBHOST - 3430ES2 only */
  1935. static struct clk usbhost_120m_fck = {
  1936. .name = "usbhost_120m_fck",
  1937. .ops = &clkops_omap2_dflt,
  1938. .parent = &dpll5_m2_ck,
  1939. .init = &omap2_init_clk_clkdm,
  1940. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
  1941. .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
  1942. .clkdm_name = "usbhost_clkdm",
  1943. .recalc = &followparent_recalc,
  1944. };
  1945. static struct clk usbhost_48m_fck = {
  1946. .name = "usbhost_48m_fck",
  1947. .ops = &clkops_omap3430es2_dss_usbhost_wait,
  1948. .parent = &omap_48m_fck,
  1949. .init = &omap2_init_clk_clkdm,
  1950. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
  1951. .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
  1952. .clkdm_name = "usbhost_clkdm",
  1953. .recalc = &followparent_recalc,
  1954. };
  1955. static struct clk usbhost_ick = {
  1956. /* Handles both L3 and L4 clocks */
  1957. .name = "usbhost_ick",
  1958. .ops = &clkops_omap3430es2_dss_usbhost_wait,
  1959. .parent = &l4_ick,
  1960. .init = &omap2_init_clk_clkdm,
  1961. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
  1962. .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
  1963. .clkdm_name = "usbhost_clkdm",
  1964. .recalc = &followparent_recalc,
  1965. };
  1966. /* WKUP */
  1967. static const struct clksel_rate usim_96m_rates[] = {
  1968. { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
  1969. { .div = 4, .val = 4, .flags = RATE_IN_343X },
  1970. { .div = 8, .val = 5, .flags = RATE_IN_343X },
  1971. { .div = 10, .val = 6, .flags = RATE_IN_343X },
  1972. { .div = 0 },
  1973. };
  1974. static const struct clksel_rate usim_120m_rates[] = {
  1975. { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
  1976. { .div = 8, .val = 8, .flags = RATE_IN_343X },
  1977. { .div = 16, .val = 9, .flags = RATE_IN_343X },
  1978. { .div = 20, .val = 10, .flags = RATE_IN_343X },
  1979. { .div = 0 },
  1980. };
  1981. static const struct clksel usim_clksel[] = {
  1982. { .parent = &omap_96m_fck, .rates = usim_96m_rates },
  1983. { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
  1984. { .parent = &sys_ck, .rates = div2_rates },
  1985. { .parent = NULL },
  1986. };
  1987. /* 3430ES2 only */
  1988. static struct clk usim_fck = {
  1989. .name = "usim_fck",
  1990. .ops = &clkops_omap2_dflt_wait,
  1991. .init = &omap2_init_clksel_parent,
  1992. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  1993. .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
  1994. .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
  1995. .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
  1996. .clksel = usim_clksel,
  1997. .recalc = &omap2_clksel_recalc,
  1998. };
  1999. /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
  2000. static struct clk gpt1_fck = {
  2001. .name = "gpt1_fck",
  2002. .ops = &clkops_omap2_dflt_wait,
  2003. .init = &omap2_init_clksel_parent,
  2004. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2005. .enable_bit = OMAP3430_EN_GPT1_SHIFT,
  2006. .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
  2007. .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
  2008. .clksel = omap343x_gpt_clksel,
  2009. .clkdm_name = "wkup_clkdm",
  2010. .recalc = &omap2_clksel_recalc,
  2011. };
  2012. static struct clk wkup_32k_fck = {
  2013. .name = "wkup_32k_fck",
  2014. .ops = &clkops_null,
  2015. .init = &omap2_init_clk_clkdm,
  2016. .parent = &omap_32k_fck,
  2017. .clkdm_name = "wkup_clkdm",
  2018. .recalc = &followparent_recalc,
  2019. };
  2020. static struct clk gpio1_dbck = {
  2021. .name = "gpio1_dbck",
  2022. .ops = &clkops_omap2_dflt,
  2023. .parent = &wkup_32k_fck,
  2024. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2025. .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
  2026. .clkdm_name = "wkup_clkdm",
  2027. .recalc = &followparent_recalc,
  2028. };
  2029. static struct clk wdt2_fck = {
  2030. .name = "wdt2_fck",
  2031. .ops = &clkops_omap2_dflt_wait,
  2032. .parent = &wkup_32k_fck,
  2033. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2034. .enable_bit = OMAP3430_EN_WDT2_SHIFT,
  2035. .clkdm_name = "wkup_clkdm",
  2036. .recalc = &followparent_recalc,
  2037. };
  2038. static struct clk wkup_l4_ick = {
  2039. .name = "wkup_l4_ick",
  2040. .ops = &clkops_null,
  2041. .parent = &sys_ck,
  2042. .clkdm_name = "wkup_clkdm",
  2043. .recalc = &followparent_recalc,
  2044. };
  2045. /* 3430ES2 only */
  2046. /* Never specifically named in the TRM, so we have to infer a likely name */
  2047. static struct clk usim_ick = {
  2048. .name = "usim_ick",
  2049. .ops = &clkops_omap2_dflt_wait,
  2050. .parent = &wkup_l4_ick,
  2051. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2052. .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
  2053. .clkdm_name = "wkup_clkdm",
  2054. .recalc = &followparent_recalc,
  2055. };
  2056. static struct clk wdt2_ick = {
  2057. .name = "wdt2_ick",
  2058. .ops = &clkops_omap2_dflt_wait,
  2059. .parent = &wkup_l4_ick,
  2060. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2061. .enable_bit = OMAP3430_EN_WDT2_SHIFT,
  2062. .clkdm_name = "wkup_clkdm",
  2063. .recalc = &followparent_recalc,
  2064. };
  2065. static struct clk wdt1_ick = {
  2066. .name = "wdt1_ick",
  2067. .ops = &clkops_omap2_dflt_wait,
  2068. .parent = &wkup_l4_ick,
  2069. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2070. .enable_bit = OMAP3430_EN_WDT1_SHIFT,
  2071. .clkdm_name = "wkup_clkdm",
  2072. .recalc = &followparent_recalc,
  2073. };
  2074. static struct clk gpio1_ick = {
  2075. .name = "gpio1_ick",
  2076. .ops = &clkops_omap2_dflt_wait,
  2077. .parent = &wkup_l4_ick,
  2078. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2079. .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
  2080. .clkdm_name = "wkup_clkdm",
  2081. .recalc = &followparent_recalc,
  2082. };
  2083. static struct clk omap_32ksync_ick = {
  2084. .name = "omap_32ksync_ick",
  2085. .ops = &clkops_omap2_dflt_wait,
  2086. .parent = &wkup_l4_ick,
  2087. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2088. .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
  2089. .clkdm_name = "wkup_clkdm",
  2090. .recalc = &followparent_recalc,
  2091. };
  2092. /* XXX This clock no longer exists in 3430 TRM rev F */
  2093. static struct clk gpt12_ick = {
  2094. .name = "gpt12_ick",
  2095. .ops = &clkops_omap2_dflt_wait,
  2096. .parent = &wkup_l4_ick,
  2097. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2098. .enable_bit = OMAP3430_EN_GPT12_SHIFT,
  2099. .clkdm_name = "wkup_clkdm",
  2100. .recalc = &followparent_recalc,
  2101. };
  2102. static struct clk gpt1_ick = {
  2103. .name = "gpt1_ick",
  2104. .ops = &clkops_omap2_dflt_wait,
  2105. .parent = &wkup_l4_ick,
  2106. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
  2107. .enable_bit = OMAP3430_EN_GPT1_SHIFT,
  2108. .clkdm_name = "wkup_clkdm",
  2109. .recalc = &followparent_recalc,
  2110. };
  2111. /* PER clock domain */
  2112. static struct clk per_96m_fck = {
  2113. .name = "per_96m_fck",
  2114. .ops = &clkops_null,
  2115. .parent = &omap_96m_alwon_fck,
  2116. .init = &omap2_init_clk_clkdm,
  2117. .clkdm_name = "per_clkdm",
  2118. .recalc = &followparent_recalc,
  2119. };
  2120. static struct clk per_48m_fck = {
  2121. .name = "per_48m_fck",
  2122. .ops = &clkops_null,
  2123. .parent = &omap_48m_fck,
  2124. .init = &omap2_init_clk_clkdm,
  2125. .clkdm_name = "per_clkdm",
  2126. .recalc = &followparent_recalc,
  2127. };
  2128. static struct clk uart3_fck = {
  2129. .name = "uart3_fck",
  2130. .ops = &clkops_omap2_dflt_wait,
  2131. .parent = &per_48m_fck,
  2132. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2133. .enable_bit = OMAP3430_EN_UART3_SHIFT,
  2134. .clkdm_name = "per_clkdm",
  2135. .recalc = &followparent_recalc,
  2136. };
  2137. static struct clk gpt2_fck = {
  2138. .name = "gpt2_fck",
  2139. .ops = &clkops_omap2_dflt_wait,
  2140. .init = &omap2_init_clksel_parent,
  2141. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2142. .enable_bit = OMAP3430_EN_GPT2_SHIFT,
  2143. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2144. .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
  2145. .clksel = omap343x_gpt_clksel,
  2146. .clkdm_name = "per_clkdm",
  2147. .recalc = &omap2_clksel_recalc,
  2148. };
  2149. static struct clk gpt3_fck = {
  2150. .name = "gpt3_fck",
  2151. .ops = &clkops_omap2_dflt_wait,
  2152. .init = &omap2_init_clksel_parent,
  2153. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2154. .enable_bit = OMAP3430_EN_GPT3_SHIFT,
  2155. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2156. .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
  2157. .clksel = omap343x_gpt_clksel,
  2158. .clkdm_name = "per_clkdm",
  2159. .recalc = &omap2_clksel_recalc,
  2160. };
  2161. static struct clk gpt4_fck = {
  2162. .name = "gpt4_fck",
  2163. .ops = &clkops_omap2_dflt_wait,
  2164. .init = &omap2_init_clksel_parent,
  2165. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2166. .enable_bit = OMAP3430_EN_GPT4_SHIFT,
  2167. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2168. .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
  2169. .clksel = omap343x_gpt_clksel,
  2170. .clkdm_name = "per_clkdm",
  2171. .recalc = &omap2_clksel_recalc,
  2172. };
  2173. static struct clk gpt5_fck = {
  2174. .name = "gpt5_fck",
  2175. .ops = &clkops_omap2_dflt_wait,
  2176. .init = &omap2_init_clksel_parent,
  2177. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2178. .enable_bit = OMAP3430_EN_GPT5_SHIFT,
  2179. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2180. .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
  2181. .clksel = omap343x_gpt_clksel,
  2182. .clkdm_name = "per_clkdm",
  2183. .recalc = &omap2_clksel_recalc,
  2184. };
  2185. static struct clk gpt6_fck = {
  2186. .name = "gpt6_fck",
  2187. .ops = &clkops_omap2_dflt_wait,
  2188. .init = &omap2_init_clksel_parent,
  2189. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2190. .enable_bit = OMAP3430_EN_GPT6_SHIFT,
  2191. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2192. .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
  2193. .clksel = omap343x_gpt_clksel,
  2194. .clkdm_name = "per_clkdm",
  2195. .recalc = &omap2_clksel_recalc,
  2196. };
  2197. static struct clk gpt7_fck = {
  2198. .name = "gpt7_fck",
  2199. .ops = &clkops_omap2_dflt_wait,
  2200. .init = &omap2_init_clksel_parent,
  2201. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2202. .enable_bit = OMAP3430_EN_GPT7_SHIFT,
  2203. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2204. .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
  2205. .clksel = omap343x_gpt_clksel,
  2206. .clkdm_name = "per_clkdm",
  2207. .recalc = &omap2_clksel_recalc,
  2208. };
  2209. static struct clk gpt8_fck = {
  2210. .name = "gpt8_fck",
  2211. .ops = &clkops_omap2_dflt_wait,
  2212. .init = &omap2_init_clksel_parent,
  2213. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2214. .enable_bit = OMAP3430_EN_GPT8_SHIFT,
  2215. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2216. .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
  2217. .clksel = omap343x_gpt_clksel,
  2218. .clkdm_name = "per_clkdm",
  2219. .recalc = &omap2_clksel_recalc,
  2220. };
  2221. static struct clk gpt9_fck = {
  2222. .name = "gpt9_fck",
  2223. .ops = &clkops_omap2_dflt_wait,
  2224. .init = &omap2_init_clksel_parent,
  2225. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2226. .enable_bit = OMAP3430_EN_GPT9_SHIFT,
  2227. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
  2228. .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
  2229. .clksel = omap343x_gpt_clksel,
  2230. .clkdm_name = "per_clkdm",
  2231. .recalc = &omap2_clksel_recalc,
  2232. };
  2233. static struct clk per_32k_alwon_fck = {
  2234. .name = "per_32k_alwon_fck",
  2235. .ops = &clkops_null,
  2236. .parent = &omap_32k_fck,
  2237. .clkdm_name = "per_clkdm",
  2238. .recalc = &followparent_recalc,
  2239. };
  2240. static struct clk gpio6_dbck = {
  2241. .name = "gpio6_dbck",
  2242. .ops = &clkops_omap2_dflt,
  2243. .parent = &per_32k_alwon_fck,
  2244. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2245. .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
  2246. .clkdm_name = "per_clkdm",
  2247. .recalc = &followparent_recalc,
  2248. };
  2249. static struct clk gpio5_dbck = {
  2250. .name = "gpio5_dbck",
  2251. .ops = &clkops_omap2_dflt,
  2252. .parent = &per_32k_alwon_fck,
  2253. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2254. .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
  2255. .clkdm_name = "per_clkdm",
  2256. .recalc = &followparent_recalc,
  2257. };
  2258. static struct clk gpio4_dbck = {
  2259. .name = "gpio4_dbck",
  2260. .ops = &clkops_omap2_dflt,
  2261. .parent = &per_32k_alwon_fck,
  2262. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2263. .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
  2264. .clkdm_name = "per_clkdm",
  2265. .recalc = &followparent_recalc,
  2266. };
  2267. static struct clk gpio3_dbck = {
  2268. .name = "gpio3_dbck",
  2269. .ops = &clkops_omap2_dflt,
  2270. .parent = &per_32k_alwon_fck,
  2271. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2272. .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
  2273. .clkdm_name = "per_clkdm",
  2274. .recalc = &followparent_recalc,
  2275. };
  2276. static struct clk gpio2_dbck = {
  2277. .name = "gpio2_dbck",
  2278. .ops = &clkops_omap2_dflt,
  2279. .parent = &per_32k_alwon_fck,
  2280. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2281. .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
  2282. .clkdm_name = "per_clkdm",
  2283. .recalc = &followparent_recalc,
  2284. };
  2285. static struct clk wdt3_fck = {
  2286. .name = "wdt3_fck",
  2287. .ops = &clkops_omap2_dflt_wait,
  2288. .parent = &per_32k_alwon_fck,
  2289. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2290. .enable_bit = OMAP3430_EN_WDT3_SHIFT,
  2291. .clkdm_name = "per_clkdm",
  2292. .recalc = &followparent_recalc,
  2293. };
  2294. static struct clk per_l4_ick = {
  2295. .name = "per_l4_ick",
  2296. .ops = &clkops_null,
  2297. .parent = &l4_ick,
  2298. .clkdm_name = "per_clkdm",
  2299. .recalc = &followparent_recalc,
  2300. };
  2301. static struct clk gpio6_ick = {
  2302. .name = "gpio6_ick",
  2303. .ops = &clkops_omap2_dflt_wait,
  2304. .parent = &per_l4_ick,
  2305. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2306. .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
  2307. .clkdm_name = "per_clkdm",
  2308. .recalc = &followparent_recalc,
  2309. };
  2310. static struct clk gpio5_ick = {
  2311. .name = "gpio5_ick",
  2312. .ops = &clkops_omap2_dflt_wait,
  2313. .parent = &per_l4_ick,
  2314. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2315. .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
  2316. .clkdm_name = "per_clkdm",
  2317. .recalc = &followparent_recalc,
  2318. };
  2319. static struct clk gpio4_ick = {
  2320. .name = "gpio4_ick",
  2321. .ops = &clkops_omap2_dflt_wait,
  2322. .parent = &per_l4_ick,
  2323. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2324. .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
  2325. .clkdm_name = "per_clkdm",
  2326. .recalc = &followparent_recalc,
  2327. };
  2328. static struct clk gpio3_ick = {
  2329. .name = "gpio3_ick",
  2330. .ops = &clkops_omap2_dflt_wait,
  2331. .parent = &per_l4_ick,
  2332. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2333. .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
  2334. .clkdm_name = "per_clkdm",
  2335. .recalc = &followparent_recalc,
  2336. };
  2337. static struct clk gpio2_ick = {
  2338. .name = "gpio2_ick",
  2339. .ops = &clkops_omap2_dflt_wait,
  2340. .parent = &per_l4_ick,
  2341. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2342. .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
  2343. .clkdm_name = "per_clkdm",
  2344. .recalc = &followparent_recalc,
  2345. };
  2346. static struct clk wdt3_ick = {
  2347. .name = "wdt3_ick",
  2348. .ops = &clkops_omap2_dflt_wait,
  2349. .parent = &per_l4_ick,
  2350. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2351. .enable_bit = OMAP3430_EN_WDT3_SHIFT,
  2352. .clkdm_name = "per_clkdm",
  2353. .recalc = &followparent_recalc,
  2354. };
  2355. static struct clk uart3_ick = {
  2356. .name = "uart3_ick",
  2357. .ops = &clkops_omap2_dflt_wait,
  2358. .parent = &per_l4_ick,
  2359. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2360. .enable_bit = OMAP3430_EN_UART3_SHIFT,
  2361. .clkdm_name = "per_clkdm",
  2362. .recalc = &followparent_recalc,
  2363. };
  2364. static struct clk gpt9_ick = {
  2365. .name = "gpt9_ick",
  2366. .ops = &clkops_omap2_dflt_wait,
  2367. .parent = &per_l4_ick,
  2368. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2369. .enable_bit = OMAP3430_EN_GPT9_SHIFT,
  2370. .clkdm_name = "per_clkdm",
  2371. .recalc = &followparent_recalc,
  2372. };
  2373. static struct clk gpt8_ick = {
  2374. .name = "gpt8_ick",
  2375. .ops = &clkops_omap2_dflt_wait,
  2376. .parent = &per_l4_ick,
  2377. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2378. .enable_bit = OMAP3430_EN_GPT8_SHIFT,
  2379. .clkdm_name = "per_clkdm",
  2380. .recalc = &followparent_recalc,
  2381. };
  2382. static struct clk gpt7_ick = {
  2383. .name = "gpt7_ick",
  2384. .ops = &clkops_omap2_dflt_wait,
  2385. .parent = &per_l4_ick,
  2386. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2387. .enable_bit = OMAP3430_EN_GPT7_SHIFT,
  2388. .clkdm_name = "per_clkdm",
  2389. .recalc = &followparent_recalc,
  2390. };
  2391. static struct clk gpt6_ick = {
  2392. .name = "gpt6_ick",
  2393. .ops = &clkops_omap2_dflt_wait,
  2394. .parent = &per_l4_ick,
  2395. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2396. .enable_bit = OMAP3430_EN_GPT6_SHIFT,
  2397. .clkdm_name = "per_clkdm",
  2398. .recalc = &followparent_recalc,
  2399. };
  2400. static struct clk gpt5_ick = {
  2401. .name = "gpt5_ick",
  2402. .ops = &clkops_omap2_dflt_wait,
  2403. .parent = &per_l4_ick,
  2404. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2405. .enable_bit = OMAP3430_EN_GPT5_SHIFT,
  2406. .clkdm_name = "per_clkdm",
  2407. .recalc = &followparent_recalc,
  2408. };
  2409. static struct clk gpt4_ick = {
  2410. .name = "gpt4_ick",
  2411. .ops = &clkops_omap2_dflt_wait,
  2412. .parent = &per_l4_ick,
  2413. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2414. .enable_bit = OMAP3430_EN_GPT4_SHIFT,
  2415. .clkdm_name = "per_clkdm",
  2416. .recalc = &followparent_recalc,
  2417. };
  2418. static struct clk gpt3_ick = {
  2419. .name = "gpt3_ick",
  2420. .ops = &clkops_omap2_dflt_wait,
  2421. .parent = &per_l4_ick,
  2422. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2423. .enable_bit = OMAP3430_EN_GPT3_SHIFT,
  2424. .clkdm_name = "per_clkdm",
  2425. .recalc = &followparent_recalc,
  2426. };
  2427. static struct clk gpt2_ick = {
  2428. .name = "gpt2_ick",
  2429. .ops = &clkops_omap2_dflt_wait,
  2430. .parent = &per_l4_ick,
  2431. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2432. .enable_bit = OMAP3430_EN_GPT2_SHIFT,
  2433. .clkdm_name = "per_clkdm",
  2434. .recalc = &followparent_recalc,
  2435. };
  2436. static struct clk mcbsp2_ick = {
  2437. .name = "mcbsp_ick",
  2438. .ops = &clkops_omap2_dflt_wait,
  2439. .id = 2,
  2440. .parent = &per_l4_ick,
  2441. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2442. .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
  2443. .clkdm_name = "per_clkdm",
  2444. .recalc = &followparent_recalc,
  2445. };
  2446. static struct clk mcbsp3_ick = {
  2447. .name = "mcbsp_ick",
  2448. .ops = &clkops_omap2_dflt_wait,
  2449. .id = 3,
  2450. .parent = &per_l4_ick,
  2451. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2452. .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
  2453. .clkdm_name = "per_clkdm",
  2454. .recalc = &followparent_recalc,
  2455. };
  2456. static struct clk mcbsp4_ick = {
  2457. .name = "mcbsp_ick",
  2458. .ops = &clkops_omap2_dflt_wait,
  2459. .id = 4,
  2460. .parent = &per_l4_ick,
  2461. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
  2462. .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
  2463. .clkdm_name = "per_clkdm",
  2464. .recalc = &followparent_recalc,
  2465. };
  2466. static const struct clksel mcbsp_234_clksel[] = {
  2467. { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
  2468. { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
  2469. { .parent = NULL }
  2470. };
  2471. static struct clk mcbsp2_fck = {
  2472. .name = "mcbsp_fck",
  2473. .ops = &clkops_omap2_dflt_wait,
  2474. .id = 2,
  2475. .init = &omap2_init_clksel_parent,
  2476. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2477. .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
  2478. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
  2479. .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
  2480. .clksel = mcbsp_234_clksel,
  2481. .clkdm_name = "per_clkdm",
  2482. .recalc = &omap2_clksel_recalc,
  2483. };
  2484. static struct clk mcbsp3_fck = {
  2485. .name = "mcbsp_fck",
  2486. .ops = &clkops_omap2_dflt_wait,
  2487. .id = 3,
  2488. .init = &omap2_init_clksel_parent,
  2489. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2490. .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
  2491. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
  2492. .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
  2493. .clksel = mcbsp_234_clksel,
  2494. .clkdm_name = "per_clkdm",
  2495. .recalc = &omap2_clksel_recalc,
  2496. };
  2497. static struct clk mcbsp4_fck = {
  2498. .name = "mcbsp_fck",
  2499. .ops = &clkops_omap2_dflt_wait,
  2500. .id = 4,
  2501. .init = &omap2_init_clksel_parent,
  2502. .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
  2503. .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
  2504. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
  2505. .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
  2506. .clksel = mcbsp_234_clksel,
  2507. .clkdm_name = "per_clkdm",
  2508. .recalc = &omap2_clksel_recalc,
  2509. };
  2510. /* EMU clocks */
  2511. /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
  2512. static const struct clksel_rate emu_src_sys_rates[] = {
  2513. { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
  2514. { .div = 0 },
  2515. };
  2516. static const struct clksel_rate emu_src_core_rates[] = {
  2517. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  2518. { .div = 0 },
  2519. };
  2520. static const struct clksel_rate emu_src_per_rates[] = {
  2521. { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
  2522. { .div = 0 },
  2523. };
  2524. static const struct clksel_rate emu_src_mpu_rates[] = {
  2525. { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
  2526. { .div = 0 },
  2527. };
  2528. static const struct clksel emu_src_clksel[] = {
  2529. { .parent = &sys_ck, .rates = emu_src_sys_rates },
  2530. { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
  2531. { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
  2532. { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
  2533. { .parent = NULL },
  2534. };
  2535. /*
  2536. * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
  2537. * to switch the source of some of the EMU clocks.
  2538. * XXX Are there CLKEN bits for these EMU clks?
  2539. */
  2540. static struct clk emu_src_ck = {
  2541. .name = "emu_src_ck",
  2542. .ops = &clkops_null,
  2543. .init = &omap2_init_clksel_parent,
  2544. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2545. .clksel_mask = OMAP3430_MUX_CTRL_MASK,
  2546. .clksel = emu_src_clksel,
  2547. .clkdm_name = "emu_clkdm",
  2548. .recalc = &omap2_clksel_recalc,
  2549. };
  2550. static const struct clksel_rate pclk_emu_rates[] = {
  2551. { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
  2552. { .div = 3, .val = 3, .flags = RATE_IN_343X },
  2553. { .div = 4, .val = 4, .flags = RATE_IN_343X },
  2554. { .div = 6, .val = 6, .flags = RATE_IN_343X },
  2555. { .div = 0 },
  2556. };
  2557. static const struct clksel pclk_emu_clksel[] = {
  2558. { .parent = &emu_src_ck, .rates = pclk_emu_rates },
  2559. { .parent = NULL },
  2560. };
  2561. static struct clk pclk_fck = {
  2562. .name = "pclk_fck",
  2563. .ops = &clkops_null,
  2564. .init = &omap2_init_clksel_parent,
  2565. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2566. .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
  2567. .clksel = pclk_emu_clksel,
  2568. .clkdm_name = "emu_clkdm",
  2569. .recalc = &omap2_clksel_recalc,
  2570. };
  2571. static const struct clksel_rate pclkx2_emu_rates[] = {
  2572. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  2573. { .div = 2, .val = 2, .flags = RATE_IN_343X },
  2574. { .div = 3, .val = 3, .flags = RATE_IN_343X },
  2575. { .div = 0 },
  2576. };
  2577. static const struct clksel pclkx2_emu_clksel[] = {
  2578. { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
  2579. { .parent = NULL },
  2580. };
  2581. static struct clk pclkx2_fck = {
  2582. .name = "pclkx2_fck",
  2583. .ops = &clkops_null,
  2584. .init = &omap2_init_clksel_parent,
  2585. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2586. .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
  2587. .clksel = pclkx2_emu_clksel,
  2588. .clkdm_name = "emu_clkdm",
  2589. .recalc = &omap2_clksel_recalc,
  2590. };
  2591. static const struct clksel atclk_emu_clksel[] = {
  2592. { .parent = &emu_src_ck, .rates = div2_rates },
  2593. { .parent = NULL },
  2594. };
  2595. static struct clk atclk_fck = {
  2596. .name = "atclk_fck",
  2597. .ops = &clkops_null,
  2598. .init = &omap2_init_clksel_parent,
  2599. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2600. .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
  2601. .clksel = atclk_emu_clksel,
  2602. .clkdm_name = "emu_clkdm",
  2603. .recalc = &omap2_clksel_recalc,
  2604. };
  2605. static struct clk traceclk_src_fck = {
  2606. .name = "traceclk_src_fck",
  2607. .ops = &clkops_null,
  2608. .init = &omap2_init_clksel_parent,
  2609. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2610. .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
  2611. .clksel = emu_src_clksel,
  2612. .clkdm_name = "emu_clkdm",
  2613. .recalc = &omap2_clksel_recalc,
  2614. };
  2615. static const struct clksel_rate traceclk_rates[] = {
  2616. { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
  2617. { .div = 2, .val = 2, .flags = RATE_IN_343X },
  2618. { .div = 4, .val = 4, .flags = RATE_IN_343X },
  2619. { .div = 0 },
  2620. };
  2621. static const struct clksel traceclk_clksel[] = {
  2622. { .parent = &traceclk_src_fck, .rates = traceclk_rates },
  2623. { .parent = NULL },
  2624. };
  2625. static struct clk traceclk_fck = {
  2626. .name = "traceclk_fck",
  2627. .ops = &clkops_null,
  2628. .init = &omap2_init_clksel_parent,
  2629. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  2630. .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
  2631. .clksel = traceclk_clksel,
  2632. .clkdm_name = "emu_clkdm",
  2633. .recalc = &omap2_clksel_recalc,
  2634. };
  2635. /* SR clocks */
  2636. /* SmartReflex fclk (VDD1) */
  2637. static struct clk sr1_fck = {
  2638. .name = "sr1_fck",
  2639. .ops = &clkops_omap2_dflt_wait,
  2640. .parent = &sys_ck,
  2641. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2642. .enable_bit = OMAP3430_EN_SR1_SHIFT,
  2643. .recalc = &followparent_recalc,
  2644. };
  2645. /* SmartReflex fclk (VDD2) */
  2646. static struct clk sr2_fck = {
  2647. .name = "sr2_fck",
  2648. .ops = &clkops_omap2_dflt_wait,
  2649. .parent = &sys_ck,
  2650. .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
  2651. .enable_bit = OMAP3430_EN_SR2_SHIFT,
  2652. .recalc = &followparent_recalc,
  2653. };
  2654. static struct clk sr_l4_ick = {
  2655. .name = "sr_l4_ick",
  2656. .ops = &clkops_null, /* RMK: missing? */
  2657. .parent = &l4_ick,
  2658. .clkdm_name = "core_l4_clkdm",
  2659. .recalc = &followparent_recalc,
  2660. };
  2661. /* SECURE_32K_FCK clocks */
  2662. static struct clk gpt12_fck = {
  2663. .name = "gpt12_fck",
  2664. .ops = &clkops_null,
  2665. .parent = &secure_32k_fck,
  2666. .recalc = &followparent_recalc,
  2667. };
  2668. static struct clk wdt1_fck = {
  2669. .name = "wdt1_fck",
  2670. .ops = &clkops_null,
  2671. .parent = &secure_32k_fck,
  2672. .recalc = &followparent_recalc,
  2673. };
  2674. #endif