r8a7790.dtsi 2.4 KB

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  1. /*
  2. * Device Tree Source for the r8a7790 SoC
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. / {
  11. compatible = "renesas,r8a7790";
  12. interrupt-parent = <&gic>;
  13. #address-cells = <2>;
  14. #size-cells = <2>;
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. cpu0: cpu@0 {
  19. device_type = "cpu";
  20. compatible = "arm,cortex-a15";
  21. reg = <0>;
  22. clock-frequency = <1300000000>;
  23. };
  24. };
  25. gic: interrupt-controller@f1001000 {
  26. compatible = "arm,cortex-a15-gic";
  27. #interrupt-cells = <3>;
  28. #address-cells = <0>;
  29. interrupt-controller;
  30. reg = <0 0xf1001000 0 0x1000>,
  31. <0 0xf1002000 0 0x1000>,
  32. <0 0xf1004000 0 0x2000>,
  33. <0 0xf1006000 0 0x2000>;
  34. interrupts = <1 9 0xf04>;
  35. };
  36. timer {
  37. compatible = "arm,armv7-timer";
  38. interrupts = <1 13 0xf08>,
  39. <1 14 0xf08>,
  40. <1 11 0xf08>,
  41. <1 10 0xf08>;
  42. };
  43. irqc0: interrupt-controller@e61c0000 {
  44. compatible = "renesas,irqc";
  45. #interrupt-cells = <2>;
  46. interrupt-controller;
  47. reg = <0 0xe61c0000 0 0x200>;
  48. interrupt-parent = <&gic>;
  49. interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
  50. };
  51. mmcif0: mmcif@ee200000 {
  52. compatible = "renesas,sh-mmcif";
  53. reg = <0 0xee200000 0 0x80>;
  54. interrupt-parent = <&gic>;
  55. interrupts = <0 169 0x4>;
  56. reg-io-width = <4>;
  57. status = "disabled";
  58. };
  59. mmcif1: mmcif@ee220000 {
  60. compatible = "renesas,sh-mmcif";
  61. reg = <0 0xee220000 0 0x80>;
  62. interrupt-parent = <&gic>;
  63. interrupts = <0 170 0x4>;
  64. reg-io-width = <4>;
  65. status = "disabled";
  66. };
  67. sdhi0: sdhi@ee100000 {
  68. compatible = "renesas,r8a7790-sdhi";
  69. reg = <0 0xee100000 0 0x100>;
  70. interrupt-parent = <&gic>;
  71. interrupts = <0 165 4>;
  72. cap-sd-highspeed;
  73. status = "disabled";
  74. };
  75. sdhi1: sdhi@ee120000 {
  76. compatible = "renesas,r8a7790-sdhi";
  77. reg = <0 0xee120000 0 0x100>;
  78. interrupt-parent = <&gic>;
  79. interrupts = <0 166 4>;
  80. cap-sd-highspeed;
  81. status = "disabled";
  82. };
  83. sdhi2: sdhi@ee140000 {
  84. compatible = "renesas,r8a7790-sdhi";
  85. reg = <0 0xee140000 0 0x100>;
  86. interrupt-parent = <&gic>;
  87. interrupts = <0 167 4>;
  88. cap-sd-highspeed;
  89. status = "disabled";
  90. };
  91. sdhi3: sdhi@ee160000 {
  92. compatible = "renesas,r8a7790-sdhi";
  93. reg = <0 0xee160000 0 0x100>;
  94. interrupt-parent = <&gic>;
  95. interrupts = <0 168 4>;
  96. cap-sd-highspeed;
  97. status = "disabled";
  98. };
  99. };