cb710-mmc.c 22 KB

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  1. /*
  2. * cb710/mmc.c
  3. *
  4. * Copyright by Michał Mirosław, 2008-2009
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/pci.h>
  13. #include <linux/delay.h>
  14. #include "cb710-mmc.h"
  15. static const u8 cb710_clock_divider_log2[8] = {
  16. /* 1, 2, 4, 8, 16, 32, 128, 512 */
  17. 0, 1, 2, 3, 4, 5, 7, 9
  18. };
  19. #define CB710_MAX_DIVIDER_IDX \
  20. (ARRAY_SIZE(cb710_clock_divider_log2) - 1)
  21. static const u8 cb710_src_freq_mhz[16] = {
  22. 33, 10, 20, 25, 30, 35, 40, 45,
  23. 50, 55, 60, 65, 70, 75, 80, 85
  24. };
  25. static void cb710_mmc_select_clock_divider(struct mmc_host *mmc, int hz)
  26. {
  27. struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
  28. struct pci_dev *pdev = cb710_slot_to_chip(slot)->pdev;
  29. u32 src_freq_idx;
  30. u32 divider_idx;
  31. int src_hz;
  32. /* on CB710 in HP nx9500:
  33. * src_freq_idx == 0
  34. * indexes 1-7 work as written in the table
  35. * indexes 0,8-15 give no clock output
  36. */
  37. pci_read_config_dword(pdev, 0x48, &src_freq_idx);
  38. src_freq_idx = (src_freq_idx >> 16) & 0xF;
  39. src_hz = cb710_src_freq_mhz[src_freq_idx] * 1000000;
  40. for (divider_idx = 0; divider_idx < CB710_MAX_DIVIDER_IDX; ++divider_idx) {
  41. if (hz >= src_hz >> cb710_clock_divider_log2[divider_idx])
  42. break;
  43. }
  44. if (src_freq_idx)
  45. divider_idx |= 0x8;
  46. else if (divider_idx == 0)
  47. divider_idx = 1;
  48. cb710_pci_update_config_reg(pdev, 0x40, ~0xF0000000, divider_idx << 28);
  49. dev_dbg(cb710_slot_dev(slot),
  50. "clock set to %d Hz, wanted %d Hz; src_freq_idx = %d, divider_idx = %d|%d\n",
  51. src_hz >> cb710_clock_divider_log2[divider_idx & 7],
  52. hz, src_freq_idx, divider_idx & 7, divider_idx & 8);
  53. }
  54. static void __cb710_mmc_enable_irq(struct cb710_slot *slot,
  55. unsigned short enable, unsigned short mask)
  56. {
  57. /* clear global IE
  58. * - it gets set later if any interrupt sources are enabled */
  59. mask |= CB710_MMC_IE_IRQ_ENABLE;
  60. /* look like interrupt is fired whenever
  61. * WORD[0x0C] & WORD[0x10] != 0;
  62. * -> bit 15 port 0x0C seems to be global interrupt enable
  63. */
  64. enable = (cb710_read_port_16(slot, CB710_MMC_IRQ_ENABLE_PORT)
  65. & ~mask) | enable;
  66. if (enable)
  67. enable |= CB710_MMC_IE_IRQ_ENABLE;
  68. cb710_write_port_16(slot, CB710_MMC_IRQ_ENABLE_PORT, enable);
  69. }
  70. static void cb710_mmc_enable_irq(struct cb710_slot *slot,
  71. unsigned short enable, unsigned short mask)
  72. {
  73. struct cb710_mmc_reader *reader = mmc_priv(cb710_slot_to_mmc(slot));
  74. unsigned long flags;
  75. spin_lock_irqsave(&reader->irq_lock, flags);
  76. /* this is the only thing irq_lock protects */
  77. __cb710_mmc_enable_irq(slot, enable, mask);
  78. spin_unlock_irqrestore(&reader->irq_lock, flags);
  79. }
  80. static void cb710_mmc_reset_events(struct cb710_slot *slot)
  81. {
  82. cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, 0xFF);
  83. cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, 0xFF);
  84. cb710_write_port_8(slot, CB710_MMC_STATUS2_PORT, 0xFF);
  85. }
  86. static int cb710_mmc_is_card_inserted(struct cb710_slot *slot)
  87. {
  88. return cb710_read_port_8(slot, CB710_MMC_STATUS3_PORT)
  89. & CB710_MMC_S3_CARD_DETECTED;
  90. }
  91. static void cb710_mmc_enable_4bit_data(struct cb710_slot *slot, int enable)
  92. {
  93. dev_dbg(cb710_slot_dev(slot), "configuring %d-data-line%s mode\n",
  94. enable ? 4 : 1, enable ? "s" : "");
  95. if (enable)
  96. cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT,
  97. CB710_MMC_C1_4BIT_DATA_BUS, 0);
  98. else
  99. cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT,
  100. 0, CB710_MMC_C1_4BIT_DATA_BUS);
  101. }
  102. static int cb710_check_event(struct cb710_slot *slot, u8 what)
  103. {
  104. u16 status;
  105. status = cb710_read_port_16(slot, CB710_MMC_STATUS_PORT);
  106. if (status & CB710_MMC_S0_FIFO_UNDERFLOW) {
  107. /* it is just a guess, so log it */
  108. dev_dbg(cb710_slot_dev(slot),
  109. "CHECK : ignoring bit 6 in status %04X\n", status);
  110. cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT,
  111. CB710_MMC_S0_FIFO_UNDERFLOW);
  112. status &= ~CB710_MMC_S0_FIFO_UNDERFLOW;
  113. }
  114. if (status & CB710_MMC_STATUS_ERROR_EVENTS) {
  115. dev_dbg(cb710_slot_dev(slot),
  116. "CHECK : returning EIO on status %04X\n", status);
  117. cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, status & 0xFF);
  118. cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT,
  119. CB710_MMC_S1_RESET);
  120. return -EIO;
  121. }
  122. /* 'what' is a bit in MMC_STATUS1 */
  123. if ((status >> 8) & what) {
  124. cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, what);
  125. return 1;
  126. }
  127. return 0;
  128. }
  129. static int cb710_wait_for_event(struct cb710_slot *slot, u8 what)
  130. {
  131. int err = 0;
  132. unsigned limit = 2000000; /* FIXME: real timeout */
  133. #ifdef CONFIG_CB710_DEBUG
  134. u32 e, x;
  135. e = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
  136. #endif
  137. while (!(err = cb710_check_event(slot, what))) {
  138. if (!--limit) {
  139. cb710_dump_regs(cb710_slot_to_chip(slot),
  140. CB710_DUMP_REGS_MMC);
  141. err = -ETIMEDOUT;
  142. break;
  143. }
  144. udelay(1);
  145. }
  146. #ifdef CONFIG_CB710_DEBUG
  147. x = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
  148. limit = 2000000 - limit;
  149. if (limit > 100)
  150. dev_dbg(cb710_slot_dev(slot),
  151. "WAIT10: waited %d loops, what %d, entry val %08X, exit val %08X\n",
  152. limit, what, e, x);
  153. #endif
  154. return err < 0 ? err : 0;
  155. }
  156. static int cb710_wait_while_busy(struct cb710_slot *slot, uint8_t mask)
  157. {
  158. unsigned limit = 500000; /* FIXME: real timeout */
  159. int err = 0;
  160. #ifdef CONFIG_CB710_DEBUG
  161. u32 e, x;
  162. e = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
  163. #endif
  164. while (cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & mask) {
  165. if (!--limit) {
  166. cb710_dump_regs(cb710_slot_to_chip(slot),
  167. CB710_DUMP_REGS_MMC);
  168. err = -ETIMEDOUT;
  169. break;
  170. }
  171. udelay(1);
  172. }
  173. #ifdef CONFIG_CB710_DEBUG
  174. x = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
  175. limit = 500000 - limit;
  176. if (limit > 100)
  177. dev_dbg(cb710_slot_dev(slot),
  178. "WAIT12: waited %d loops, mask %02X, entry val %08X, exit val %08X\n",
  179. limit, mask, e, x);
  180. #endif
  181. return 0;
  182. }
  183. static void cb710_mmc_set_transfer_size(struct cb710_slot *slot,
  184. size_t count, size_t blocksize)
  185. {
  186. cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
  187. cb710_write_port_32(slot, CB710_MMC_TRANSFER_SIZE_PORT,
  188. ((count - 1) << 16)|(blocksize - 1));
  189. dev_vdbg(cb710_slot_dev(slot), "set up for %zu block%s of %zu bytes\n",
  190. count, count == 1 ? "" : "s", blocksize);
  191. }
  192. static void cb710_mmc_fifo_hack(struct cb710_slot *slot)
  193. {
  194. /* without this, received data is prepended with 8-bytes of zeroes */
  195. u32 r1, r2;
  196. int ok = 0;
  197. r1 = cb710_read_port_32(slot, CB710_MMC_DATA_PORT);
  198. r2 = cb710_read_port_32(slot, CB710_MMC_DATA_PORT);
  199. if (cb710_read_port_8(slot, CB710_MMC_STATUS0_PORT)
  200. & CB710_MMC_S0_FIFO_UNDERFLOW) {
  201. cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT,
  202. CB710_MMC_S0_FIFO_UNDERFLOW);
  203. ok = 1;
  204. }
  205. dev_dbg(cb710_slot_dev(slot),
  206. "FIFO-read-hack: expected STATUS0 bit was %s\n",
  207. ok ? "set." : "NOT SET!");
  208. dev_dbg(cb710_slot_dev(slot),
  209. "FIFO-read-hack: dwords ignored: %08X %08X - %s\n",
  210. r1, r2, (r1|r2) ? "BAD (NOT ZERO)!" : "ok");
  211. }
  212. static int cb710_mmc_receive_pio(struct cb710_slot *slot,
  213. struct sg_mapping_iter *miter, size_t dw_count)
  214. {
  215. if (!(cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & CB710_MMC_S2_FIFO_READY)) {
  216. int err = cb710_wait_for_event(slot,
  217. CB710_MMC_S1_PIO_TRANSFER_DONE);
  218. if (err)
  219. return err;
  220. }
  221. cb710_sg_dwiter_write_from_io(miter,
  222. slot->iobase + CB710_MMC_DATA_PORT, dw_count);
  223. return 0;
  224. }
  225. static bool cb710_is_transfer_size_supported(struct mmc_data *data)
  226. {
  227. return !(data->blksz & 15 && (data->blocks != 1 || data->blksz != 8));
  228. }
  229. static int cb710_mmc_receive(struct cb710_slot *slot, struct mmc_data *data)
  230. {
  231. struct sg_mapping_iter miter;
  232. size_t len, blocks = data->blocks;
  233. int err = 0;
  234. /* TODO: I don't know how/if the hardware handles non-16B-boundary blocks
  235. * except single 8B block */
  236. if (unlikely(data->blksz & 15 && (data->blocks != 1 || data->blksz != 8)))
  237. return -EINVAL;
  238. sg_miter_start(&miter, data->sg, data->sg_len, SG_MITER_TO_SG);
  239. cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
  240. 15, CB710_MMC_C2_READ_PIO_SIZE_MASK);
  241. cb710_mmc_fifo_hack(slot);
  242. while (blocks-- > 0) {
  243. len = data->blksz;
  244. while (len >= 16) {
  245. err = cb710_mmc_receive_pio(slot, &miter, 4);
  246. if (err)
  247. goto out;
  248. len -= 16;
  249. }
  250. if (!len)
  251. continue;
  252. cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
  253. len - 1, CB710_MMC_C2_READ_PIO_SIZE_MASK);
  254. len = (len >= 8) ? 4 : 2;
  255. err = cb710_mmc_receive_pio(slot, &miter, len);
  256. if (err)
  257. goto out;
  258. }
  259. out:
  260. sg_miter_stop(&miter);
  261. return err;
  262. }
  263. static int cb710_mmc_send(struct cb710_slot *slot, struct mmc_data *data)
  264. {
  265. struct sg_mapping_iter miter;
  266. size_t len, blocks = data->blocks;
  267. int err = 0;
  268. /* TODO: I don't know how/if the hardware handles multiple
  269. * non-16B-boundary blocks */
  270. if (unlikely(data->blocks > 1 && data->blksz & 15))
  271. return -EINVAL;
  272. sg_miter_start(&miter, data->sg, data->sg_len, SG_MITER_FROM_SG);
  273. cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
  274. 0, CB710_MMC_C2_READ_PIO_SIZE_MASK);
  275. while (blocks-- > 0) {
  276. len = (data->blksz + 15) >> 4;
  277. do {
  278. if (!(cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT)
  279. & CB710_MMC_S2_FIFO_EMPTY)) {
  280. err = cb710_wait_for_event(slot,
  281. CB710_MMC_S1_PIO_TRANSFER_DONE);
  282. if (err)
  283. goto out;
  284. }
  285. cb710_sg_dwiter_read_to_io(&miter,
  286. slot->iobase + CB710_MMC_DATA_PORT, 4);
  287. } while (--len);
  288. }
  289. out:
  290. sg_miter_stop(&miter);
  291. return err;
  292. }
  293. static u16 cb710_encode_cmd_flags(struct cb710_mmc_reader *reader,
  294. struct mmc_command *cmd)
  295. {
  296. unsigned int flags = cmd->flags;
  297. u16 cb_flags = 0;
  298. /* Windows driver returned 0 for commands for which no response
  299. * is expected. It happened that there were only two such commands
  300. * used: MMC_GO_IDLE_STATE and MMC_GO_INACTIVE_STATE so it might
  301. * as well be a bug in that driver.
  302. *
  303. * Original driver set bit 14 for MMC/SD application
  304. * commands. There's no difference 'on the wire' and
  305. * it apparently works without it anyway.
  306. */
  307. switch (flags & MMC_CMD_MASK) {
  308. case MMC_CMD_AC: cb_flags = CB710_MMC_CMD_AC; break;
  309. case MMC_CMD_ADTC: cb_flags = CB710_MMC_CMD_ADTC; break;
  310. case MMC_CMD_BC: cb_flags = CB710_MMC_CMD_BC; break;
  311. case MMC_CMD_BCR: cb_flags = CB710_MMC_CMD_BCR; break;
  312. }
  313. if (flags & MMC_RSP_BUSY)
  314. cb_flags |= CB710_MMC_RSP_BUSY;
  315. cb_flags |= cmd->opcode << CB710_MMC_CMD_CODE_SHIFT;
  316. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  317. cb_flags |= CB710_MMC_DATA_READ;
  318. if (flags & MMC_RSP_PRESENT) {
  319. /* Windows driver set 01 at bits 4,3 except for
  320. * MMC_SET_BLOCKLEN where it set 10. Maybe the
  321. * hardware can do something special about this
  322. * command? The original driver looks buggy/incomplete
  323. * anyway so we ignore this for now.
  324. *
  325. * I assume that 00 here means no response is expected.
  326. */
  327. cb_flags |= CB710_MMC_RSP_PRESENT;
  328. if (flags & MMC_RSP_136)
  329. cb_flags |= CB710_MMC_RSP_136;
  330. if (!(flags & MMC_RSP_CRC))
  331. cb_flags |= CB710_MMC_RSP_NO_CRC;
  332. }
  333. return cb_flags;
  334. }
  335. static void cb710_receive_response(struct cb710_slot *slot,
  336. struct mmc_command *cmd)
  337. {
  338. unsigned rsp_opcode, wanted_opcode;
  339. /* Looks like final byte with CRC is always stripped (same as SDHCI) */
  340. if (cmd->flags & MMC_RSP_136) {
  341. u32 resp[4];
  342. resp[0] = cb710_read_port_32(slot, CB710_MMC_RESPONSE3_PORT);
  343. resp[1] = cb710_read_port_32(slot, CB710_MMC_RESPONSE2_PORT);
  344. resp[2] = cb710_read_port_32(slot, CB710_MMC_RESPONSE1_PORT);
  345. resp[3] = cb710_read_port_32(slot, CB710_MMC_RESPONSE0_PORT);
  346. rsp_opcode = resp[0] >> 24;
  347. cmd->resp[0] = (resp[0] << 8)|(resp[1] >> 24);
  348. cmd->resp[1] = (resp[1] << 8)|(resp[2] >> 24);
  349. cmd->resp[2] = (resp[2] << 8)|(resp[3] >> 24);
  350. cmd->resp[3] = (resp[3] << 8);
  351. } else {
  352. rsp_opcode = cb710_read_port_32(slot, CB710_MMC_RESPONSE1_PORT) & 0x3F;
  353. cmd->resp[0] = cb710_read_port_32(slot, CB710_MMC_RESPONSE0_PORT);
  354. }
  355. wanted_opcode = (cmd->flags & MMC_RSP_OPCODE) ? cmd->opcode : 0x3F;
  356. if (rsp_opcode != wanted_opcode)
  357. cmd->error = -EILSEQ;
  358. }
  359. static int cb710_mmc_transfer_data(struct cb710_slot *slot,
  360. struct mmc_data *data)
  361. {
  362. int error, to;
  363. if (data->flags & MMC_DATA_READ)
  364. error = cb710_mmc_receive(slot, data);
  365. else
  366. error = cb710_mmc_send(slot, data);
  367. to = cb710_wait_for_event(slot, CB710_MMC_S1_DATA_TRANSFER_DONE);
  368. if (!error)
  369. error = to;
  370. if (!error)
  371. data->bytes_xfered = data->blksz * data->blocks;
  372. return error;
  373. }
  374. static int cb710_mmc_command(struct mmc_host *mmc, struct mmc_command *cmd)
  375. {
  376. struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
  377. struct cb710_mmc_reader *reader = mmc_priv(mmc);
  378. struct mmc_data *data = cmd->data;
  379. u16 cb_cmd = cb710_encode_cmd_flags(reader, cmd);
  380. dev_dbg(cb710_slot_dev(slot), "cmd request: 0x%04X\n", cb_cmd);
  381. if (data) {
  382. if (!cb710_is_transfer_size_supported(data)) {
  383. data->error = -EINVAL;
  384. return -1;
  385. }
  386. cb710_mmc_set_transfer_size(slot, data->blocks, data->blksz);
  387. }
  388. cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20|CB710_MMC_S2_BUSY_10);
  389. cb710_write_port_16(slot, CB710_MMC_CMD_TYPE_PORT, cb_cmd);
  390. cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
  391. cb710_write_port_32(slot, CB710_MMC_CMD_PARAM_PORT, cmd->arg);
  392. cb710_mmc_reset_events(slot);
  393. cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
  394. cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x01, 0);
  395. cmd->error = cb710_wait_for_event(slot, CB710_MMC_S1_COMMAND_SENT);
  396. if (cmd->error)
  397. return -1;
  398. if (cmd->flags & MMC_RSP_PRESENT) {
  399. cb710_receive_response(slot, cmd);
  400. if (cmd->error)
  401. return -1;
  402. }
  403. if (data)
  404. data->error = cb710_mmc_transfer_data(slot, data);
  405. return 0;
  406. }
  407. static void cb710_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  408. {
  409. struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
  410. struct cb710_mmc_reader *reader = mmc_priv(mmc);
  411. WARN_ON(reader->mrq != NULL);
  412. reader->mrq = mrq;
  413. cb710_mmc_enable_irq(slot, CB710_MMC_IE_TEST_MASK, 0);
  414. if (cb710_mmc_is_card_inserted(slot)) {
  415. if (!cb710_mmc_command(mmc, mrq->cmd) && mrq->stop)
  416. cb710_mmc_command(mmc, mrq->stop);
  417. mdelay(1);
  418. } else {
  419. mrq->cmd->error = -ENOMEDIUM;
  420. }
  421. tasklet_schedule(&reader->finish_req_tasklet);
  422. }
  423. static int cb710_mmc_powerup(struct cb710_slot *slot)
  424. {
  425. #ifdef CONFIG_CB710_DEBUG
  426. struct cb710_chip *chip = cb710_slot_to_chip(slot);
  427. #endif
  428. int err;
  429. /* a lot of magic for now */
  430. dev_dbg(cb710_slot_dev(slot), "bus powerup\n");
  431. cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
  432. err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
  433. if (unlikely(err))
  434. return err;
  435. cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x80, 0);
  436. cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0x80, 0);
  437. cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
  438. mdelay(1);
  439. dev_dbg(cb710_slot_dev(slot), "after delay 1\n");
  440. cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
  441. err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
  442. if (unlikely(err))
  443. return err;
  444. cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x09, 0);
  445. cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
  446. mdelay(1);
  447. dev_dbg(cb710_slot_dev(slot), "after delay 2\n");
  448. cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
  449. err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
  450. if (unlikely(err))
  451. return err;
  452. cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0, 0x08);
  453. cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
  454. mdelay(2);
  455. dev_dbg(cb710_slot_dev(slot), "after delay 3\n");
  456. cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
  457. cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x06, 0);
  458. cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x70, 0);
  459. cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT, 0x80, 0);
  460. cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0x03, 0);
  461. cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
  462. err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
  463. if (unlikely(err))
  464. return err;
  465. /* This port behaves weird: quick byte reads of 0x08,0x09 return
  466. * 0xFF,0x00 after writing 0xFFFF to 0x08; it works correctly when
  467. * read/written from userspace... What am I missing here?
  468. * (it doesn't depend on write-to-read delay) */
  469. cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0xFFFF);
  470. cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x06, 0);
  471. cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
  472. dev_dbg(cb710_slot_dev(slot), "bus powerup finished\n");
  473. return cb710_check_event(slot, 0);
  474. }
  475. static void cb710_mmc_powerdown(struct cb710_slot *slot)
  476. {
  477. cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0, 0x81);
  478. cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0, 0x80);
  479. }
  480. static void cb710_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  481. {
  482. struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
  483. struct cb710_mmc_reader *reader = mmc_priv(mmc);
  484. int err;
  485. cb710_mmc_select_clock_divider(mmc, ios->clock);
  486. if (!cb710_mmc_is_card_inserted(slot)) {
  487. dev_dbg(cb710_slot_dev(slot),
  488. "no card inserted - ignoring bus powerup request\n");
  489. ios->power_mode = MMC_POWER_OFF;
  490. }
  491. if (ios->power_mode != reader->last_power_mode)
  492. switch (ios->power_mode) {
  493. case MMC_POWER_ON:
  494. err = cb710_mmc_powerup(slot);
  495. if (err) {
  496. dev_warn(cb710_slot_dev(slot),
  497. "powerup failed (%d)- retrying\n", err);
  498. cb710_mmc_powerdown(slot);
  499. udelay(1);
  500. err = cb710_mmc_powerup(slot);
  501. if (err)
  502. dev_warn(cb710_slot_dev(slot),
  503. "powerup retry failed (%d) - expect errors\n",
  504. err);
  505. }
  506. reader->last_power_mode = MMC_POWER_ON;
  507. break;
  508. case MMC_POWER_OFF:
  509. cb710_mmc_powerdown(slot);
  510. reader->last_power_mode = MMC_POWER_OFF;
  511. break;
  512. case MMC_POWER_UP:
  513. default:
  514. /* ignore */;
  515. }
  516. cb710_mmc_enable_4bit_data(slot, ios->bus_width != MMC_BUS_WIDTH_1);
  517. cb710_mmc_enable_irq(slot, CB710_MMC_IE_TEST_MASK, 0);
  518. }
  519. static int cb710_mmc_get_ro(struct mmc_host *mmc)
  520. {
  521. struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
  522. return cb710_read_port_8(slot, CB710_MMC_STATUS3_PORT)
  523. & CB710_MMC_S3_WRITE_PROTECTED;
  524. }
  525. static int cb710_mmc_irq_handler(struct cb710_slot *slot)
  526. {
  527. struct mmc_host *mmc = cb710_slot_to_mmc(slot);
  528. struct cb710_mmc_reader *reader = mmc_priv(mmc);
  529. u32 status, config1, config2, irqen;
  530. status = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
  531. irqen = cb710_read_port_32(slot, CB710_MMC_IRQ_ENABLE_PORT);
  532. config2 = cb710_read_port_32(slot, CB710_MMC_CONFIGB_PORT);
  533. config1 = cb710_read_port_32(slot, CB710_MMC_CONFIG_PORT);
  534. dev_dbg(cb710_slot_dev(slot), "interrupt; status: %08X, "
  535. "ie: %08X, c2: %08X, c1: %08X\n",
  536. status, irqen, config2, config1);
  537. if (status & (CB710_MMC_S1_CARD_CHANGED << 8)) {
  538. /* ack the event */
  539. cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT,
  540. CB710_MMC_S1_CARD_CHANGED);
  541. if ((irqen & CB710_MMC_IE_CISTATUS_MASK)
  542. == CB710_MMC_IE_CISTATUS_MASK)
  543. mmc_detect_change(mmc, HZ/5);
  544. } else {
  545. dev_dbg(cb710_slot_dev(slot), "unknown interrupt (test)\n");
  546. spin_lock(&reader->irq_lock);
  547. __cb710_mmc_enable_irq(slot, 0, CB710_MMC_IE_TEST_MASK);
  548. spin_unlock(&reader->irq_lock);
  549. }
  550. return 1;
  551. }
  552. static void cb710_mmc_finish_request_tasklet(unsigned long data)
  553. {
  554. struct mmc_host *mmc = (void *)data;
  555. struct cb710_mmc_reader *reader = mmc_priv(mmc);
  556. struct mmc_request *mrq = reader->mrq;
  557. reader->mrq = NULL;
  558. mmc_request_done(mmc, mrq);
  559. }
  560. static const struct mmc_host_ops cb710_mmc_host = {
  561. .request = cb710_mmc_request,
  562. .set_ios = cb710_mmc_set_ios,
  563. .get_ro = cb710_mmc_get_ro
  564. };
  565. #ifdef CONFIG_PM
  566. static int cb710_mmc_suspend(struct platform_device *pdev, pm_message_t state)
  567. {
  568. struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
  569. struct mmc_host *mmc = cb710_slot_to_mmc(slot);
  570. int err;
  571. err = mmc_suspend_host(mmc);
  572. if (err)
  573. return err;
  574. cb710_mmc_enable_irq(slot, 0, ~0);
  575. return 0;
  576. }
  577. static int cb710_mmc_resume(struct platform_device *pdev)
  578. {
  579. struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
  580. struct mmc_host *mmc = cb710_slot_to_mmc(slot);
  581. cb710_mmc_enable_irq(slot, 0, ~0);
  582. return mmc_resume_host(mmc);
  583. }
  584. #endif /* CONFIG_PM */
  585. static int __devinit cb710_mmc_init(struct platform_device *pdev)
  586. {
  587. struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
  588. struct cb710_chip *chip = cb710_slot_to_chip(slot);
  589. struct mmc_host *mmc;
  590. struct cb710_mmc_reader *reader;
  591. int err;
  592. u32 val;
  593. mmc = mmc_alloc_host(sizeof(*reader), cb710_slot_dev(slot));
  594. if (!mmc)
  595. return -ENOMEM;
  596. dev_set_drvdata(&pdev->dev, mmc);
  597. /* harmless (maybe) magic */
  598. pci_read_config_dword(chip->pdev, 0x48, &val);
  599. val = cb710_src_freq_mhz[(val >> 16) & 0xF];
  600. dev_dbg(cb710_slot_dev(slot), "source frequency: %dMHz\n", val);
  601. val *= 1000000;
  602. mmc->ops = &cb710_mmc_host;
  603. mmc->f_max = val;
  604. mmc->f_min = val >> cb710_clock_divider_log2[CB710_MAX_DIVIDER_IDX];
  605. mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
  606. mmc->caps = MMC_CAP_4_BIT_DATA;
  607. reader = mmc_priv(mmc);
  608. tasklet_init(&reader->finish_req_tasklet,
  609. cb710_mmc_finish_request_tasklet, (unsigned long)mmc);
  610. spin_lock_init(&reader->irq_lock);
  611. cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
  612. cb710_mmc_enable_irq(slot, 0, ~0);
  613. cb710_set_irq_handler(slot, cb710_mmc_irq_handler);
  614. err = mmc_add_host(mmc);
  615. if (unlikely(err))
  616. goto err_free_mmc;
  617. dev_dbg(cb710_slot_dev(slot), "mmc_hostname is %s\n",
  618. mmc_hostname(mmc));
  619. cb710_mmc_enable_irq(slot, CB710_MMC_IE_CARD_INSERTION_STATUS, 0);
  620. return 0;
  621. err_free_mmc:
  622. dev_dbg(cb710_slot_dev(slot), "mmc_add_host() failed: %d\n", err);
  623. mmc_free_host(mmc);
  624. return err;
  625. }
  626. static int __devexit cb710_mmc_exit(struct platform_device *pdev)
  627. {
  628. struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
  629. struct mmc_host *mmc = cb710_slot_to_mmc(slot);
  630. struct cb710_mmc_reader *reader = mmc_priv(mmc);
  631. cb710_mmc_enable_irq(slot, 0, CB710_MMC_IE_CARD_INSERTION_STATUS);
  632. mmc_remove_host(mmc);
  633. /* IRQs should be disabled now, but let's stay on the safe side */
  634. cb710_mmc_enable_irq(slot, 0, ~0);
  635. cb710_set_irq_handler(slot, NULL);
  636. /* clear config ports - just in case */
  637. cb710_write_port_32(slot, CB710_MMC_CONFIG_PORT, 0);
  638. cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0);
  639. tasklet_kill(&reader->finish_req_tasklet);
  640. mmc_free_host(mmc);
  641. return 0;
  642. }
  643. static struct platform_driver cb710_mmc_driver = {
  644. .driver.name = "cb710-mmc",
  645. .probe = cb710_mmc_init,
  646. .remove = __devexit_p(cb710_mmc_exit),
  647. #ifdef CONFIG_PM
  648. .suspend = cb710_mmc_suspend,
  649. .resume = cb710_mmc_resume,
  650. #endif
  651. };
  652. static int __init cb710_mmc_init_module(void)
  653. {
  654. return platform_driver_register(&cb710_mmc_driver);
  655. }
  656. static void __exit cb710_mmc_cleanup_module(void)
  657. {
  658. platform_driver_unregister(&cb710_mmc_driver);
  659. }
  660. module_init(cb710_mmc_init_module);
  661. module_exit(cb710_mmc_cleanup_module);
  662. MODULE_AUTHOR("Michał Mirosław <mirq-linux@rere.qmqm.pl>");
  663. MODULE_DESCRIPTION("ENE CB710 memory card reader driver - MMC/SD part");
  664. MODULE_LICENSE("GPL");
  665. MODULE_ALIAS("platform:cb710-mmc");