exynos5440.dtsi 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181
  1. /*
  2. * SAMSUNG EXYNOS5440 SoC device tree source
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. compatible = "samsung,exynos5440";
  14. interrupt-parent = <&gic>;
  15. clock: clock-controller@0x160000 {
  16. compatible = "samsung,exynos5440-clock";
  17. reg = <0x160000 0x1000>;
  18. #clock-cells = <1>;
  19. };
  20. gic:interrupt-controller@2E0000 {
  21. compatible = "arm,cortex-a15-gic";
  22. #interrupt-cells = <3>;
  23. interrupt-controller;
  24. reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
  25. };
  26. cpus {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. cpu@0 {
  30. compatible = "arm,cortex-a15";
  31. reg = <0>;
  32. };
  33. cpu@1 {
  34. compatible = "arm,cortex-a15";
  35. reg = <1>;
  36. };
  37. cpu@2 {
  38. compatible = "arm,cortex-a15";
  39. reg = <2>;
  40. };
  41. cpu@3 {
  42. compatible = "arm,cortex-a15";
  43. reg = <3>;
  44. };
  45. };
  46. timer {
  47. compatible = "arm,cortex-a15-timer",
  48. "arm,armv7-timer";
  49. interrupts = <1 13 0xf08>,
  50. <1 14 0xf08>,
  51. <1 11 0xf08>,
  52. <1 10 0xf08>;
  53. clock-frequency = <50000000>;
  54. };
  55. serial@B0000 {
  56. compatible = "samsung,exynos4210-uart";
  57. reg = <0xB0000 0x1000>;
  58. interrupts = <0 2 0>;
  59. clocks = <&clock 21>, <&clock 21>;
  60. clock-names = "uart", "clk_uart_baud0";
  61. };
  62. serial@C0000 {
  63. compatible = "samsung,exynos4210-uart";
  64. reg = <0xC0000 0x1000>;
  65. interrupts = <0 3 0>;
  66. clocks = <&clock 21>, <&clock 21>;
  67. clock-names = "uart", "clk_uart_baud0";
  68. };
  69. spi {
  70. compatible = "samsung,exynos4210-spi";
  71. reg = <0xD0000 0x1000>;
  72. interrupts = <0 4 0>;
  73. tx-dma-channel = <&pdma0 5>; /* preliminary */
  74. rx-dma-channel = <&pdma0 4>; /* preliminary */
  75. #address-cells = <1>;
  76. #size-cells = <0>;
  77. clocks = <&clock 21>, <&clock 16>;
  78. clock-names = "spi", "spi_busclk0";
  79. };
  80. pinctrl {
  81. compatible = "samsung,exynos5440-pinctrl";
  82. reg = <0xE0000 0x1000>;
  83. interrupt-controller;
  84. #interrupt-cells = <2>;
  85. #gpio-cells = <2>;
  86. fan: fan {
  87. samsung,exynos5440-pin-function = <1>;
  88. };
  89. hdd_led0: hdd_led0 {
  90. samsung,exynos5440-pin-function = <2>;
  91. };
  92. hdd_led1: hdd_led1 {
  93. samsung,exynos5440-pin-function = <3>;
  94. };
  95. uart1: uart1 {
  96. samsung,exynos5440-pin-function = <4>;
  97. };
  98. };
  99. i2c@F0000 {
  100. compatible = "samsung,exynos5440-i2c";
  101. reg = <0xF0000 0x1000>;
  102. interrupts = <0 5 0>;
  103. #address-cells = <1>;
  104. #size-cells = <0>;
  105. clocks = <&clock 21>;
  106. clock-names = "i2c";
  107. };
  108. i2c@100000 {
  109. compatible = "samsung,exynos5440-i2c";
  110. reg = <0x100000 0x1000>;
  111. interrupts = <0 6 0>;
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. clocks = <&clock 21>;
  115. clock-names = "i2c";
  116. };
  117. watchdog {
  118. compatible = "samsung,s3c2410-wdt";
  119. reg = <0x110000 0x1000>;
  120. interrupts = <0 1 0>;
  121. clocks = <&clock 21>;
  122. clock-names = "watchdog";
  123. };
  124. amba {
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. compatible = "arm,amba-bus";
  128. interrupt-parent = <&gic>;
  129. ranges;
  130. pdma0: pdma@121A0000 {
  131. compatible = "arm,pl330", "arm,primecell";
  132. reg = <0x120000 0x1000>;
  133. interrupts = <0 34 0>;
  134. clocks = <&clock 21>;
  135. clock-names = "apb_pclk";
  136. #dma-cells = <1>;
  137. #dma-channels = <8>;
  138. #dma-requests = <32>;
  139. };
  140. pdma1: pdma@121B0000 {
  141. compatible = "arm,pl330", "arm,primecell";
  142. reg = <0x121000 0x1000>;
  143. interrupts = <0 35 0>;
  144. clocks = <&clock 21>;
  145. clock-names = "apb_pclk";
  146. #dma-cells = <1>;
  147. #dma-channels = <8>;
  148. #dma-requests = <32>;
  149. };
  150. };
  151. rtc {
  152. compatible = "samsung,s3c6410-rtc";
  153. reg = <0x130000 0x1000>;
  154. interrupts = <0 17 0>, <0 16 0>;
  155. clocks = <&clock 21>;
  156. clock-names = "rtc";
  157. };
  158. };