iwl-agn.c 82 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. /* allow CTS-to-self if possible. this is relevant only for
  101. * 5000, but will not damage 4965 */
  102. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  103. ret = iwl_check_rxon_cmd(priv);
  104. if (ret) {
  105. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  106. return -EINVAL;
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. return 0;
  119. }
  120. /* station table will be cleared */
  121. priv->assoc_station_added = 0;
  122. /* If we are currently associated and the new config requires
  123. * an RXON_ASSOC and the new config wants the associated mask enabled,
  124. * we must clear the associated from the active configuration
  125. * before we apply the new config */
  126. if (iwl_is_associated(priv) && new_assoc) {
  127. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  128. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  129. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  130. sizeof(struct iwl_rxon_cmd),
  131. &priv->active_rxon);
  132. /* If the mask clearing failed then we set
  133. * active_rxon back to what it was previously */
  134. if (ret) {
  135. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  136. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  137. return ret;
  138. }
  139. }
  140. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  141. "* with%s RXON_FILTER_ASSOC_MSK\n"
  142. "* channel = %d\n"
  143. "* bssid = %pM\n",
  144. (new_assoc ? "" : "out"),
  145. le16_to_cpu(priv->staging_rxon.channel),
  146. priv->staging_rxon.bssid_addr);
  147. iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
  148. /* Apply the new configuration
  149. * RXON unassoc clears the station table in uCode, send it before
  150. * we add the bcast station. If assoc bit is set, we will send RXON
  151. * after having added the bcast and bssid station.
  152. */
  153. if (!new_assoc) {
  154. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  155. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  156. if (ret) {
  157. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  158. return ret;
  159. }
  160. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  161. }
  162. priv->cfg->ops->smgmt->clear_station_table(priv);
  163. priv->start_calib = 0;
  164. /* Add the broadcast address so we can send broadcast frames */
  165. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  166. IWL_INVALID_STATION) {
  167. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  168. return -EIO;
  169. }
  170. /* If we have set the ASSOC_MSK and we are in BSS mode then
  171. * add the IWL_AP_ID to the station rate table */
  172. if (new_assoc) {
  173. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  174. ret = iwl_rxon_add_station(priv,
  175. priv->active_rxon.bssid_addr, 1);
  176. if (ret == IWL_INVALID_STATION) {
  177. IWL_ERR(priv,
  178. "Error adding AP address for TX.\n");
  179. return -EIO;
  180. }
  181. priv->assoc_station_added = 1;
  182. if (priv->default_wep_key &&
  183. iwl_send_static_wepkey_cmd(priv, 0))
  184. IWL_ERR(priv,
  185. "Could not send WEP static key.\n");
  186. }
  187. /* Apply the new configuration
  188. * RXON assoc doesn't clear the station table in uCode,
  189. */
  190. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  191. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  192. if (ret) {
  193. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  194. return ret;
  195. }
  196. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  197. }
  198. iwl_init_sensitivity(priv);
  199. /* If we issue a new RXON command which required a tune then we must
  200. * send a new TXPOWER command or we won't be able to Tx any frames */
  201. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  202. if (ret) {
  203. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  204. return ret;
  205. }
  206. return 0;
  207. }
  208. void iwl_update_chain_flags(struct iwl_priv *priv)
  209. {
  210. if (priv->cfg->ops->hcmd->set_rxon_chain)
  211. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  212. iwlcore_commit_rxon(priv);
  213. }
  214. static void iwl_clear_free_frames(struct iwl_priv *priv)
  215. {
  216. struct list_head *element;
  217. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  218. priv->frames_count);
  219. while (!list_empty(&priv->free_frames)) {
  220. element = priv->free_frames.next;
  221. list_del(element);
  222. kfree(list_entry(element, struct iwl_frame, list));
  223. priv->frames_count--;
  224. }
  225. if (priv->frames_count) {
  226. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  227. priv->frames_count);
  228. priv->frames_count = 0;
  229. }
  230. }
  231. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  232. {
  233. struct iwl_frame *frame;
  234. struct list_head *element;
  235. if (list_empty(&priv->free_frames)) {
  236. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  237. if (!frame) {
  238. IWL_ERR(priv, "Could not allocate frame!\n");
  239. return NULL;
  240. }
  241. priv->frames_count++;
  242. return frame;
  243. }
  244. element = priv->free_frames.next;
  245. list_del(element);
  246. return list_entry(element, struct iwl_frame, list);
  247. }
  248. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  249. {
  250. memset(frame, 0, sizeof(*frame));
  251. list_add(&frame->list, &priv->free_frames);
  252. }
  253. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  254. struct ieee80211_hdr *hdr,
  255. int left)
  256. {
  257. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  258. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  259. (priv->iw_mode != NL80211_IFTYPE_AP)))
  260. return 0;
  261. if (priv->ibss_beacon->len > left)
  262. return 0;
  263. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  264. return priv->ibss_beacon->len;
  265. }
  266. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  267. struct iwl_frame *frame, u8 rate)
  268. {
  269. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  270. unsigned int frame_size;
  271. tx_beacon_cmd = &frame->u.beacon;
  272. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  273. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  274. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  275. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  276. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  277. BUG_ON(frame_size > MAX_MPDU_SIZE);
  278. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  279. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  280. tx_beacon_cmd->tx.rate_n_flags =
  281. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  282. else
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, 0);
  285. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  286. TX_CMD_FLG_TSF_MSK |
  287. TX_CMD_FLG_STA_RATE_MSK;
  288. return sizeof(*tx_beacon_cmd) + frame_size;
  289. }
  290. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  291. {
  292. struct iwl_frame *frame;
  293. unsigned int frame_size;
  294. int rc;
  295. u8 rate;
  296. frame = iwl_get_free_frame(priv);
  297. if (!frame) {
  298. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  299. "command.\n");
  300. return -ENOMEM;
  301. }
  302. rate = iwl_rate_get_lowest_plcp(priv);
  303. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  304. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  305. &frame->u.cmd[0]);
  306. iwl_free_frame(priv, frame);
  307. return rc;
  308. }
  309. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  310. {
  311. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  312. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  313. if (sizeof(dma_addr_t) > sizeof(u32))
  314. addr |=
  315. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  316. return addr;
  317. }
  318. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  319. {
  320. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  321. return le16_to_cpu(tb->hi_n_len) >> 4;
  322. }
  323. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  324. dma_addr_t addr, u16 len)
  325. {
  326. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  327. u16 hi_n_len = len << 4;
  328. put_unaligned_le32(addr, &tb->lo);
  329. if (sizeof(dma_addr_t) > sizeof(u32))
  330. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  331. tb->hi_n_len = cpu_to_le16(hi_n_len);
  332. tfd->num_tbs = idx + 1;
  333. }
  334. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  335. {
  336. return tfd->num_tbs & 0x1f;
  337. }
  338. /**
  339. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  340. * @priv - driver private data
  341. * @txq - tx queue
  342. *
  343. * Does NOT advance any TFD circular buffer read/write indexes
  344. * Does NOT free the TFD itself (which is within circular buffer)
  345. */
  346. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  347. {
  348. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  349. struct iwl_tfd *tfd;
  350. struct pci_dev *dev = priv->pci_dev;
  351. int index = txq->q.read_ptr;
  352. int i;
  353. int num_tbs;
  354. tfd = &tfd_tmp[index];
  355. /* Sanity check on number of chunks */
  356. num_tbs = iwl_tfd_get_num_tbs(tfd);
  357. if (num_tbs >= IWL_NUM_OF_TBS) {
  358. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  359. /* @todo issue fatal error, it is quite serious situation */
  360. return;
  361. }
  362. /* Unmap tx_cmd */
  363. if (num_tbs)
  364. pci_unmap_single(dev,
  365. pci_unmap_addr(&txq->cmd[index]->meta, mapping),
  366. pci_unmap_len(&txq->cmd[index]->meta, len),
  367. PCI_DMA_BIDIRECTIONAL);
  368. /* Unmap chunks, if any. */
  369. for (i = 1; i < num_tbs; i++) {
  370. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  371. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  372. if (txq->txb) {
  373. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  374. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  375. }
  376. }
  377. }
  378. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  379. struct iwl_tx_queue *txq,
  380. dma_addr_t addr, u16 len,
  381. u8 reset, u8 pad)
  382. {
  383. struct iwl_queue *q;
  384. struct iwl_tfd *tfd, *tfd_tmp;
  385. u32 num_tbs;
  386. q = &txq->q;
  387. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  388. tfd = &tfd_tmp[q->write_ptr];
  389. if (reset)
  390. memset(tfd, 0, sizeof(*tfd));
  391. num_tbs = iwl_tfd_get_num_tbs(tfd);
  392. /* Each TFD can point to a maximum 20 Tx buffers */
  393. if (num_tbs >= IWL_NUM_OF_TBS) {
  394. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  395. IWL_NUM_OF_TBS);
  396. return -EINVAL;
  397. }
  398. BUG_ON(addr & ~DMA_BIT_MASK(36));
  399. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  400. IWL_ERR(priv, "Unaligned address = %llx\n",
  401. (unsigned long long)addr);
  402. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  403. return 0;
  404. }
  405. /*
  406. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  407. * given Tx queue, and enable the DMA channel used for that queue.
  408. *
  409. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  410. * channels supported in hardware.
  411. */
  412. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  413. struct iwl_tx_queue *txq)
  414. {
  415. int ret;
  416. unsigned long flags;
  417. int txq_id = txq->q.id;
  418. spin_lock_irqsave(&priv->lock, flags);
  419. ret = iwl_grab_nic_access(priv);
  420. if (ret) {
  421. spin_unlock_irqrestore(&priv->lock, flags);
  422. return ret;
  423. }
  424. /* Circular buffer (TFD queue in DRAM) physical base address */
  425. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  426. txq->q.dma_addr >> 8);
  427. iwl_release_nic_access(priv);
  428. spin_unlock_irqrestore(&priv->lock, flags);
  429. return 0;
  430. }
  431. /******************************************************************************
  432. *
  433. * Misc. internal state and helper functions
  434. *
  435. ******************************************************************************/
  436. #define MAX_UCODE_BEACON_INTERVAL 4096
  437. static u16 iwl_adjust_beacon_interval(u16 beacon_val)
  438. {
  439. u16 new_val = 0;
  440. u16 beacon_factor = 0;
  441. beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  442. / MAX_UCODE_BEACON_INTERVAL;
  443. new_val = beacon_val / beacon_factor;
  444. if (!new_val)
  445. new_val = MAX_UCODE_BEACON_INTERVAL;
  446. return new_val;
  447. }
  448. static void iwl_setup_rxon_timing(struct iwl_priv *priv)
  449. {
  450. u64 tsf;
  451. s32 interval_tm, rem;
  452. unsigned long flags;
  453. struct ieee80211_conf *conf = NULL;
  454. u16 beacon_int = 0;
  455. conf = ieee80211_get_hw_conf(priv->hw);
  456. spin_lock_irqsave(&priv->lock, flags);
  457. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  458. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  459. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  460. beacon_int = iwl_adjust_beacon_interval(priv->beacon_int);
  461. priv->rxon_timing.atim_window = 0;
  462. } else {
  463. beacon_int = iwl_adjust_beacon_interval(
  464. priv->vif->bss_conf.beacon_int);
  465. /* TODO: we need to get atim_window from upper stack
  466. * for now we set to 0 */
  467. priv->rxon_timing.atim_window = 0;
  468. }
  469. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  470. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  471. interval_tm = beacon_int * 1024;
  472. rem = do_div(tsf, interval_tm);
  473. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  474. spin_unlock_irqrestore(&priv->lock, flags);
  475. IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n",
  476. le16_to_cpu(priv->rxon_timing.beacon_interval),
  477. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  478. le16_to_cpu(priv->rxon_timing.atim_window));
  479. }
  480. /******************************************************************************
  481. *
  482. * Generic RX handler implementations
  483. *
  484. ******************************************************************************/
  485. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  486. struct iwl_rx_mem_buffer *rxb)
  487. {
  488. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  489. struct iwl_alive_resp *palive;
  490. struct delayed_work *pwork;
  491. palive = &pkt->u.alive_frame;
  492. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  493. "0x%01X 0x%01X\n",
  494. palive->is_valid, palive->ver_type,
  495. palive->ver_subtype);
  496. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  497. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  498. memcpy(&priv->card_alive_init,
  499. &pkt->u.alive_frame,
  500. sizeof(struct iwl_init_alive_resp));
  501. pwork = &priv->init_alive_start;
  502. } else {
  503. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  504. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  505. sizeof(struct iwl_alive_resp));
  506. pwork = &priv->alive_start;
  507. }
  508. /* We delay the ALIVE response by 5ms to
  509. * give the HW RF Kill time to activate... */
  510. if (palive->is_valid == UCODE_VALID_OK)
  511. queue_delayed_work(priv->workqueue, pwork,
  512. msecs_to_jiffies(5));
  513. else
  514. IWL_WARN(priv, "uCode did not respond OK.\n");
  515. }
  516. static void iwl_bg_beacon_update(struct work_struct *work)
  517. {
  518. struct iwl_priv *priv =
  519. container_of(work, struct iwl_priv, beacon_update);
  520. struct sk_buff *beacon;
  521. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  522. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  523. if (!beacon) {
  524. IWL_ERR(priv, "update beacon failed\n");
  525. return;
  526. }
  527. mutex_lock(&priv->mutex);
  528. /* new beacon skb is allocated every time; dispose previous.*/
  529. if (priv->ibss_beacon)
  530. dev_kfree_skb(priv->ibss_beacon);
  531. priv->ibss_beacon = beacon;
  532. mutex_unlock(&priv->mutex);
  533. iwl_send_beacon_cmd(priv);
  534. }
  535. /**
  536. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  537. *
  538. * This callback is provided in order to send a statistics request.
  539. *
  540. * This timer function is continually reset to execute within
  541. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  542. * was received. We need to ensure we receive the statistics in order
  543. * to update the temperature used for calibrating the TXPOWER.
  544. */
  545. static void iwl_bg_statistics_periodic(unsigned long data)
  546. {
  547. struct iwl_priv *priv = (struct iwl_priv *)data;
  548. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  549. return;
  550. /* dont send host command if rf-kill is on */
  551. if (!iwl_is_ready_rf(priv))
  552. return;
  553. iwl_send_statistics_request(priv, CMD_ASYNC);
  554. }
  555. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  556. struct iwl_rx_mem_buffer *rxb)
  557. {
  558. #ifdef CONFIG_IWLWIFI_DEBUG
  559. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  560. struct iwl4965_beacon_notif *beacon =
  561. (struct iwl4965_beacon_notif *)pkt->u.raw;
  562. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  563. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  564. "tsf %d %d rate %d\n",
  565. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  566. beacon->beacon_notify_hdr.failure_frame,
  567. le32_to_cpu(beacon->ibss_mgr_status),
  568. le32_to_cpu(beacon->high_tsf),
  569. le32_to_cpu(beacon->low_tsf), rate);
  570. #endif
  571. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  572. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  573. queue_work(priv->workqueue, &priv->beacon_update);
  574. }
  575. /* Handle notification from uCode that card's power state is changing
  576. * due to software, hardware, or critical temperature RFKILL */
  577. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  578. struct iwl_rx_mem_buffer *rxb)
  579. {
  580. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  581. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  582. unsigned long status = priv->status;
  583. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  584. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  585. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  586. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  587. RF_CARD_DISABLED)) {
  588. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  589. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  590. if (!iwl_grab_nic_access(priv)) {
  591. iwl_write_direct32(
  592. priv, HBUS_TARG_MBX_C,
  593. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  594. iwl_release_nic_access(priv);
  595. }
  596. if (!(flags & RXON_CARD_DISABLED)) {
  597. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  598. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  599. if (!iwl_grab_nic_access(priv)) {
  600. iwl_write_direct32(
  601. priv, HBUS_TARG_MBX_C,
  602. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  603. iwl_release_nic_access(priv);
  604. }
  605. }
  606. if (flags & RF_CARD_DISABLED) {
  607. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  608. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  609. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  610. if (!iwl_grab_nic_access(priv))
  611. iwl_release_nic_access(priv);
  612. }
  613. }
  614. if (flags & HW_CARD_DISABLED)
  615. set_bit(STATUS_RF_KILL_HW, &priv->status);
  616. else
  617. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  618. if (flags & SW_CARD_DISABLED)
  619. set_bit(STATUS_RF_KILL_SW, &priv->status);
  620. else
  621. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  622. if (!(flags & RXON_CARD_DISABLED))
  623. iwl_scan_cancel(priv);
  624. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  625. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  626. (test_bit(STATUS_RF_KILL_SW, &status) !=
  627. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  628. queue_work(priv->workqueue, &priv->rf_kill);
  629. else
  630. wake_up_interruptible(&priv->wait_command_queue);
  631. }
  632. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  633. {
  634. int ret;
  635. unsigned long flags;
  636. spin_lock_irqsave(&priv->lock, flags);
  637. ret = iwl_grab_nic_access(priv);
  638. if (ret)
  639. goto err;
  640. if (src == IWL_PWR_SRC_VAUX) {
  641. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  642. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  643. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  644. ~APMG_PS_CTRL_MSK_PWR_SRC);
  645. } else {
  646. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  647. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  648. ~APMG_PS_CTRL_MSK_PWR_SRC);
  649. }
  650. iwl_release_nic_access(priv);
  651. err:
  652. spin_unlock_irqrestore(&priv->lock, flags);
  653. return ret;
  654. }
  655. /**
  656. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  657. *
  658. * Setup the RX handlers for each of the reply types sent from the uCode
  659. * to the host.
  660. *
  661. * This function chains into the hardware specific files for them to setup
  662. * any hardware specific handlers as well.
  663. */
  664. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  665. {
  666. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  667. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  668. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  669. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  670. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  671. iwl_rx_pm_debug_statistics_notif;
  672. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  673. /*
  674. * The same handler is used for both the REPLY to a discrete
  675. * statistics request from the host as well as for the periodic
  676. * statistics notifications (after received beacons) from the uCode.
  677. */
  678. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  679. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  680. iwl_setup_spectrum_handlers(priv);
  681. iwl_setup_rx_scan_handlers(priv);
  682. /* status change handler */
  683. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  684. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  685. iwl_rx_missed_beacon_notif;
  686. /* Rx handlers */
  687. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  688. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  689. /* block ack */
  690. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  691. /* Set up hardware specific Rx handlers */
  692. priv->cfg->ops->lib->rx_handler_setup(priv);
  693. }
  694. /**
  695. * iwl_rx_handle - Main entry function for receiving responses from uCode
  696. *
  697. * Uses the priv->rx_handlers callback function array to invoke
  698. * the appropriate handlers, including command responses,
  699. * frame-received notifications, and other notifications.
  700. */
  701. void iwl_rx_handle(struct iwl_priv *priv)
  702. {
  703. struct iwl_rx_mem_buffer *rxb;
  704. struct iwl_rx_packet *pkt;
  705. struct iwl_rx_queue *rxq = &priv->rxq;
  706. u32 r, i;
  707. int reclaim;
  708. unsigned long flags;
  709. u8 fill_rx = 0;
  710. u32 count = 8;
  711. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  712. * buffer that the driver may process (last buffer filled by ucode). */
  713. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  714. i = rxq->read;
  715. /* Rx interrupt, but nothing sent from uCode */
  716. if (i == r)
  717. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  718. if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  719. fill_rx = 1;
  720. while (i != r) {
  721. rxb = rxq->queue[i];
  722. /* If an RXB doesn't have a Rx queue slot associated with it,
  723. * then a bug has been introduced in the queue refilling
  724. * routines -- catch it here */
  725. BUG_ON(rxb == NULL);
  726. rxq->queue[i] = NULL;
  727. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  728. priv->hw_params.rx_buf_size + 256,
  729. PCI_DMA_FROMDEVICE);
  730. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  731. /* Reclaim a command buffer only if this packet is a response
  732. * to a (driver-originated) command.
  733. * If the packet (e.g. Rx frame) originated from uCode,
  734. * there is no command buffer to reclaim.
  735. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  736. * but apparently a few don't get set; catch them here. */
  737. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  738. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  739. (pkt->hdr.cmd != REPLY_RX) &&
  740. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  741. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  742. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  743. (pkt->hdr.cmd != REPLY_TX);
  744. /* Based on type of command response or notification,
  745. * handle those that need handling via function in
  746. * rx_handlers table. See iwl_setup_rx_handlers() */
  747. if (priv->rx_handlers[pkt->hdr.cmd]) {
  748. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  749. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  750. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  751. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  752. } else {
  753. /* No handling needed */
  754. IWL_DEBUG_RX(priv,
  755. "r %d i %d No handler needed for %s, 0x%02x\n",
  756. r, i, get_cmd_string(pkt->hdr.cmd),
  757. pkt->hdr.cmd);
  758. }
  759. if (reclaim) {
  760. /* Invoke any callbacks, transfer the skb to caller, and
  761. * fire off the (possibly) blocking iwl_send_cmd()
  762. * as we reclaim the driver command queue */
  763. if (rxb && rxb->skb)
  764. iwl_tx_cmd_complete(priv, rxb);
  765. else
  766. IWL_WARN(priv, "Claim null rxb?\n");
  767. }
  768. /* For now we just don't re-use anything. We can tweak this
  769. * later to try and re-use notification packets and SKBs that
  770. * fail to Rx correctly */
  771. if (rxb->skb != NULL) {
  772. priv->alloc_rxb_skb--;
  773. dev_kfree_skb_any(rxb->skb);
  774. rxb->skb = NULL;
  775. }
  776. spin_lock_irqsave(&rxq->lock, flags);
  777. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  778. spin_unlock_irqrestore(&rxq->lock, flags);
  779. i = (i + 1) & RX_QUEUE_MASK;
  780. /* If there are a lot of unused frames,
  781. * restock the Rx queue so ucode wont assert. */
  782. if (fill_rx) {
  783. count++;
  784. if (count >= 8) {
  785. priv->rxq.read = i;
  786. iwl_rx_queue_restock(priv);
  787. count = 0;
  788. }
  789. }
  790. }
  791. /* Backtrack one entry */
  792. priv->rxq.read = i;
  793. iwl_rx_queue_restock(priv);
  794. }
  795. /* call this function to flush any scheduled tasklet */
  796. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  797. {
  798. /* wait to make sure we flush pending tasklet*/
  799. synchronize_irq(priv->pci_dev->irq);
  800. tasklet_kill(&priv->irq_tasklet);
  801. }
  802. static void iwl_irq_tasklet(struct iwl_priv *priv)
  803. {
  804. u32 inta, handled = 0;
  805. u32 inta_fh;
  806. unsigned long flags;
  807. #ifdef CONFIG_IWLWIFI_DEBUG
  808. u32 inta_mask;
  809. #endif
  810. spin_lock_irqsave(&priv->lock, flags);
  811. /* Ack/clear/reset pending uCode interrupts.
  812. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  813. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  814. inta = iwl_read32(priv, CSR_INT);
  815. iwl_write32(priv, CSR_INT, inta);
  816. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  817. * Any new interrupts that happen after this, either while we're
  818. * in this tasklet, or later, will show up in next ISR/tasklet. */
  819. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  820. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  821. #ifdef CONFIG_IWLWIFI_DEBUG
  822. if (priv->debug_level & IWL_DL_ISR) {
  823. /* just for debug */
  824. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  825. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  826. inta, inta_mask, inta_fh);
  827. }
  828. #endif
  829. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  830. * atomic, make sure that inta covers all the interrupts that
  831. * we've discovered, even if FH interrupt came in just after
  832. * reading CSR_INT. */
  833. if (inta_fh & CSR49_FH_INT_RX_MASK)
  834. inta |= CSR_INT_BIT_FH_RX;
  835. if (inta_fh & CSR49_FH_INT_TX_MASK)
  836. inta |= CSR_INT_BIT_FH_TX;
  837. /* Now service all interrupt bits discovered above. */
  838. if (inta & CSR_INT_BIT_HW_ERR) {
  839. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  840. /* Tell the device to stop sending interrupts */
  841. iwl_disable_interrupts(priv);
  842. priv->isr_stats.hw++;
  843. iwl_irq_handle_error(priv);
  844. handled |= CSR_INT_BIT_HW_ERR;
  845. spin_unlock_irqrestore(&priv->lock, flags);
  846. return;
  847. }
  848. #ifdef CONFIG_IWLWIFI_DEBUG
  849. if (priv->debug_level & (IWL_DL_ISR)) {
  850. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  851. if (inta & CSR_INT_BIT_SCD) {
  852. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  853. "the frame/frames.\n");
  854. priv->isr_stats.sch++;
  855. }
  856. /* Alive notification via Rx interrupt will do the real work */
  857. if (inta & CSR_INT_BIT_ALIVE) {
  858. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  859. priv->isr_stats.alive++;
  860. }
  861. }
  862. #endif
  863. /* Safely ignore these bits for debug checks below */
  864. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  865. /* HW RF KILL switch toggled */
  866. if (inta & CSR_INT_BIT_RF_KILL) {
  867. int hw_rf_kill = 0;
  868. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  869. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  870. hw_rf_kill = 1;
  871. IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
  872. hw_rf_kill ? "disable radio" : "enable radio");
  873. priv->isr_stats.rfkill++;
  874. /* driver only loads ucode once setting the interface up.
  875. * the driver allows loading the ucode even if the radio
  876. * is killed. Hence update the killswitch state here. The
  877. * rfkill handler will care about restarting if needed.
  878. */
  879. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  880. if (hw_rf_kill)
  881. set_bit(STATUS_RF_KILL_HW, &priv->status);
  882. else
  883. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  884. queue_work(priv->workqueue, &priv->rf_kill);
  885. }
  886. handled |= CSR_INT_BIT_RF_KILL;
  887. }
  888. /* Chip got too hot and stopped itself */
  889. if (inta & CSR_INT_BIT_CT_KILL) {
  890. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  891. priv->isr_stats.ctkill++;
  892. handled |= CSR_INT_BIT_CT_KILL;
  893. }
  894. /* Error detected by uCode */
  895. if (inta & CSR_INT_BIT_SW_ERR) {
  896. IWL_ERR(priv, "Microcode SW error detected. "
  897. " Restarting 0x%X.\n", inta);
  898. priv->isr_stats.sw++;
  899. priv->isr_stats.sw_err = inta;
  900. iwl_irq_handle_error(priv);
  901. handled |= CSR_INT_BIT_SW_ERR;
  902. }
  903. /* uCode wakes up after power-down sleep */
  904. if (inta & CSR_INT_BIT_WAKEUP) {
  905. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  906. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  907. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  908. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  909. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  910. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  911. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  912. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  913. priv->isr_stats.wakeup++;
  914. handled |= CSR_INT_BIT_WAKEUP;
  915. }
  916. /* All uCode command responses, including Tx command responses,
  917. * Rx "responses" (frame-received notification), and other
  918. * notifications from uCode come through here*/
  919. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  920. iwl_rx_handle(priv);
  921. priv->isr_stats.rx++;
  922. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  923. }
  924. if (inta & CSR_INT_BIT_FH_TX) {
  925. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  926. priv->isr_stats.tx++;
  927. handled |= CSR_INT_BIT_FH_TX;
  928. /* FH finished to write, send event */
  929. priv->ucode_write_complete = 1;
  930. wake_up_interruptible(&priv->wait_command_queue);
  931. }
  932. if (inta & ~handled) {
  933. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  934. priv->isr_stats.unhandled++;
  935. }
  936. if (inta & ~CSR_INI_SET_MASK) {
  937. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  938. inta & ~CSR_INI_SET_MASK);
  939. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  940. }
  941. /* Re-enable all interrupts */
  942. /* only Re-enable if diabled by irq */
  943. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  944. iwl_enable_interrupts(priv);
  945. #ifdef CONFIG_IWLWIFI_DEBUG
  946. if (priv->debug_level & (IWL_DL_ISR)) {
  947. inta = iwl_read32(priv, CSR_INT);
  948. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  949. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  950. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  951. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  952. }
  953. #endif
  954. spin_unlock_irqrestore(&priv->lock, flags);
  955. }
  956. /******************************************************************************
  957. *
  958. * uCode download functions
  959. *
  960. ******************************************************************************/
  961. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  962. {
  963. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  964. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  965. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  966. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  967. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  968. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  969. }
  970. static void iwl_nic_start(struct iwl_priv *priv)
  971. {
  972. /* Remove all resets to allow NIC to operate */
  973. iwl_write32(priv, CSR_RESET, 0);
  974. }
  975. /**
  976. * iwl_read_ucode - Read uCode images from disk file.
  977. *
  978. * Copy into buffers for card to fetch via bus-mastering
  979. */
  980. static int iwl_read_ucode(struct iwl_priv *priv)
  981. {
  982. struct iwl_ucode *ucode;
  983. int ret = -EINVAL, index;
  984. const struct firmware *ucode_raw;
  985. const char *name_pre = priv->cfg->fw_name_pre;
  986. const unsigned int api_max = priv->cfg->ucode_api_max;
  987. const unsigned int api_min = priv->cfg->ucode_api_min;
  988. char buf[25];
  989. u8 *src;
  990. size_t len;
  991. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  992. /* Ask kernel firmware_class module to get the boot firmware off disk.
  993. * request_firmware() is synchronous, file is in memory on return. */
  994. for (index = api_max; index >= api_min; index--) {
  995. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  996. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  997. if (ret < 0) {
  998. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  999. buf, ret);
  1000. if (ret == -ENOENT)
  1001. continue;
  1002. else
  1003. goto error;
  1004. } else {
  1005. if (index < api_max)
  1006. IWL_ERR(priv, "Loaded firmware %s, "
  1007. "which is deprecated. "
  1008. "Please use API v%u instead.\n",
  1009. buf, api_max);
  1010. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1011. buf, ucode_raw->size);
  1012. break;
  1013. }
  1014. }
  1015. if (ret < 0)
  1016. goto error;
  1017. /* Make sure that we got at least our header! */
  1018. if (ucode_raw->size < sizeof(*ucode)) {
  1019. IWL_ERR(priv, "File size way too small!\n");
  1020. ret = -EINVAL;
  1021. goto err_release;
  1022. }
  1023. /* Data from ucode file: header followed by uCode images */
  1024. ucode = (void *)ucode_raw->data;
  1025. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1026. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1027. inst_size = le32_to_cpu(ucode->inst_size);
  1028. data_size = le32_to_cpu(ucode->data_size);
  1029. init_size = le32_to_cpu(ucode->init_size);
  1030. init_data_size = le32_to_cpu(ucode->init_data_size);
  1031. boot_size = le32_to_cpu(ucode->boot_size);
  1032. /* api_ver should match the api version forming part of the
  1033. * firmware filename ... but we don't check for that and only rely
  1034. * on the API version read from firmware header from here on forward */
  1035. if (api_ver < api_min || api_ver > api_max) {
  1036. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1037. "Driver supports v%u, firmware is v%u.\n",
  1038. api_max, api_ver);
  1039. priv->ucode_ver = 0;
  1040. ret = -EINVAL;
  1041. goto err_release;
  1042. }
  1043. if (api_ver != api_max)
  1044. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1045. "got v%u. New firmware can be obtained "
  1046. "from http://www.intellinuxwireless.org.\n",
  1047. api_max, api_ver);
  1048. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1049. IWL_UCODE_MAJOR(priv->ucode_ver),
  1050. IWL_UCODE_MINOR(priv->ucode_ver),
  1051. IWL_UCODE_API(priv->ucode_ver),
  1052. IWL_UCODE_SERIAL(priv->ucode_ver));
  1053. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1054. priv->ucode_ver);
  1055. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1056. inst_size);
  1057. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1058. data_size);
  1059. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1060. init_size);
  1061. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1062. init_data_size);
  1063. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1064. boot_size);
  1065. /* Verify size of file vs. image size info in file's header */
  1066. if (ucode_raw->size < sizeof(*ucode) +
  1067. inst_size + data_size + init_size +
  1068. init_data_size + boot_size) {
  1069. IWL_DEBUG_INFO(priv, "uCode file size %d too small\n",
  1070. (int)ucode_raw->size);
  1071. ret = -EINVAL;
  1072. goto err_release;
  1073. }
  1074. /* Verify that uCode images will fit in card's SRAM */
  1075. if (inst_size > priv->hw_params.max_inst_size) {
  1076. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1077. inst_size);
  1078. ret = -EINVAL;
  1079. goto err_release;
  1080. }
  1081. if (data_size > priv->hw_params.max_data_size) {
  1082. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1083. data_size);
  1084. ret = -EINVAL;
  1085. goto err_release;
  1086. }
  1087. if (init_size > priv->hw_params.max_inst_size) {
  1088. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1089. init_size);
  1090. ret = -EINVAL;
  1091. goto err_release;
  1092. }
  1093. if (init_data_size > priv->hw_params.max_data_size) {
  1094. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1095. init_data_size);
  1096. ret = -EINVAL;
  1097. goto err_release;
  1098. }
  1099. if (boot_size > priv->hw_params.max_bsm_size) {
  1100. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1101. boot_size);
  1102. ret = -EINVAL;
  1103. goto err_release;
  1104. }
  1105. /* Allocate ucode buffers for card's bus-master loading ... */
  1106. /* Runtime instructions and 2 copies of data:
  1107. * 1) unmodified from disk
  1108. * 2) backup cache for save/restore during power-downs */
  1109. priv->ucode_code.len = inst_size;
  1110. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1111. priv->ucode_data.len = data_size;
  1112. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1113. priv->ucode_data_backup.len = data_size;
  1114. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1115. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1116. !priv->ucode_data_backup.v_addr)
  1117. goto err_pci_alloc;
  1118. /* Initialization instructions and data */
  1119. if (init_size && init_data_size) {
  1120. priv->ucode_init.len = init_size;
  1121. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1122. priv->ucode_init_data.len = init_data_size;
  1123. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1124. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1125. goto err_pci_alloc;
  1126. }
  1127. /* Bootstrap (instructions only, no data) */
  1128. if (boot_size) {
  1129. priv->ucode_boot.len = boot_size;
  1130. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1131. if (!priv->ucode_boot.v_addr)
  1132. goto err_pci_alloc;
  1133. }
  1134. /* Copy images into buffers for card's bus-master reads ... */
  1135. /* Runtime instructions (first block of data in file) */
  1136. src = &ucode->data[0];
  1137. len = priv->ucode_code.len;
  1138. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1139. memcpy(priv->ucode_code.v_addr, src, len);
  1140. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1141. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1142. /* Runtime data (2nd block)
  1143. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1144. src = &ucode->data[inst_size];
  1145. len = priv->ucode_data.len;
  1146. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1147. memcpy(priv->ucode_data.v_addr, src, len);
  1148. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1149. /* Initialization instructions (3rd block) */
  1150. if (init_size) {
  1151. src = &ucode->data[inst_size + data_size];
  1152. len = priv->ucode_init.len;
  1153. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1154. len);
  1155. memcpy(priv->ucode_init.v_addr, src, len);
  1156. }
  1157. /* Initialization data (4th block) */
  1158. if (init_data_size) {
  1159. src = &ucode->data[inst_size + data_size + init_size];
  1160. len = priv->ucode_init_data.len;
  1161. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1162. len);
  1163. memcpy(priv->ucode_init_data.v_addr, src, len);
  1164. }
  1165. /* Bootstrap instructions (5th block) */
  1166. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  1167. len = priv->ucode_boot.len;
  1168. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1169. memcpy(priv->ucode_boot.v_addr, src, len);
  1170. /* We have our copies now, allow OS release its copies */
  1171. release_firmware(ucode_raw);
  1172. return 0;
  1173. err_pci_alloc:
  1174. IWL_ERR(priv, "failed to allocate pci memory\n");
  1175. ret = -ENOMEM;
  1176. iwl_dealloc_ucode_pci(priv);
  1177. err_release:
  1178. release_firmware(ucode_raw);
  1179. error:
  1180. return ret;
  1181. }
  1182. /**
  1183. * iwl_alive_start - called after REPLY_ALIVE notification received
  1184. * from protocol/runtime uCode (initialization uCode's
  1185. * Alive gets handled by iwl_init_alive_start()).
  1186. */
  1187. static void iwl_alive_start(struct iwl_priv *priv)
  1188. {
  1189. int ret = 0;
  1190. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1191. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1192. /* We had an error bringing up the hardware, so take it
  1193. * all the way back down so we can try again */
  1194. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1195. goto restart;
  1196. }
  1197. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1198. * This is a paranoid check, because we would not have gotten the
  1199. * "runtime" alive if code weren't properly loaded. */
  1200. if (iwl_verify_ucode(priv)) {
  1201. /* Runtime instruction load was bad;
  1202. * take it all the way back down so we can try again */
  1203. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1204. goto restart;
  1205. }
  1206. priv->cfg->ops->smgmt->clear_station_table(priv);
  1207. ret = priv->cfg->ops->lib->alive_notify(priv);
  1208. if (ret) {
  1209. IWL_WARN(priv,
  1210. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1211. goto restart;
  1212. }
  1213. /* After the ALIVE response, we can send host commands to the uCode */
  1214. set_bit(STATUS_ALIVE, &priv->status);
  1215. if (iwl_is_rfkill(priv))
  1216. return;
  1217. ieee80211_wake_queues(priv->hw);
  1218. priv->active_rate = priv->rates_mask;
  1219. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1220. if (iwl_is_associated(priv)) {
  1221. struct iwl_rxon_cmd *active_rxon =
  1222. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1223. /* apply any changes in staging */
  1224. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1225. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1226. } else {
  1227. /* Initialize our rx_config data */
  1228. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1229. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1230. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1231. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1232. }
  1233. /* Configure Bluetooth device coexistence support */
  1234. iwl_send_bt_config(priv);
  1235. iwl_reset_run_time_calib(priv);
  1236. /* Configure the adapter for unassociated operation */
  1237. iwlcore_commit_rxon(priv);
  1238. /* At this point, the NIC is initialized and operational */
  1239. iwl_rf_kill_ct_config(priv);
  1240. iwl_leds_register(priv);
  1241. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1242. set_bit(STATUS_READY, &priv->status);
  1243. wake_up_interruptible(&priv->wait_command_queue);
  1244. iwl_power_update_mode(priv, 1);
  1245. /* reassociate for ADHOC mode */
  1246. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1247. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1248. priv->vif);
  1249. if (beacon)
  1250. iwl_mac_beacon_update(priv->hw, beacon);
  1251. }
  1252. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1253. iwl_set_mode(priv, priv->iw_mode);
  1254. return;
  1255. restart:
  1256. queue_work(priv->workqueue, &priv->restart);
  1257. }
  1258. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1259. static void __iwl_down(struct iwl_priv *priv)
  1260. {
  1261. unsigned long flags;
  1262. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1263. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1264. if (!exit_pending)
  1265. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1266. iwl_leds_unregister(priv);
  1267. priv->cfg->ops->smgmt->clear_station_table(priv);
  1268. /* Unblock any waiting calls */
  1269. wake_up_interruptible_all(&priv->wait_command_queue);
  1270. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1271. * exiting the module */
  1272. if (!exit_pending)
  1273. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1274. /* stop and reset the on-board processor */
  1275. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1276. /* tell the device to stop sending interrupts */
  1277. spin_lock_irqsave(&priv->lock, flags);
  1278. iwl_disable_interrupts(priv);
  1279. spin_unlock_irqrestore(&priv->lock, flags);
  1280. iwl_synchronize_irq(priv);
  1281. if (priv->mac80211_registered)
  1282. ieee80211_stop_queues(priv->hw);
  1283. /* If we have not previously called iwl_init() then
  1284. * clear all bits but the RF Kill bits and return */
  1285. if (!iwl_is_init(priv)) {
  1286. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1287. STATUS_RF_KILL_HW |
  1288. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  1289. STATUS_RF_KILL_SW |
  1290. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1291. STATUS_GEO_CONFIGURED |
  1292. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1293. STATUS_EXIT_PENDING;
  1294. goto exit;
  1295. }
  1296. /* ...otherwise clear out all the status bits but the RF Kill
  1297. * bits and continue taking the NIC down. */
  1298. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1299. STATUS_RF_KILL_HW |
  1300. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  1301. STATUS_RF_KILL_SW |
  1302. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1303. STATUS_GEO_CONFIGURED |
  1304. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1305. STATUS_FW_ERROR |
  1306. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1307. STATUS_EXIT_PENDING;
  1308. spin_lock_irqsave(&priv->lock, flags);
  1309. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1310. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1311. spin_unlock_irqrestore(&priv->lock, flags);
  1312. iwl_txq_ctx_stop(priv);
  1313. iwl_rxq_stop(priv);
  1314. spin_lock_irqsave(&priv->lock, flags);
  1315. if (!iwl_grab_nic_access(priv)) {
  1316. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1317. APMG_CLK_VAL_DMA_CLK_RQT);
  1318. iwl_release_nic_access(priv);
  1319. }
  1320. spin_unlock_irqrestore(&priv->lock, flags);
  1321. udelay(5);
  1322. /* FIXME: apm_ops.suspend(priv) */
  1323. if (exit_pending)
  1324. priv->cfg->ops->lib->apm_ops.stop(priv);
  1325. else
  1326. priv->cfg->ops->lib->apm_ops.reset(priv);
  1327. exit:
  1328. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1329. if (priv->ibss_beacon)
  1330. dev_kfree_skb(priv->ibss_beacon);
  1331. priv->ibss_beacon = NULL;
  1332. /* clear out any free frames */
  1333. iwl_clear_free_frames(priv);
  1334. }
  1335. static void iwl_down(struct iwl_priv *priv)
  1336. {
  1337. mutex_lock(&priv->mutex);
  1338. __iwl_down(priv);
  1339. mutex_unlock(&priv->mutex);
  1340. iwl_cancel_deferred_work(priv);
  1341. }
  1342. #define MAX_HW_RESTARTS 5
  1343. static int __iwl_up(struct iwl_priv *priv)
  1344. {
  1345. int i;
  1346. int ret;
  1347. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1348. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1349. return -EIO;
  1350. }
  1351. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1352. IWL_ERR(priv, "ucode not available for device bringup\n");
  1353. return -EIO;
  1354. }
  1355. /* If platform's RF_KILL switch is NOT set to KILL */
  1356. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1357. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1358. else
  1359. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1360. if (iwl_is_rfkill(priv)) {
  1361. iwl_enable_interrupts(priv);
  1362. IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n",
  1363. test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW");
  1364. return 0;
  1365. }
  1366. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1367. ret = iwl_hw_nic_init(priv);
  1368. if (ret) {
  1369. IWL_ERR(priv, "Unable to init nic\n");
  1370. return ret;
  1371. }
  1372. /* make sure rfkill handshake bits are cleared */
  1373. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1374. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1375. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1376. /* clear (again), then enable host interrupts */
  1377. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1378. iwl_enable_interrupts(priv);
  1379. /* really make sure rfkill handshake bits are cleared */
  1380. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1381. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1382. /* Copy original ucode data image from disk into backup cache.
  1383. * This will be used to initialize the on-board processor's
  1384. * data SRAM for a clean start when the runtime program first loads. */
  1385. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1386. priv->ucode_data.len);
  1387. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1388. priv->cfg->ops->smgmt->clear_station_table(priv);
  1389. /* load bootstrap state machine,
  1390. * load bootstrap program into processor's memory,
  1391. * prepare to load the "initialize" uCode */
  1392. ret = priv->cfg->ops->lib->load_ucode(priv);
  1393. if (ret) {
  1394. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1395. ret);
  1396. continue;
  1397. }
  1398. /* start card; "initialize" will load runtime ucode */
  1399. iwl_nic_start(priv);
  1400. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1401. return 0;
  1402. }
  1403. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1404. __iwl_down(priv);
  1405. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1406. /* tried to restart and config the device for as long as our
  1407. * patience could withstand */
  1408. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1409. return -EIO;
  1410. }
  1411. /*****************************************************************************
  1412. *
  1413. * Workqueue callbacks
  1414. *
  1415. *****************************************************************************/
  1416. static void iwl_bg_init_alive_start(struct work_struct *data)
  1417. {
  1418. struct iwl_priv *priv =
  1419. container_of(data, struct iwl_priv, init_alive_start.work);
  1420. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1421. return;
  1422. mutex_lock(&priv->mutex);
  1423. priv->cfg->ops->lib->init_alive_start(priv);
  1424. mutex_unlock(&priv->mutex);
  1425. }
  1426. static void iwl_bg_alive_start(struct work_struct *data)
  1427. {
  1428. struct iwl_priv *priv =
  1429. container_of(data, struct iwl_priv, alive_start.work);
  1430. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1431. return;
  1432. mutex_lock(&priv->mutex);
  1433. iwl_alive_start(priv);
  1434. mutex_unlock(&priv->mutex);
  1435. }
  1436. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1437. {
  1438. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1439. run_time_calib_work);
  1440. mutex_lock(&priv->mutex);
  1441. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1442. test_bit(STATUS_SCANNING, &priv->status)) {
  1443. mutex_unlock(&priv->mutex);
  1444. return;
  1445. }
  1446. if (priv->start_calib) {
  1447. iwl_chain_noise_calibration(priv, &priv->statistics);
  1448. iwl_sensitivity_calibration(priv, &priv->statistics);
  1449. }
  1450. mutex_unlock(&priv->mutex);
  1451. return;
  1452. }
  1453. static void iwl_bg_up(struct work_struct *data)
  1454. {
  1455. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1456. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1457. return;
  1458. mutex_lock(&priv->mutex);
  1459. __iwl_up(priv);
  1460. mutex_unlock(&priv->mutex);
  1461. iwl_rfkill_set_hw_state(priv);
  1462. }
  1463. static void iwl_bg_restart(struct work_struct *data)
  1464. {
  1465. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1466. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1467. return;
  1468. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1469. mutex_lock(&priv->mutex);
  1470. priv->vif = NULL;
  1471. priv->is_open = 0;
  1472. mutex_unlock(&priv->mutex);
  1473. iwl_down(priv);
  1474. ieee80211_restart_hw(priv->hw);
  1475. } else {
  1476. iwl_down(priv);
  1477. queue_work(priv->workqueue, &priv->up);
  1478. }
  1479. }
  1480. static void iwl_bg_rx_replenish(struct work_struct *data)
  1481. {
  1482. struct iwl_priv *priv =
  1483. container_of(data, struct iwl_priv, rx_replenish);
  1484. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1485. return;
  1486. mutex_lock(&priv->mutex);
  1487. iwl_rx_replenish(priv);
  1488. mutex_unlock(&priv->mutex);
  1489. }
  1490. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1491. void iwl_post_associate(struct iwl_priv *priv)
  1492. {
  1493. struct ieee80211_conf *conf = NULL;
  1494. int ret = 0;
  1495. unsigned long flags;
  1496. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1497. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1498. return;
  1499. }
  1500. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1501. priv->assoc_id, priv->active_rxon.bssid_addr);
  1502. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1503. return;
  1504. if (!priv->vif || !priv->is_open)
  1505. return;
  1506. iwl_power_cancel_timeout(priv);
  1507. iwl_scan_cancel_timeout(priv, 200);
  1508. conf = ieee80211_get_hw_conf(priv->hw);
  1509. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1510. iwlcore_commit_rxon(priv);
  1511. iwl_setup_rxon_timing(priv);
  1512. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1513. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1514. if (ret)
  1515. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1516. "Attempting to continue.\n");
  1517. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1518. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1519. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1520. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1521. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1522. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1523. priv->assoc_id, priv->beacon_int);
  1524. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1525. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1526. else
  1527. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1528. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1529. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1530. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1531. else
  1532. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1533. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1534. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1535. }
  1536. iwlcore_commit_rxon(priv);
  1537. switch (priv->iw_mode) {
  1538. case NL80211_IFTYPE_STATION:
  1539. break;
  1540. case NL80211_IFTYPE_ADHOC:
  1541. /* assume default assoc id */
  1542. priv->assoc_id = 1;
  1543. iwl_rxon_add_station(priv, priv->bssid, 0);
  1544. iwl_send_beacon_cmd(priv);
  1545. break;
  1546. default:
  1547. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1548. __func__, priv->iw_mode);
  1549. break;
  1550. }
  1551. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1552. priv->assoc_station_added = 1;
  1553. spin_lock_irqsave(&priv->lock, flags);
  1554. iwl_activate_qos(priv, 0);
  1555. spin_unlock_irqrestore(&priv->lock, flags);
  1556. /* the chain noise calibration will enabled PM upon completion
  1557. * If chain noise has already been run, then we need to enable
  1558. * power management here */
  1559. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1560. iwl_power_enable_management(priv);
  1561. /* Enable Rx differential gain and sensitivity calibrations */
  1562. iwl_chain_noise_reset(priv);
  1563. priv->start_calib = 1;
  1564. }
  1565. /*****************************************************************************
  1566. *
  1567. * mac80211 entry point functions
  1568. *
  1569. *****************************************************************************/
  1570. #define UCODE_READY_TIMEOUT (4 * HZ)
  1571. static int iwl_mac_start(struct ieee80211_hw *hw)
  1572. {
  1573. struct iwl_priv *priv = hw->priv;
  1574. int ret;
  1575. IWL_DEBUG_MAC80211(priv, "enter\n");
  1576. /* we should be verifying the device is ready to be opened */
  1577. mutex_lock(&priv->mutex);
  1578. memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd));
  1579. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1580. * ucode filename and max sizes are card-specific. */
  1581. if (!priv->ucode_code.len) {
  1582. ret = iwl_read_ucode(priv);
  1583. if (ret) {
  1584. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1585. mutex_unlock(&priv->mutex);
  1586. return ret;
  1587. }
  1588. }
  1589. ret = __iwl_up(priv);
  1590. mutex_unlock(&priv->mutex);
  1591. iwl_rfkill_set_hw_state(priv);
  1592. if (ret)
  1593. return ret;
  1594. if (iwl_is_rfkill(priv))
  1595. goto out;
  1596. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1597. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1598. * mac80211 will not be run successfully. */
  1599. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1600. test_bit(STATUS_READY, &priv->status),
  1601. UCODE_READY_TIMEOUT);
  1602. if (!ret) {
  1603. if (!test_bit(STATUS_READY, &priv->status)) {
  1604. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1605. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1606. return -ETIMEDOUT;
  1607. }
  1608. }
  1609. out:
  1610. priv->is_open = 1;
  1611. IWL_DEBUG_MAC80211(priv, "leave\n");
  1612. return 0;
  1613. }
  1614. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1615. {
  1616. struct iwl_priv *priv = hw->priv;
  1617. IWL_DEBUG_MAC80211(priv, "enter\n");
  1618. if (!priv->is_open)
  1619. return;
  1620. priv->is_open = 0;
  1621. if (iwl_is_ready_rf(priv)) {
  1622. /* stop mac, cancel any scan request and clear
  1623. * RXON_FILTER_ASSOC_MSK BIT
  1624. */
  1625. mutex_lock(&priv->mutex);
  1626. iwl_scan_cancel_timeout(priv, 100);
  1627. mutex_unlock(&priv->mutex);
  1628. }
  1629. iwl_down(priv);
  1630. flush_workqueue(priv->workqueue);
  1631. /* enable interrupts again in order to receive rfkill changes */
  1632. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1633. iwl_enable_interrupts(priv);
  1634. IWL_DEBUG_MAC80211(priv, "leave\n");
  1635. }
  1636. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1637. {
  1638. struct iwl_priv *priv = hw->priv;
  1639. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1640. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1641. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1642. if (iwl_tx_skb(priv, skb))
  1643. dev_kfree_skb_any(skb);
  1644. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1645. return NETDEV_TX_OK;
  1646. }
  1647. void iwl_config_ap(struct iwl_priv *priv)
  1648. {
  1649. int ret = 0;
  1650. unsigned long flags;
  1651. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1652. return;
  1653. /* The following should be done only at AP bring up */
  1654. if (!iwl_is_associated(priv)) {
  1655. /* RXON - unassoc (to set timing command) */
  1656. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1657. iwlcore_commit_rxon(priv);
  1658. /* RXON Timing */
  1659. iwl_setup_rxon_timing(priv);
  1660. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1661. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1662. if (ret)
  1663. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1664. "Attempting to continue.\n");
  1665. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1666. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1667. /* FIXME: what should be the assoc_id for AP? */
  1668. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1669. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1670. priv->staging_rxon.flags |=
  1671. RXON_FLG_SHORT_PREAMBLE_MSK;
  1672. else
  1673. priv->staging_rxon.flags &=
  1674. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1675. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1676. if (priv->assoc_capability &
  1677. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1678. priv->staging_rxon.flags |=
  1679. RXON_FLG_SHORT_SLOT_MSK;
  1680. else
  1681. priv->staging_rxon.flags &=
  1682. ~RXON_FLG_SHORT_SLOT_MSK;
  1683. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1684. priv->staging_rxon.flags &=
  1685. ~RXON_FLG_SHORT_SLOT_MSK;
  1686. }
  1687. /* restore RXON assoc */
  1688. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1689. iwlcore_commit_rxon(priv);
  1690. spin_lock_irqsave(&priv->lock, flags);
  1691. iwl_activate_qos(priv, 1);
  1692. spin_unlock_irqrestore(&priv->lock, flags);
  1693. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1694. }
  1695. iwl_send_beacon_cmd(priv);
  1696. /* FIXME - we need to add code here to detect a totally new
  1697. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1698. * clear sta table, add BCAST sta... */
  1699. }
  1700. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1701. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1702. u32 iv32, u16 *phase1key)
  1703. {
  1704. struct iwl_priv *priv = hw->priv;
  1705. IWL_DEBUG_MAC80211(priv, "enter\n");
  1706. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1707. IWL_DEBUG_MAC80211(priv, "leave\n");
  1708. }
  1709. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1710. struct ieee80211_vif *vif,
  1711. struct ieee80211_sta *sta,
  1712. struct ieee80211_key_conf *key)
  1713. {
  1714. struct iwl_priv *priv = hw->priv;
  1715. const u8 *addr;
  1716. int ret;
  1717. u8 sta_id;
  1718. bool is_default_wep_key = false;
  1719. IWL_DEBUG_MAC80211(priv, "enter\n");
  1720. if (priv->hw_params.sw_crypto) {
  1721. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  1722. return -EOPNOTSUPP;
  1723. }
  1724. addr = sta ? sta->addr : iwl_bcast_addr;
  1725. sta_id = priv->cfg->ops->smgmt->find_station(priv, addr);
  1726. if (sta_id == IWL_INVALID_STATION) {
  1727. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  1728. addr);
  1729. return -EINVAL;
  1730. }
  1731. mutex_lock(&priv->mutex);
  1732. iwl_scan_cancel_timeout(priv, 100);
  1733. mutex_unlock(&priv->mutex);
  1734. /* If we are getting WEP group key and we didn't receive any key mapping
  1735. * so far, we are in legacy wep mode (group key only), otherwise we are
  1736. * in 1X mode.
  1737. * In legacy wep mode, we use another host command to the uCode */
  1738. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  1739. priv->iw_mode != NL80211_IFTYPE_AP) {
  1740. if (cmd == SET_KEY)
  1741. is_default_wep_key = !priv->key_mapping_key;
  1742. else
  1743. is_default_wep_key =
  1744. (key->hw_key_idx == HW_KEY_DEFAULT);
  1745. }
  1746. switch (cmd) {
  1747. case SET_KEY:
  1748. if (is_default_wep_key)
  1749. ret = iwl_set_default_wep_key(priv, key);
  1750. else
  1751. ret = iwl_set_dynamic_key(priv, key, sta_id);
  1752. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  1753. break;
  1754. case DISABLE_KEY:
  1755. if (is_default_wep_key)
  1756. ret = iwl_remove_default_wep_key(priv, key);
  1757. else
  1758. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  1759. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  1760. break;
  1761. default:
  1762. ret = -EINVAL;
  1763. }
  1764. IWL_DEBUG_MAC80211(priv, "leave\n");
  1765. return ret;
  1766. }
  1767. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  1768. enum ieee80211_ampdu_mlme_action action,
  1769. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  1770. {
  1771. struct iwl_priv *priv = hw->priv;
  1772. int ret;
  1773. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  1774. sta->addr, tid);
  1775. if (!(priv->cfg->sku & IWL_SKU_N))
  1776. return -EACCES;
  1777. switch (action) {
  1778. case IEEE80211_AMPDU_RX_START:
  1779. IWL_DEBUG_HT(priv, "start Rx\n");
  1780. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  1781. case IEEE80211_AMPDU_RX_STOP:
  1782. IWL_DEBUG_HT(priv, "stop Rx\n");
  1783. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  1784. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1785. return 0;
  1786. else
  1787. return ret;
  1788. case IEEE80211_AMPDU_TX_START:
  1789. IWL_DEBUG_HT(priv, "start Tx\n");
  1790. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  1791. case IEEE80211_AMPDU_TX_STOP:
  1792. IWL_DEBUG_HT(priv, "stop Tx\n");
  1793. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  1794. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1795. return 0;
  1796. else
  1797. return ret;
  1798. default:
  1799. IWL_DEBUG_HT(priv, "unknown\n");
  1800. return -EINVAL;
  1801. break;
  1802. }
  1803. return 0;
  1804. }
  1805. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  1806. struct ieee80211_low_level_stats *stats)
  1807. {
  1808. struct iwl_priv *priv = hw->priv;
  1809. priv = hw->priv;
  1810. IWL_DEBUG_MAC80211(priv, "enter\n");
  1811. IWL_DEBUG_MAC80211(priv, "leave\n");
  1812. return 0;
  1813. }
  1814. /*****************************************************************************
  1815. *
  1816. * sysfs attributes
  1817. *
  1818. *****************************************************************************/
  1819. #ifdef CONFIG_IWLWIFI_DEBUG
  1820. /*
  1821. * The following adds a new attribute to the sysfs representation
  1822. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  1823. * used for controlling the debug level.
  1824. *
  1825. * See the level definitions in iwl for details.
  1826. */
  1827. static ssize_t show_debug_level(struct device *d,
  1828. struct device_attribute *attr, char *buf)
  1829. {
  1830. struct iwl_priv *priv = dev_get_drvdata(d);
  1831. return sprintf(buf, "0x%08X\n", priv->debug_level);
  1832. }
  1833. static ssize_t store_debug_level(struct device *d,
  1834. struct device_attribute *attr,
  1835. const char *buf, size_t count)
  1836. {
  1837. struct iwl_priv *priv = dev_get_drvdata(d);
  1838. unsigned long val;
  1839. int ret;
  1840. ret = strict_strtoul(buf, 0, &val);
  1841. if (ret)
  1842. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  1843. else
  1844. priv->debug_level = val;
  1845. return strnlen(buf, count);
  1846. }
  1847. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  1848. show_debug_level, store_debug_level);
  1849. #endif /* CONFIG_IWLWIFI_DEBUG */
  1850. static ssize_t show_version(struct device *d,
  1851. struct device_attribute *attr, char *buf)
  1852. {
  1853. struct iwl_priv *priv = dev_get_drvdata(d);
  1854. struct iwl_alive_resp *palive = &priv->card_alive;
  1855. ssize_t pos = 0;
  1856. u16 eeprom_ver;
  1857. if (palive->is_valid)
  1858. pos += sprintf(buf + pos,
  1859. "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
  1860. "fw type: 0x%01X 0x%01X\n",
  1861. palive->ucode_major, palive->ucode_minor,
  1862. palive->sw_rev[0], palive->sw_rev[1],
  1863. palive->ver_type, palive->ver_subtype);
  1864. else
  1865. pos += sprintf(buf + pos, "fw not loaded\n");
  1866. if (priv->eeprom) {
  1867. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1868. pos += sprintf(buf + pos, "EEPROM version: 0x%x\n",
  1869. eeprom_ver);
  1870. } else {
  1871. pos += sprintf(buf + pos, "EEPROM not initialzed\n");
  1872. }
  1873. return pos;
  1874. }
  1875. static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
  1876. static ssize_t show_temperature(struct device *d,
  1877. struct device_attribute *attr, char *buf)
  1878. {
  1879. struct iwl_priv *priv = dev_get_drvdata(d);
  1880. if (!iwl_is_alive(priv))
  1881. return -EAGAIN;
  1882. return sprintf(buf, "%d\n", priv->temperature);
  1883. }
  1884. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  1885. static ssize_t show_tx_power(struct device *d,
  1886. struct device_attribute *attr, char *buf)
  1887. {
  1888. struct iwl_priv *priv = dev_get_drvdata(d);
  1889. if (!iwl_is_ready_rf(priv))
  1890. return sprintf(buf, "off\n");
  1891. else
  1892. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  1893. }
  1894. static ssize_t store_tx_power(struct device *d,
  1895. struct device_attribute *attr,
  1896. const char *buf, size_t count)
  1897. {
  1898. struct iwl_priv *priv = dev_get_drvdata(d);
  1899. unsigned long val;
  1900. int ret;
  1901. ret = strict_strtoul(buf, 10, &val);
  1902. if (ret)
  1903. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  1904. else
  1905. iwl_set_tx_power(priv, val, false);
  1906. return count;
  1907. }
  1908. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  1909. static ssize_t show_flags(struct device *d,
  1910. struct device_attribute *attr, char *buf)
  1911. {
  1912. struct iwl_priv *priv = dev_get_drvdata(d);
  1913. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  1914. }
  1915. static ssize_t store_flags(struct device *d,
  1916. struct device_attribute *attr,
  1917. const char *buf, size_t count)
  1918. {
  1919. struct iwl_priv *priv = dev_get_drvdata(d);
  1920. unsigned long val;
  1921. u32 flags;
  1922. int ret = strict_strtoul(buf, 0, &val);
  1923. if (ret)
  1924. return ret;
  1925. flags = (u32)val;
  1926. mutex_lock(&priv->mutex);
  1927. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  1928. /* Cancel any currently running scans... */
  1929. if (iwl_scan_cancel_timeout(priv, 100))
  1930. IWL_WARN(priv, "Could not cancel scan.\n");
  1931. else {
  1932. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  1933. priv->staging_rxon.flags = cpu_to_le32(flags);
  1934. iwlcore_commit_rxon(priv);
  1935. }
  1936. }
  1937. mutex_unlock(&priv->mutex);
  1938. return count;
  1939. }
  1940. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  1941. static ssize_t show_filter_flags(struct device *d,
  1942. struct device_attribute *attr, char *buf)
  1943. {
  1944. struct iwl_priv *priv = dev_get_drvdata(d);
  1945. return sprintf(buf, "0x%04X\n",
  1946. le32_to_cpu(priv->active_rxon.filter_flags));
  1947. }
  1948. static ssize_t store_filter_flags(struct device *d,
  1949. struct device_attribute *attr,
  1950. const char *buf, size_t count)
  1951. {
  1952. struct iwl_priv *priv = dev_get_drvdata(d);
  1953. unsigned long val;
  1954. u32 filter_flags;
  1955. int ret = strict_strtoul(buf, 0, &val);
  1956. if (ret)
  1957. return ret;
  1958. filter_flags = (u32)val;
  1959. mutex_lock(&priv->mutex);
  1960. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  1961. /* Cancel any currently running scans... */
  1962. if (iwl_scan_cancel_timeout(priv, 100))
  1963. IWL_WARN(priv, "Could not cancel scan.\n");
  1964. else {
  1965. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  1966. "0x%04X\n", filter_flags);
  1967. priv->staging_rxon.filter_flags =
  1968. cpu_to_le32(filter_flags);
  1969. iwlcore_commit_rxon(priv);
  1970. }
  1971. }
  1972. mutex_unlock(&priv->mutex);
  1973. return count;
  1974. }
  1975. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  1976. store_filter_flags);
  1977. static ssize_t store_power_level(struct device *d,
  1978. struct device_attribute *attr,
  1979. const char *buf, size_t count)
  1980. {
  1981. struct iwl_priv *priv = dev_get_drvdata(d);
  1982. int ret;
  1983. unsigned long mode;
  1984. mutex_lock(&priv->mutex);
  1985. ret = strict_strtoul(buf, 10, &mode);
  1986. if (ret)
  1987. goto out;
  1988. ret = iwl_power_set_user_mode(priv, mode);
  1989. if (ret) {
  1990. IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
  1991. goto out;
  1992. }
  1993. ret = count;
  1994. out:
  1995. mutex_unlock(&priv->mutex);
  1996. return ret;
  1997. }
  1998. static ssize_t show_power_level(struct device *d,
  1999. struct device_attribute *attr, char *buf)
  2000. {
  2001. struct iwl_priv *priv = dev_get_drvdata(d);
  2002. int mode = priv->power_data.user_power_setting;
  2003. int system = priv->power_data.system_power_setting;
  2004. int level = priv->power_data.power_mode;
  2005. char *p = buf;
  2006. switch (system) {
  2007. case IWL_POWER_SYS_AUTO:
  2008. p += sprintf(p, "SYSTEM:auto");
  2009. break;
  2010. case IWL_POWER_SYS_AC:
  2011. p += sprintf(p, "SYSTEM:ac");
  2012. break;
  2013. case IWL_POWER_SYS_BATTERY:
  2014. p += sprintf(p, "SYSTEM:battery");
  2015. break;
  2016. }
  2017. p += sprintf(p, "\tMODE:%s", (mode < IWL_POWER_AUTO) ?
  2018. "fixed" : "auto");
  2019. p += sprintf(p, "\tINDEX:%d", level);
  2020. p += sprintf(p, "\n");
  2021. return p - buf + 1;
  2022. }
  2023. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  2024. store_power_level);
  2025. static ssize_t show_statistics(struct device *d,
  2026. struct device_attribute *attr, char *buf)
  2027. {
  2028. struct iwl_priv *priv = dev_get_drvdata(d);
  2029. u32 size = sizeof(struct iwl_notif_statistics);
  2030. u32 len = 0, ofs = 0;
  2031. u8 *data = (u8 *)&priv->statistics;
  2032. int rc = 0;
  2033. if (!iwl_is_alive(priv))
  2034. return -EAGAIN;
  2035. mutex_lock(&priv->mutex);
  2036. rc = iwl_send_statistics_request(priv, 0);
  2037. mutex_unlock(&priv->mutex);
  2038. if (rc) {
  2039. len = sprintf(buf,
  2040. "Error sending statistics request: 0x%08X\n", rc);
  2041. return len;
  2042. }
  2043. while (size && (PAGE_SIZE - len)) {
  2044. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2045. PAGE_SIZE - len, 1);
  2046. len = strlen(buf);
  2047. if (PAGE_SIZE - len)
  2048. buf[len++] = '\n';
  2049. ofs += 16;
  2050. size -= min(size, 16U);
  2051. }
  2052. return len;
  2053. }
  2054. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2055. /*****************************************************************************
  2056. *
  2057. * driver setup and teardown
  2058. *
  2059. *****************************************************************************/
  2060. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2061. {
  2062. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2063. init_waitqueue_head(&priv->wait_command_queue);
  2064. INIT_WORK(&priv->up, iwl_bg_up);
  2065. INIT_WORK(&priv->restart, iwl_bg_restart);
  2066. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2067. INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
  2068. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2069. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2070. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2071. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2072. iwl_setup_scan_deferred_work(priv);
  2073. iwl_setup_power_deferred_work(priv);
  2074. if (priv->cfg->ops->lib->setup_deferred_work)
  2075. priv->cfg->ops->lib->setup_deferred_work(priv);
  2076. init_timer(&priv->statistics_periodic);
  2077. priv->statistics_periodic.data = (unsigned long)priv;
  2078. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2079. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2080. iwl_irq_tasklet, (unsigned long)priv);
  2081. }
  2082. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2083. {
  2084. if (priv->cfg->ops->lib->cancel_deferred_work)
  2085. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2086. cancel_delayed_work_sync(&priv->init_alive_start);
  2087. cancel_delayed_work(&priv->scan_check);
  2088. cancel_delayed_work_sync(&priv->set_power_save);
  2089. cancel_delayed_work(&priv->alive_start);
  2090. cancel_work_sync(&priv->beacon_update);
  2091. del_timer_sync(&priv->statistics_periodic);
  2092. }
  2093. static struct attribute *iwl_sysfs_entries[] = {
  2094. &dev_attr_flags.attr,
  2095. &dev_attr_filter_flags.attr,
  2096. &dev_attr_power_level.attr,
  2097. &dev_attr_statistics.attr,
  2098. &dev_attr_temperature.attr,
  2099. &dev_attr_tx_power.attr,
  2100. #ifdef CONFIG_IWLWIFI_DEBUG
  2101. &dev_attr_debug_level.attr,
  2102. #endif
  2103. &dev_attr_version.attr,
  2104. NULL
  2105. };
  2106. static struct attribute_group iwl_attribute_group = {
  2107. .name = NULL, /* put in device directory */
  2108. .attrs = iwl_sysfs_entries,
  2109. };
  2110. static struct ieee80211_ops iwl_hw_ops = {
  2111. .tx = iwl_mac_tx,
  2112. .start = iwl_mac_start,
  2113. .stop = iwl_mac_stop,
  2114. .add_interface = iwl_mac_add_interface,
  2115. .remove_interface = iwl_mac_remove_interface,
  2116. .config = iwl_mac_config,
  2117. .configure_filter = iwl_configure_filter,
  2118. .set_key = iwl_mac_set_key,
  2119. .update_tkip_key = iwl_mac_update_tkip_key,
  2120. .get_stats = iwl_mac_get_stats,
  2121. .get_tx_stats = iwl_mac_get_tx_stats,
  2122. .conf_tx = iwl_mac_conf_tx,
  2123. .reset_tsf = iwl_mac_reset_tsf,
  2124. .bss_info_changed = iwl_bss_info_changed,
  2125. .ampdu_action = iwl_mac_ampdu_action,
  2126. .hw_scan = iwl_mac_hw_scan
  2127. };
  2128. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2129. {
  2130. int err = 0;
  2131. struct iwl_priv *priv;
  2132. struct ieee80211_hw *hw;
  2133. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2134. unsigned long flags;
  2135. u16 pci_cmd;
  2136. /************************
  2137. * 1. Allocating HW data
  2138. ************************/
  2139. /* Disabling hardware scan means that mac80211 will perform scans
  2140. * "the hard way", rather than using device's scan. */
  2141. if (cfg->mod_params->disable_hw_scan) {
  2142. if (cfg->mod_params->debug & IWL_DL_INFO)
  2143. dev_printk(KERN_DEBUG, &(pdev->dev),
  2144. "Disabling hw_scan\n");
  2145. iwl_hw_ops.hw_scan = NULL;
  2146. }
  2147. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2148. if (!hw) {
  2149. err = -ENOMEM;
  2150. goto out;
  2151. }
  2152. priv = hw->priv;
  2153. /* At this point both hw and priv are allocated. */
  2154. SET_IEEE80211_DEV(hw, &pdev->dev);
  2155. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2156. priv->cfg = cfg;
  2157. priv->pci_dev = pdev;
  2158. #ifdef CONFIG_IWLWIFI_DEBUG
  2159. priv->debug_level = priv->cfg->mod_params->debug;
  2160. atomic_set(&priv->restrict_refcnt, 0);
  2161. #endif
  2162. /**************************
  2163. * 2. Initializing PCI bus
  2164. **************************/
  2165. if (pci_enable_device(pdev)) {
  2166. err = -ENODEV;
  2167. goto out_ieee80211_free_hw;
  2168. }
  2169. pci_set_master(pdev);
  2170. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2171. if (!err)
  2172. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2173. if (err) {
  2174. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2175. if (!err)
  2176. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2177. /* both attempts failed: */
  2178. if (err) {
  2179. IWL_WARN(priv, "No suitable DMA available.\n");
  2180. goto out_pci_disable_device;
  2181. }
  2182. }
  2183. err = pci_request_regions(pdev, DRV_NAME);
  2184. if (err)
  2185. goto out_pci_disable_device;
  2186. pci_set_drvdata(pdev, priv);
  2187. /***********************
  2188. * 3. Read REV register
  2189. ***********************/
  2190. priv->hw_base = pci_iomap(pdev, 0, 0);
  2191. if (!priv->hw_base) {
  2192. err = -ENODEV;
  2193. goto out_pci_release_regions;
  2194. }
  2195. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2196. (unsigned long long) pci_resource_len(pdev, 0));
  2197. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2198. iwl_hw_detect(priv);
  2199. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2200. priv->cfg->name, priv->hw_rev);
  2201. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2202. * PCI Tx retries from interfering with C3 CPU state */
  2203. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2204. /* amp init */
  2205. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2206. if (err < 0) {
  2207. IWL_ERR(priv, "Failed to init APMG\n");
  2208. goto out_iounmap;
  2209. }
  2210. /*****************
  2211. * 4. Read EEPROM
  2212. *****************/
  2213. /* Read the EEPROM */
  2214. err = iwl_eeprom_init(priv);
  2215. if (err) {
  2216. IWL_ERR(priv, "Unable to init EEPROM\n");
  2217. goto out_iounmap;
  2218. }
  2219. err = iwl_eeprom_check_version(priv);
  2220. if (err)
  2221. goto out_free_eeprom;
  2222. /* extract MAC Address */
  2223. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2224. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2225. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2226. /************************
  2227. * 5. Setup HW constants
  2228. ************************/
  2229. if (iwl_set_hw_params(priv)) {
  2230. IWL_ERR(priv, "failed to set hw parameters\n");
  2231. goto out_free_eeprom;
  2232. }
  2233. /*******************
  2234. * 6. Setup priv
  2235. *******************/
  2236. err = iwl_init_drv(priv);
  2237. if (err)
  2238. goto out_free_eeprom;
  2239. /* At this point both hw and priv are initialized. */
  2240. /********************
  2241. * 7. Setup services
  2242. ********************/
  2243. spin_lock_irqsave(&priv->lock, flags);
  2244. iwl_disable_interrupts(priv);
  2245. spin_unlock_irqrestore(&priv->lock, flags);
  2246. pci_enable_msi(priv->pci_dev);
  2247. err = request_irq(priv->pci_dev->irq, iwl_isr, IRQF_SHARED,
  2248. DRV_NAME, priv);
  2249. if (err) {
  2250. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2251. goto out_disable_msi;
  2252. }
  2253. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2254. if (err) {
  2255. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2256. goto out_free_irq;
  2257. }
  2258. iwl_setup_deferred_work(priv);
  2259. iwl_setup_rx_handlers(priv);
  2260. /**********************************
  2261. * 8. Setup and register mac80211
  2262. **********************************/
  2263. /* enable interrupts if needed: hw bug w/a */
  2264. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2265. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2266. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2267. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2268. }
  2269. iwl_enable_interrupts(priv);
  2270. err = iwl_setup_mac(priv);
  2271. if (err)
  2272. goto out_remove_sysfs;
  2273. err = iwl_dbgfs_register(priv, DRV_NAME);
  2274. if (err)
  2275. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2276. /* If platform's RF_KILL switch is NOT set to KILL */
  2277. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2278. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2279. else
  2280. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2281. err = iwl_rfkill_init(priv);
  2282. if (err)
  2283. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  2284. "Ignoring error: %d\n", err);
  2285. else
  2286. iwl_rfkill_set_hw_state(priv);
  2287. iwl_power_initialize(priv);
  2288. return 0;
  2289. out_remove_sysfs:
  2290. destroy_workqueue(priv->workqueue);
  2291. priv->workqueue = NULL;
  2292. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2293. out_free_irq:
  2294. free_irq(priv->pci_dev->irq, priv);
  2295. out_disable_msi:
  2296. pci_disable_msi(priv->pci_dev);
  2297. iwl_uninit_drv(priv);
  2298. out_free_eeprom:
  2299. iwl_eeprom_free(priv);
  2300. out_iounmap:
  2301. pci_iounmap(pdev, priv->hw_base);
  2302. out_pci_release_regions:
  2303. pci_set_drvdata(pdev, NULL);
  2304. pci_release_regions(pdev);
  2305. out_pci_disable_device:
  2306. pci_disable_device(pdev);
  2307. out_ieee80211_free_hw:
  2308. ieee80211_free_hw(priv->hw);
  2309. out:
  2310. return err;
  2311. }
  2312. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2313. {
  2314. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2315. unsigned long flags;
  2316. if (!priv)
  2317. return;
  2318. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2319. iwl_dbgfs_unregister(priv);
  2320. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2321. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2322. * to be called and iwl_down since we are removing the device
  2323. * we need to set STATUS_EXIT_PENDING bit.
  2324. */
  2325. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2326. if (priv->mac80211_registered) {
  2327. ieee80211_unregister_hw(priv->hw);
  2328. priv->mac80211_registered = 0;
  2329. } else {
  2330. iwl_down(priv);
  2331. }
  2332. /* make sure we flush any pending irq or
  2333. * tasklet for the driver
  2334. */
  2335. spin_lock_irqsave(&priv->lock, flags);
  2336. iwl_disable_interrupts(priv);
  2337. spin_unlock_irqrestore(&priv->lock, flags);
  2338. iwl_synchronize_irq(priv);
  2339. iwl_rfkill_unregister(priv);
  2340. iwl_dealloc_ucode_pci(priv);
  2341. if (priv->rxq.bd)
  2342. iwl_rx_queue_free(priv, &priv->rxq);
  2343. iwl_hw_txq_ctx_free(priv);
  2344. priv->cfg->ops->smgmt->clear_station_table(priv);
  2345. iwl_eeprom_free(priv);
  2346. /*netif_stop_queue(dev); */
  2347. flush_workqueue(priv->workqueue);
  2348. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2349. * priv->workqueue... so we can't take down the workqueue
  2350. * until now... */
  2351. destroy_workqueue(priv->workqueue);
  2352. priv->workqueue = NULL;
  2353. free_irq(priv->pci_dev->irq, priv);
  2354. pci_disable_msi(priv->pci_dev);
  2355. pci_iounmap(pdev, priv->hw_base);
  2356. pci_release_regions(pdev);
  2357. pci_disable_device(pdev);
  2358. pci_set_drvdata(pdev, NULL);
  2359. iwl_uninit_drv(priv);
  2360. if (priv->ibss_beacon)
  2361. dev_kfree_skb(priv->ibss_beacon);
  2362. ieee80211_free_hw(priv->hw);
  2363. }
  2364. /*****************************************************************************
  2365. *
  2366. * driver and module entry point
  2367. *
  2368. *****************************************************************************/
  2369. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2370. static struct pci_device_id iwl_hw_card_ids[] = {
  2371. #ifdef CONFIG_IWL4965
  2372. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2373. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2374. #endif /* CONFIG_IWL4965 */
  2375. #ifdef CONFIG_IWL5000
  2376. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2377. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2378. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2379. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2380. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2381. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2382. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2383. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2384. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2385. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2386. /* 5350 WiFi/WiMax */
  2387. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2388. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2389. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2390. /* 5150 Wifi/WiMax */
  2391. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2392. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2393. /* 6000/6050 Series */
  2394. {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
  2395. {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
  2396. {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
  2397. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2398. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2399. {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
  2400. {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2401. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2402. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2403. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2404. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2405. /* 1000 Series WiFi */
  2406. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2407. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2408. #endif /* CONFIG_IWL5000 */
  2409. {0}
  2410. };
  2411. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2412. static struct pci_driver iwl_driver = {
  2413. .name = DRV_NAME,
  2414. .id_table = iwl_hw_card_ids,
  2415. .probe = iwl_pci_probe,
  2416. .remove = __devexit_p(iwl_pci_remove),
  2417. #ifdef CONFIG_PM
  2418. .suspend = iwl_pci_suspend,
  2419. .resume = iwl_pci_resume,
  2420. #endif
  2421. };
  2422. static int __init iwl_init(void)
  2423. {
  2424. int ret;
  2425. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2426. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2427. ret = iwlagn_rate_control_register();
  2428. if (ret) {
  2429. printk(KERN_ERR DRV_NAME
  2430. "Unable to register rate control algorithm: %d\n", ret);
  2431. return ret;
  2432. }
  2433. ret = pci_register_driver(&iwl_driver);
  2434. if (ret) {
  2435. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2436. goto error_register;
  2437. }
  2438. return ret;
  2439. error_register:
  2440. iwlagn_rate_control_unregister();
  2441. return ret;
  2442. }
  2443. static void __exit iwl_exit(void)
  2444. {
  2445. pci_unregister_driver(&iwl_driver);
  2446. iwlagn_rate_control_unregister();
  2447. }
  2448. module_exit(iwl_exit);
  2449. module_init(iwl_init);