r8152.c 50 KB

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  1. /*
  2. * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/init.h>
  10. #include <linux/signal.h>
  11. #include <linux/slab.h>
  12. #include <linux/module.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/mii.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/usb.h>
  18. #include <linux/crc32.h>
  19. #include <linux/if_vlan.h>
  20. #include <linux/uaccess.h>
  21. #include <linux/list.h>
  22. #include <linux/ip.h>
  23. #include <linux/ipv6.h>
  24. /* Version Information */
  25. #define DRIVER_VERSION "v1.01.0 (2013/08/12)"
  26. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  27. #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
  28. #define MODULENAME "r8152"
  29. #define R8152_PHY_ID 32
  30. #define PLA_IDR 0xc000
  31. #define PLA_RCR 0xc010
  32. #define PLA_RMS 0xc016
  33. #define PLA_RXFIFO_CTRL0 0xc0a0
  34. #define PLA_RXFIFO_CTRL1 0xc0a4
  35. #define PLA_RXFIFO_CTRL2 0xc0a8
  36. #define PLA_FMC 0xc0b4
  37. #define PLA_CFG_WOL 0xc0b6
  38. #define PLA_MAR 0xcd00
  39. #define PAL_BDC_CR 0xd1a0
  40. #define PLA_LEDSEL 0xdd90
  41. #define PLA_LED_FEATURE 0xdd92
  42. #define PLA_PHYAR 0xde00
  43. #define PLA_GPHY_INTR_IMR 0xe022
  44. #define PLA_EEE_CR 0xe040
  45. #define PLA_EEEP_CR 0xe080
  46. #define PLA_MAC_PWR_CTRL 0xe0c0
  47. #define PLA_TCR0 0xe610
  48. #define PLA_TCR1 0xe612
  49. #define PLA_TXFIFO_CTRL 0xe618
  50. #define PLA_RSTTELLY 0xe800
  51. #define PLA_CR 0xe813
  52. #define PLA_CRWECR 0xe81c
  53. #define PLA_CONFIG5 0xe822
  54. #define PLA_PHY_PWR 0xe84c
  55. #define PLA_OOB_CTRL 0xe84f
  56. #define PLA_CPCR 0xe854
  57. #define PLA_MISC_0 0xe858
  58. #define PLA_MISC_1 0xe85a
  59. #define PLA_OCP_GPHY_BASE 0xe86c
  60. #define PLA_TELLYCNT 0xe890
  61. #define PLA_SFF_STS_7 0xe8de
  62. #define PLA_PHYSTATUS 0xe908
  63. #define PLA_BP_BA 0xfc26
  64. #define PLA_BP_0 0xfc28
  65. #define PLA_BP_1 0xfc2a
  66. #define PLA_BP_2 0xfc2c
  67. #define PLA_BP_3 0xfc2e
  68. #define PLA_BP_4 0xfc30
  69. #define PLA_BP_5 0xfc32
  70. #define PLA_BP_6 0xfc34
  71. #define PLA_BP_7 0xfc36
  72. #define USB_DEV_STAT 0xb808
  73. #define USB_USB_CTRL 0xd406
  74. #define USB_PHY_CTRL 0xd408
  75. #define USB_TX_AGG 0xd40a
  76. #define USB_RX_BUF_TH 0xd40c
  77. #define USB_USB_TIMER 0xd428
  78. #define USB_PM_CTRL_STATUS 0xd432
  79. #define USB_TX_DMA 0xd434
  80. #define USB_UPS_CTRL 0xd800
  81. #define USB_BP_BA 0xfc26
  82. #define USB_BP_0 0xfc28
  83. #define USB_BP_1 0xfc2a
  84. #define USB_BP_2 0xfc2c
  85. #define USB_BP_3 0xfc2e
  86. #define USB_BP_4 0xfc30
  87. #define USB_BP_5 0xfc32
  88. #define USB_BP_6 0xfc34
  89. #define USB_BP_7 0xfc36
  90. /* OCP Registers */
  91. #define OCP_ALDPS_CONFIG 0x2010
  92. #define OCP_EEE_CONFIG1 0x2080
  93. #define OCP_EEE_CONFIG2 0x2092
  94. #define OCP_EEE_CONFIG3 0x2094
  95. #define OCP_EEE_AR 0xa41a
  96. #define OCP_EEE_DATA 0xa41c
  97. /* PLA_RCR */
  98. #define RCR_AAP 0x00000001
  99. #define RCR_APM 0x00000002
  100. #define RCR_AM 0x00000004
  101. #define RCR_AB 0x00000008
  102. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  103. /* PLA_RXFIFO_CTRL0 */
  104. #define RXFIFO_THR1_NORMAL 0x00080002
  105. #define RXFIFO_THR1_OOB 0x01800003
  106. /* PLA_RXFIFO_CTRL1 */
  107. #define RXFIFO_THR2_FULL 0x00000060
  108. #define RXFIFO_THR2_HIGH 0x00000038
  109. #define RXFIFO_THR2_OOB 0x0000004a
  110. /* PLA_RXFIFO_CTRL2 */
  111. #define RXFIFO_THR3_FULL 0x00000078
  112. #define RXFIFO_THR3_HIGH 0x00000048
  113. #define RXFIFO_THR3_OOB 0x0000005a
  114. /* PLA_TXFIFO_CTRL */
  115. #define TXFIFO_THR_NORMAL 0x00400008
  116. /* PLA_FMC */
  117. #define FMC_FCR_MCU_EN 0x0001
  118. /* PLA_EEEP_CR */
  119. #define EEEP_CR_EEEP_TX 0x0002
  120. /* PLA_TCR0 */
  121. #define TCR0_TX_EMPTY 0x0800
  122. #define TCR0_AUTO_FIFO 0x0080
  123. /* PLA_TCR1 */
  124. #define VERSION_MASK 0x7cf0
  125. /* PLA_CR */
  126. #define CR_RST 0x10
  127. #define CR_RE 0x08
  128. #define CR_TE 0x04
  129. /* PLA_CRWECR */
  130. #define CRWECR_NORAML 0x00
  131. #define CRWECR_CONFIG 0xc0
  132. /* PLA_OOB_CTRL */
  133. #define NOW_IS_OOB 0x80
  134. #define TXFIFO_EMPTY 0x20
  135. #define RXFIFO_EMPTY 0x10
  136. #define LINK_LIST_READY 0x02
  137. #define DIS_MCU_CLROOB 0x01
  138. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  139. /* PLA_MISC_1 */
  140. #define RXDY_GATED_EN 0x0008
  141. /* PLA_SFF_STS_7 */
  142. #define RE_INIT_LL 0x8000
  143. #define MCU_BORW_EN 0x4000
  144. /* PLA_CPCR */
  145. #define CPCR_RX_VLAN 0x0040
  146. /* PLA_CFG_WOL */
  147. #define MAGIC_EN 0x0001
  148. /* PAL_BDC_CR */
  149. #define ALDPS_PROXY_MODE 0x0001
  150. /* PLA_CONFIG5 */
  151. #define LAN_WAKE_EN 0x0002
  152. /* PLA_LED_FEATURE */
  153. #define LED_MODE_MASK 0x0700
  154. /* PLA_PHY_PWR */
  155. #define TX_10M_IDLE_EN 0x0080
  156. #define PFM_PWM_SWITCH 0x0040
  157. /* PLA_MAC_PWR_CTRL */
  158. #define D3_CLK_GATED_EN 0x00004000
  159. #define MCU_CLK_RATIO 0x07010f07
  160. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  161. /* PLA_GPHY_INTR_IMR */
  162. #define GPHY_STS_MSK 0x0001
  163. #define SPEED_DOWN_MSK 0x0002
  164. #define SPDWN_RXDV_MSK 0x0004
  165. #define SPDWN_LINKCHG_MSK 0x0008
  166. /* PLA_PHYAR */
  167. #define PHYAR_FLAG 0x80000000
  168. /* PLA_EEE_CR */
  169. #define EEE_RX_EN 0x0001
  170. #define EEE_TX_EN 0x0002
  171. /* USB_DEV_STAT */
  172. #define STAT_SPEED_MASK 0x0006
  173. #define STAT_SPEED_HIGH 0x0000
  174. #define STAT_SPEED_FULL 0x0001
  175. /* USB_TX_AGG */
  176. #define TX_AGG_MAX_THRESHOLD 0x03
  177. /* USB_RX_BUF_TH */
  178. #define RX_BUF_THR 0x7a120180
  179. /* USB_TX_DMA */
  180. #define TEST_MODE_DISABLE 0x00000001
  181. #define TX_SIZE_ADJUST1 0x00000100
  182. /* USB_UPS_CTRL */
  183. #define POWER_CUT 0x0100
  184. /* USB_PM_CTRL_STATUS */
  185. #define RWSUME_INDICATE 0x0001
  186. /* USB_USB_CTRL */
  187. #define RX_AGG_DISABLE 0x0010
  188. /* OCP_ALDPS_CONFIG */
  189. #define ENPWRSAVE 0x8000
  190. #define ENPDNPS 0x0200
  191. #define LINKENA 0x0100
  192. #define DIS_SDSAVE 0x0010
  193. /* OCP_EEE_CONFIG1 */
  194. #define RG_TXLPI_MSK_HFDUP 0x8000
  195. #define RG_MATCLR_EN 0x4000
  196. #define EEE_10_CAP 0x2000
  197. #define EEE_NWAY_EN 0x1000
  198. #define TX_QUIET_EN 0x0200
  199. #define RX_QUIET_EN 0x0100
  200. #define SDRISETIME 0x0010 /* bit 4 ~ 6 */
  201. #define RG_RXLPI_MSK_HFDUP 0x0008
  202. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  203. /* OCP_EEE_CONFIG2 */
  204. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  205. #define RG_DACQUIET_EN 0x0400
  206. #define RG_LDVQUIET_EN 0x0200
  207. #define RG_CKRSEL 0x0020
  208. #define RG_EEEPRG_EN 0x0010
  209. /* OCP_EEE_CONFIG3 */
  210. #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
  211. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  212. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  213. /* OCP_EEE_AR */
  214. /* bit[15:14] function */
  215. #define FUN_ADDR 0x0000
  216. #define FUN_DATA 0x4000
  217. /* bit[4:0] device addr */
  218. #define DEVICE_ADDR 0x0007
  219. /* OCP_EEE_DATA */
  220. #define EEE_ADDR 0x003C
  221. #define EEE_DATA 0x0002
  222. enum rtl_register_content {
  223. _100bps = 0x08,
  224. _10bps = 0x04,
  225. LINK_STATUS = 0x02,
  226. FULL_DUP = 0x01,
  227. };
  228. #define RTL8152_MAX_TX 10
  229. #define RTL8152_MAX_RX 10
  230. #define INTBUFSIZE 2
  231. #define INTR_LINK 0x0004
  232. #define RTL8152_REQT_READ 0xc0
  233. #define RTL8152_REQT_WRITE 0x40
  234. #define RTL8152_REQ_GET_REGS 0x05
  235. #define RTL8152_REQ_SET_REGS 0x05
  236. #define BYTE_EN_DWORD 0xff
  237. #define BYTE_EN_WORD 0x33
  238. #define BYTE_EN_BYTE 0x11
  239. #define BYTE_EN_SIX_BYTES 0x3f
  240. #define BYTE_EN_START_MASK 0x0f
  241. #define BYTE_EN_END_MASK 0xf0
  242. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  243. #define RTL8152_TX_TIMEOUT (HZ)
  244. /* rtl8152 flags */
  245. enum rtl8152_flags {
  246. RTL8152_UNPLUG = 0,
  247. RTL8152_SET_RX_MODE,
  248. WORK_ENABLE,
  249. RTL8152_LINK_CHG,
  250. };
  251. /* Define these values to match your device */
  252. #define VENDOR_ID_REALTEK 0x0bda
  253. #define PRODUCT_ID_RTL8152 0x8152
  254. #define MCU_TYPE_PLA 0x0100
  255. #define MCU_TYPE_USB 0x0000
  256. struct rx_desc {
  257. u32 opts1;
  258. #define RX_LEN_MASK 0x7fff
  259. u32 opts2;
  260. u32 opts3;
  261. u32 opts4;
  262. u32 opts5;
  263. u32 opts6;
  264. };
  265. struct tx_desc {
  266. u32 opts1;
  267. #define TX_FS (1 << 31) /* First segment of a packet */
  268. #define TX_LS (1 << 30) /* Final segment of a packet */
  269. #define TX_LEN_MASK 0x3ffff
  270. u32 opts2;
  271. #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
  272. #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
  273. #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
  274. #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
  275. };
  276. struct rx_agg {
  277. struct list_head list;
  278. struct urb *urb;
  279. void *context;
  280. void *buffer;
  281. void *head;
  282. };
  283. struct tx_agg {
  284. struct list_head list;
  285. struct urb *urb;
  286. void *context;
  287. void *buffer;
  288. void *head;
  289. u32 skb_num;
  290. u32 skb_len;
  291. };
  292. struct r8152 {
  293. unsigned long flags;
  294. struct usb_device *udev;
  295. struct tasklet_struct tl;
  296. struct usb_interface *intf;
  297. struct net_device *netdev;
  298. struct urb *intr_urb;
  299. struct tx_agg tx_info[RTL8152_MAX_TX];
  300. struct rx_agg rx_info[RTL8152_MAX_RX];
  301. struct list_head rx_done, tx_free;
  302. struct sk_buff_head tx_queue;
  303. spinlock_t rx_lock, tx_lock;
  304. struct delayed_work schedule;
  305. struct mii_if_info mii;
  306. int intr_interval;
  307. u32 msg_enable;
  308. u16 ocp_base;
  309. u8 *intr_buff;
  310. u8 version;
  311. u8 speed;
  312. };
  313. enum rtl_version {
  314. RTL_VER_UNKNOWN = 0,
  315. RTL_VER_01,
  316. RTL_VER_02
  317. };
  318. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  319. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  320. */
  321. static const int multicast_filter_limit = 32;
  322. static unsigned int rx_buf_sz = 16384;
  323. static
  324. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  325. {
  326. int ret;
  327. void *tmp;
  328. tmp = kmalloc(size, GFP_KERNEL);
  329. if (!tmp)
  330. return -ENOMEM;
  331. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  332. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  333. value, index, tmp, size, 500);
  334. memcpy(data, tmp, size);
  335. kfree(tmp);
  336. return ret;
  337. }
  338. static
  339. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  340. {
  341. int ret;
  342. void *tmp;
  343. tmp = kmalloc(size, GFP_KERNEL);
  344. if (!tmp)
  345. return -ENOMEM;
  346. memcpy(tmp, data, size);
  347. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  348. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  349. value, index, tmp, size, 500);
  350. kfree(tmp);
  351. return ret;
  352. }
  353. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  354. void *data, u16 type)
  355. {
  356. u16 limit = 64;
  357. int ret = 0;
  358. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  359. return -ENODEV;
  360. /* both size and indix must be 4 bytes align */
  361. if ((size & 3) || !size || (index & 3) || !data)
  362. return -EPERM;
  363. if ((u32)index + (u32)size > 0xffff)
  364. return -EPERM;
  365. while (size) {
  366. if (size > limit) {
  367. ret = get_registers(tp, index, type, limit, data);
  368. if (ret < 0)
  369. break;
  370. index += limit;
  371. data += limit;
  372. size -= limit;
  373. } else {
  374. ret = get_registers(tp, index, type, size, data);
  375. if (ret < 0)
  376. break;
  377. index += size;
  378. data += size;
  379. size = 0;
  380. break;
  381. }
  382. }
  383. return ret;
  384. }
  385. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  386. u16 size, void *data, u16 type)
  387. {
  388. int ret;
  389. u16 byteen_start, byteen_end, byen;
  390. u16 limit = 512;
  391. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  392. return -ENODEV;
  393. /* both size and indix must be 4 bytes align */
  394. if ((size & 3) || !size || (index & 3) || !data)
  395. return -EPERM;
  396. if ((u32)index + (u32)size > 0xffff)
  397. return -EPERM;
  398. byteen_start = byteen & BYTE_EN_START_MASK;
  399. byteen_end = byteen & BYTE_EN_END_MASK;
  400. byen = byteen_start | (byteen_start << 4);
  401. ret = set_registers(tp, index, type | byen, 4, data);
  402. if (ret < 0)
  403. goto error1;
  404. index += 4;
  405. data += 4;
  406. size -= 4;
  407. if (size) {
  408. size -= 4;
  409. while (size) {
  410. if (size > limit) {
  411. ret = set_registers(tp, index,
  412. type | BYTE_EN_DWORD,
  413. limit, data);
  414. if (ret < 0)
  415. goto error1;
  416. index += limit;
  417. data += limit;
  418. size -= limit;
  419. } else {
  420. ret = set_registers(tp, index,
  421. type | BYTE_EN_DWORD,
  422. size, data);
  423. if (ret < 0)
  424. goto error1;
  425. index += size;
  426. data += size;
  427. size = 0;
  428. break;
  429. }
  430. }
  431. byen = byteen_end | (byteen_end >> 4);
  432. ret = set_registers(tp, index, type | byen, 4, data);
  433. if (ret < 0)
  434. goto error1;
  435. }
  436. error1:
  437. return ret;
  438. }
  439. static inline
  440. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  441. {
  442. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  443. }
  444. static inline
  445. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  446. {
  447. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  448. }
  449. static inline
  450. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  451. {
  452. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  453. }
  454. static inline
  455. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  456. {
  457. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  458. }
  459. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  460. {
  461. __le32 data;
  462. generic_ocp_read(tp, index, sizeof(data), &data, type);
  463. return __le32_to_cpu(data);
  464. }
  465. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  466. {
  467. __le32 tmp = __cpu_to_le32(data);
  468. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  469. }
  470. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  471. {
  472. u32 data;
  473. __le32 tmp;
  474. u8 shift = index & 2;
  475. index &= ~3;
  476. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  477. data = __le32_to_cpu(tmp);
  478. data >>= (shift * 8);
  479. data &= 0xffff;
  480. return (u16)data;
  481. }
  482. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  483. {
  484. u32 mask = 0xffff;
  485. __le32 tmp;
  486. u16 byen = BYTE_EN_WORD;
  487. u8 shift = index & 2;
  488. data &= mask;
  489. if (index & 2) {
  490. byen <<= shift;
  491. mask <<= (shift * 8);
  492. data <<= (shift * 8);
  493. index &= ~3;
  494. }
  495. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  496. data |= __le32_to_cpu(tmp) & ~mask;
  497. tmp = __cpu_to_le32(data);
  498. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  499. }
  500. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  501. {
  502. u32 data;
  503. __le32 tmp;
  504. u8 shift = index & 3;
  505. index &= ~3;
  506. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  507. data = __le32_to_cpu(tmp);
  508. data >>= (shift * 8);
  509. data &= 0xff;
  510. return (u8)data;
  511. }
  512. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  513. {
  514. u32 mask = 0xff;
  515. __le32 tmp;
  516. u16 byen = BYTE_EN_BYTE;
  517. u8 shift = index & 3;
  518. data &= mask;
  519. if (index & 3) {
  520. byen <<= shift;
  521. mask <<= (shift * 8);
  522. data <<= (shift * 8);
  523. index &= ~3;
  524. }
  525. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  526. data |= __le32_to_cpu(tmp) & ~mask;
  527. tmp = __cpu_to_le32(data);
  528. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  529. }
  530. static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  531. {
  532. u32 ocp_data;
  533. int i;
  534. ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) |
  535. (value & 0xffff);
  536. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  537. for (i = 20; i > 0; i--) {
  538. udelay(25);
  539. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  540. if (!(ocp_data & PHYAR_FLAG))
  541. break;
  542. }
  543. udelay(20);
  544. }
  545. static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  546. {
  547. u32 ocp_data;
  548. int i;
  549. ocp_data = (reg_addr & 0x1f) << 16;
  550. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  551. for (i = 20; i > 0; i--) {
  552. udelay(25);
  553. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  554. if (ocp_data & PHYAR_FLAG)
  555. break;
  556. }
  557. udelay(20);
  558. if (!(ocp_data & PHYAR_FLAG))
  559. return -EAGAIN;
  560. return (u16)(ocp_data & 0xffff);
  561. }
  562. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  563. {
  564. struct r8152 *tp = netdev_priv(netdev);
  565. if (phy_id != R8152_PHY_ID)
  566. return -EINVAL;
  567. return r8152_mdio_read(tp, reg);
  568. }
  569. static
  570. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  571. {
  572. struct r8152 *tp = netdev_priv(netdev);
  573. if (phy_id != R8152_PHY_ID)
  574. return;
  575. r8152_mdio_write(tp, reg, val);
  576. }
  577. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  578. {
  579. u16 ocp_base, ocp_index;
  580. ocp_base = addr & 0xf000;
  581. if (ocp_base != tp->ocp_base) {
  582. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  583. tp->ocp_base = ocp_base;
  584. }
  585. ocp_index = (addr & 0x0fff) | 0xb000;
  586. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  587. }
  588. static
  589. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  590. static inline void set_ethernet_addr(struct r8152 *tp)
  591. {
  592. struct net_device *dev = tp->netdev;
  593. u8 node_id[8] = {0};
  594. if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
  595. netif_notice(tp, probe, dev, "inet addr fail\n");
  596. else {
  597. memcpy(dev->dev_addr, node_id, dev->addr_len);
  598. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  599. }
  600. }
  601. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  602. {
  603. struct r8152 *tp = netdev_priv(netdev);
  604. struct sockaddr *addr = p;
  605. if (!is_valid_ether_addr(addr->sa_data))
  606. return -EADDRNOTAVAIL;
  607. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  608. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  609. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  610. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  611. return 0;
  612. }
  613. static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
  614. {
  615. return &dev->stats;
  616. }
  617. static void read_bulk_callback(struct urb *urb)
  618. {
  619. struct net_device *netdev;
  620. unsigned long lockflags;
  621. int status = urb->status;
  622. struct rx_agg *agg;
  623. struct r8152 *tp;
  624. int result;
  625. agg = urb->context;
  626. if (!agg)
  627. return;
  628. tp = agg->context;
  629. if (!tp)
  630. return;
  631. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  632. return;
  633. if (!test_bit(WORK_ENABLE, &tp->flags))
  634. return;
  635. netdev = tp->netdev;
  636. if (!netif_carrier_ok(netdev))
  637. return;
  638. switch (status) {
  639. case 0:
  640. if (urb->actual_length < ETH_ZLEN)
  641. break;
  642. spin_lock_irqsave(&tp->rx_lock, lockflags);
  643. list_add_tail(&agg->list, &tp->rx_done);
  644. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  645. tasklet_schedule(&tp->tl);
  646. return;
  647. case -ESHUTDOWN:
  648. set_bit(RTL8152_UNPLUG, &tp->flags);
  649. netif_device_detach(tp->netdev);
  650. return;
  651. case -ENOENT:
  652. return; /* the urb is in unlink state */
  653. case -ETIME:
  654. pr_warn_ratelimited("may be reset is needed?..\n");
  655. break;
  656. default:
  657. pr_warn_ratelimited("Rx status %d\n", status);
  658. break;
  659. }
  660. result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  661. if (result == -ENODEV) {
  662. netif_device_detach(tp->netdev);
  663. } else if (result) {
  664. spin_lock_irqsave(&tp->rx_lock, lockflags);
  665. list_add_tail(&agg->list, &tp->rx_done);
  666. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  667. tasklet_schedule(&tp->tl);
  668. }
  669. }
  670. static void write_bulk_callback(struct urb *urb)
  671. {
  672. struct net_device_stats *stats;
  673. unsigned long lockflags;
  674. struct tx_agg *agg;
  675. struct r8152 *tp;
  676. int status = urb->status;
  677. agg = urb->context;
  678. if (!agg)
  679. return;
  680. tp = agg->context;
  681. if (!tp)
  682. return;
  683. stats = rtl8152_get_stats(tp->netdev);
  684. if (status) {
  685. pr_warn_ratelimited("Tx status %d\n", status);
  686. stats->tx_errors += agg->skb_num;
  687. } else {
  688. stats->tx_packets += agg->skb_num;
  689. stats->tx_bytes += agg->skb_len;
  690. }
  691. spin_lock_irqsave(&tp->tx_lock, lockflags);
  692. list_add_tail(&agg->list, &tp->tx_free);
  693. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  694. if (!netif_carrier_ok(tp->netdev))
  695. return;
  696. if (!test_bit(WORK_ENABLE, &tp->flags))
  697. return;
  698. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  699. return;
  700. if (!skb_queue_empty(&tp->tx_queue))
  701. tasklet_schedule(&tp->tl);
  702. }
  703. static void intr_callback(struct urb *urb)
  704. {
  705. struct r8152 *tp;
  706. __u16 *d;
  707. int status = urb->status;
  708. int res;
  709. tp = urb->context;
  710. if (!tp)
  711. return;
  712. if (!test_bit(WORK_ENABLE, &tp->flags))
  713. return;
  714. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  715. return;
  716. switch (status) {
  717. case 0: /* success */
  718. break;
  719. case -ECONNRESET: /* unlink */
  720. case -ESHUTDOWN:
  721. netif_device_detach(tp->netdev);
  722. case -ENOENT:
  723. return;
  724. case -EOVERFLOW:
  725. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  726. goto resubmit;
  727. /* -EPIPE: should clear the halt */
  728. default:
  729. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  730. goto resubmit;
  731. }
  732. d = urb->transfer_buffer;
  733. if (INTR_LINK & __le16_to_cpu(d[0])) {
  734. if (!(tp->speed & LINK_STATUS)) {
  735. set_bit(RTL8152_LINK_CHG, &tp->flags);
  736. schedule_delayed_work(&tp->schedule, 0);
  737. }
  738. } else {
  739. if (tp->speed & LINK_STATUS) {
  740. set_bit(RTL8152_LINK_CHG, &tp->flags);
  741. schedule_delayed_work(&tp->schedule, 0);
  742. }
  743. }
  744. resubmit:
  745. res = usb_submit_urb(urb, GFP_ATOMIC);
  746. if (res == -ENODEV)
  747. netif_device_detach(tp->netdev);
  748. else if (res)
  749. netif_err(tp, intr, tp->netdev,
  750. "can't resubmit intr, status %d\n", res);
  751. }
  752. static inline void *rx_agg_align(void *data)
  753. {
  754. return (void *)ALIGN((uintptr_t)data, 8);
  755. }
  756. static inline void *tx_agg_align(void *data)
  757. {
  758. return (void *)ALIGN((uintptr_t)data, 4);
  759. }
  760. static void free_all_mem(struct r8152 *tp)
  761. {
  762. int i;
  763. for (i = 0; i < RTL8152_MAX_RX; i++) {
  764. if (tp->rx_info[i].urb) {
  765. usb_free_urb(tp->rx_info[i].urb);
  766. tp->rx_info[i].urb = NULL;
  767. }
  768. if (tp->rx_info[i].buffer) {
  769. kfree(tp->rx_info[i].buffer);
  770. tp->rx_info[i].buffer = NULL;
  771. tp->rx_info[i].head = NULL;
  772. }
  773. }
  774. for (i = 0; i < RTL8152_MAX_TX; i++) {
  775. if (tp->tx_info[i].urb) {
  776. usb_free_urb(tp->tx_info[i].urb);
  777. tp->tx_info[i].urb = NULL;
  778. }
  779. if (tp->tx_info[i].buffer) {
  780. kfree(tp->tx_info[i].buffer);
  781. tp->tx_info[i].buffer = NULL;
  782. tp->tx_info[i].head = NULL;
  783. }
  784. }
  785. if (tp->intr_urb) {
  786. usb_free_urb(tp->intr_urb);
  787. tp->intr_urb = NULL;
  788. }
  789. if (tp->intr_buff) {
  790. kfree(tp->intr_buff);
  791. tp->intr_buff = NULL;
  792. }
  793. }
  794. static int alloc_all_mem(struct r8152 *tp)
  795. {
  796. struct net_device *netdev = tp->netdev;
  797. struct usb_interface *intf = tp->intf;
  798. struct usb_host_interface *alt = intf->cur_altsetting;
  799. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  800. struct urb *urb;
  801. int node, i;
  802. u8 *buf;
  803. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  804. spin_lock_init(&tp->rx_lock);
  805. spin_lock_init(&tp->tx_lock);
  806. INIT_LIST_HEAD(&tp->rx_done);
  807. INIT_LIST_HEAD(&tp->tx_free);
  808. skb_queue_head_init(&tp->tx_queue);
  809. for (i = 0; i < RTL8152_MAX_RX; i++) {
  810. buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  811. if (!buf)
  812. goto err1;
  813. if (buf != rx_agg_align(buf)) {
  814. kfree(buf);
  815. buf = kmalloc_node(rx_buf_sz + 8, GFP_KERNEL, node);
  816. if (!buf)
  817. goto err1;
  818. }
  819. urb = usb_alloc_urb(0, GFP_KERNEL);
  820. if (!urb) {
  821. kfree(buf);
  822. goto err1;
  823. }
  824. INIT_LIST_HEAD(&tp->rx_info[i].list);
  825. tp->rx_info[i].context = tp;
  826. tp->rx_info[i].urb = urb;
  827. tp->rx_info[i].buffer = buf;
  828. tp->rx_info[i].head = rx_agg_align(buf);
  829. }
  830. for (i = 0; i < RTL8152_MAX_TX; i++) {
  831. buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  832. if (!buf)
  833. goto err1;
  834. if (buf != tx_agg_align(buf)) {
  835. kfree(buf);
  836. buf = kmalloc_node(rx_buf_sz + 4, GFP_KERNEL, node);
  837. if (!buf)
  838. goto err1;
  839. }
  840. urb = usb_alloc_urb(0, GFP_KERNEL);
  841. if (!urb) {
  842. kfree(buf);
  843. goto err1;
  844. }
  845. INIT_LIST_HEAD(&tp->tx_info[i].list);
  846. tp->tx_info[i].context = tp;
  847. tp->tx_info[i].urb = urb;
  848. tp->tx_info[i].buffer = buf;
  849. tp->tx_info[i].head = tx_agg_align(buf);
  850. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  851. }
  852. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  853. if (!tp->intr_urb)
  854. goto err1;
  855. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  856. if (!tp->intr_buff)
  857. goto err1;
  858. tp->intr_interval = (int)ep_intr->desc.bInterval;
  859. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  860. tp->intr_buff, INTBUFSIZE, intr_callback,
  861. tp, tp->intr_interval);
  862. return 0;
  863. err1:
  864. free_all_mem(tp);
  865. return -ENOMEM;
  866. }
  867. static void
  868. r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
  869. {
  870. memset(desc, 0, sizeof(*desc));
  871. desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
  872. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  873. __be16 protocol;
  874. u8 ip_protocol;
  875. u32 opts2 = 0;
  876. if (skb->protocol == htons(ETH_P_8021Q))
  877. protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
  878. else
  879. protocol = skb->protocol;
  880. switch (protocol) {
  881. case htons(ETH_P_IP):
  882. opts2 |= IPV4_CS;
  883. ip_protocol = ip_hdr(skb)->protocol;
  884. break;
  885. case htons(ETH_P_IPV6):
  886. opts2 |= IPV6_CS;
  887. ip_protocol = ipv6_hdr(skb)->nexthdr;
  888. break;
  889. default:
  890. ip_protocol = IPPROTO_RAW;
  891. break;
  892. }
  893. if (ip_protocol == IPPROTO_TCP) {
  894. opts2 |= TCP_CS;
  895. opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
  896. } else if (ip_protocol == IPPROTO_UDP) {
  897. opts2 |= UDP_CS;
  898. } else {
  899. WARN_ON_ONCE(1);
  900. }
  901. desc->opts2 = cpu_to_le32(opts2);
  902. }
  903. }
  904. static void rx_bottom(struct r8152 *tp)
  905. {
  906. struct net_device_stats *stats;
  907. struct net_device *netdev;
  908. struct rx_agg *agg;
  909. struct rx_desc *rx_desc;
  910. unsigned long lockflags;
  911. struct list_head *cursor, *next;
  912. struct sk_buff *skb;
  913. struct urb *urb;
  914. unsigned pkt_len;
  915. int len_used;
  916. u8 *rx_data;
  917. int ret;
  918. netdev = tp->netdev;
  919. stats = rtl8152_get_stats(netdev);
  920. spin_lock_irqsave(&tp->rx_lock, lockflags);
  921. list_for_each_safe(cursor, next, &tp->rx_done) {
  922. list_del_init(cursor);
  923. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  924. agg = list_entry(cursor, struct rx_agg, list);
  925. urb = agg->urb;
  926. if (urb->actual_length < ETH_ZLEN) {
  927. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  928. spin_lock_irqsave(&tp->rx_lock, lockflags);
  929. if (ret && ret != -ENODEV) {
  930. list_add_tail(&agg->list, next);
  931. tasklet_schedule(&tp->tl);
  932. }
  933. continue;
  934. }
  935. len_used = 0;
  936. rx_desc = agg->head;
  937. rx_data = agg->head;
  938. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  939. len_used += sizeof(struct rx_desc) + pkt_len;
  940. while (urb->actual_length >= len_used) {
  941. if (pkt_len < ETH_ZLEN)
  942. break;
  943. pkt_len -= 4; /* CRC */
  944. rx_data += sizeof(struct rx_desc);
  945. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  946. if (!skb) {
  947. stats->rx_dropped++;
  948. break;
  949. }
  950. memcpy(skb->data, rx_data, pkt_len);
  951. skb_put(skb, pkt_len);
  952. skb->protocol = eth_type_trans(skb, netdev);
  953. netif_rx(skb);
  954. stats->rx_packets++;
  955. stats->rx_bytes += pkt_len;
  956. rx_data = rx_agg_align(rx_data + pkt_len + 4);
  957. rx_desc = (struct rx_desc *)rx_data;
  958. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  959. len_used = (int)(rx_data - (u8 *)agg->head);
  960. len_used += sizeof(struct rx_desc) + pkt_len;
  961. }
  962. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  963. spin_lock_irqsave(&tp->rx_lock, lockflags);
  964. if (ret && ret != -ENODEV) {
  965. list_add_tail(&agg->list, next);
  966. tasklet_schedule(&tp->tl);
  967. }
  968. }
  969. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  970. }
  971. static void tx_bottom(struct r8152 *tp)
  972. {
  973. struct net_device_stats *stats;
  974. struct net_device *netdev;
  975. struct tx_agg *agg;
  976. unsigned long lockflags;
  977. u32 remain, total;
  978. u8 *tx_data;
  979. int res;
  980. netdev = tp->netdev;
  981. next_agg:
  982. agg = NULL;
  983. spin_lock_irqsave(&tp->tx_lock, lockflags);
  984. if (!skb_queue_empty(&tp->tx_queue) && !list_empty(&tp->tx_free)) {
  985. struct list_head *cursor;
  986. cursor = tp->tx_free.next;
  987. list_del_init(cursor);
  988. agg = list_entry(cursor, struct tx_agg, list);
  989. }
  990. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  991. if (!agg)
  992. return;
  993. tx_data = agg->head;
  994. agg->skb_num = agg->skb_len = 0;
  995. remain = rx_buf_sz - sizeof(struct tx_desc);
  996. total = 0;
  997. while (remain >= ETH_ZLEN) {
  998. struct tx_desc *tx_desc;
  999. struct sk_buff *skb;
  1000. unsigned int len;
  1001. skb = skb_dequeue(&tp->tx_queue);
  1002. if (!skb)
  1003. break;
  1004. len = skb->len;
  1005. if (remain < len) {
  1006. skb_queue_head(&tp->tx_queue, skb);
  1007. break;
  1008. }
  1009. tx_data = tx_agg_align(tx_data);
  1010. tx_desc = (struct tx_desc *)tx_data;
  1011. tx_data += sizeof(*tx_desc);
  1012. r8152_tx_csum(tp, tx_desc, skb);
  1013. memcpy(tx_data, skb->data, len);
  1014. agg->skb_num++;
  1015. agg->skb_len += len;
  1016. dev_kfree_skb_any(skb);
  1017. tx_data += len;
  1018. remain = rx_buf_sz - sizeof(*tx_desc) -
  1019. (u32)(tx_agg_align(tx_data) - agg->head);
  1020. }
  1021. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1022. agg->head, (int)(tx_data - (u8 *)agg->head),
  1023. (usb_complete_t)write_bulk_callback, agg);
  1024. res = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1025. stats = rtl8152_get_stats(netdev);
  1026. if (res) {
  1027. /* Can we get/handle EPIPE here? */
  1028. if (res == -ENODEV) {
  1029. netif_device_detach(netdev);
  1030. } else {
  1031. netif_warn(tp, tx_err, netdev,
  1032. "failed tx_urb %d\n", res);
  1033. stats->tx_dropped += agg->skb_num;
  1034. spin_lock_irqsave(&tp->tx_lock, lockflags);
  1035. list_add_tail(&agg->list, &tp->tx_free);
  1036. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  1037. }
  1038. return;
  1039. }
  1040. goto next_agg;
  1041. }
  1042. static void bottom_half(unsigned long data)
  1043. {
  1044. struct r8152 *tp;
  1045. tp = (struct r8152 *)data;
  1046. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1047. return;
  1048. if (!test_bit(WORK_ENABLE, &tp->flags))
  1049. return;
  1050. if (!netif_carrier_ok(tp->netdev))
  1051. return;
  1052. rx_bottom(tp);
  1053. tx_bottom(tp);
  1054. }
  1055. static
  1056. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1057. {
  1058. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1059. agg->head, rx_buf_sz,
  1060. (usb_complete_t)read_bulk_callback, agg);
  1061. return usb_submit_urb(agg->urb, mem_flags);
  1062. }
  1063. static void rtl8152_tx_timeout(struct net_device *netdev)
  1064. {
  1065. struct r8152 *tp = netdev_priv(netdev);
  1066. int i;
  1067. netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
  1068. for (i = 0; i < RTL8152_MAX_TX; i++)
  1069. usb_unlink_urb(tp->tx_info[i].urb);
  1070. }
  1071. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1072. {
  1073. struct r8152 *tp = netdev_priv(netdev);
  1074. if (tp->speed & LINK_STATUS) {
  1075. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1076. schedule_delayed_work(&tp->schedule, 0);
  1077. }
  1078. }
  1079. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1080. {
  1081. struct r8152 *tp = netdev_priv(netdev);
  1082. u32 mc_filter[2]; /* Multicast hash filter */
  1083. __le32 tmp[2];
  1084. u32 ocp_data;
  1085. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1086. netif_stop_queue(netdev);
  1087. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1088. ocp_data &= ~RCR_ACPT_ALL;
  1089. ocp_data |= RCR_AB | RCR_APM;
  1090. if (netdev->flags & IFF_PROMISC) {
  1091. /* Unconditionally log net taps. */
  1092. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1093. ocp_data |= RCR_AM | RCR_AAP;
  1094. mc_filter[1] = mc_filter[0] = 0xffffffff;
  1095. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1096. (netdev->flags & IFF_ALLMULTI)) {
  1097. /* Too many to filter perfectly -- accept all multicasts. */
  1098. ocp_data |= RCR_AM;
  1099. mc_filter[1] = mc_filter[0] = 0xffffffff;
  1100. } else {
  1101. struct netdev_hw_addr *ha;
  1102. mc_filter[1] = mc_filter[0] = 0;
  1103. netdev_for_each_mc_addr(ha, netdev) {
  1104. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1105. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1106. ocp_data |= RCR_AM;
  1107. }
  1108. }
  1109. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1110. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1111. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1112. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1113. netif_wake_queue(netdev);
  1114. }
  1115. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1116. struct net_device *netdev)
  1117. {
  1118. struct r8152 *tp = netdev_priv(netdev);
  1119. struct net_device_stats *stats = rtl8152_get_stats(netdev);
  1120. unsigned long lockflags;
  1121. struct tx_agg *agg = NULL;
  1122. struct tx_desc *tx_desc;
  1123. unsigned int len;
  1124. u8 *tx_data;
  1125. int res;
  1126. skb_tx_timestamp(skb);
  1127. spin_lock_irqsave(&tp->tx_lock, lockflags);
  1128. if (!list_empty(&tp->tx_free) && skb_queue_empty(&tp->tx_queue)) {
  1129. struct list_head *cursor;
  1130. cursor = tp->tx_free.next;
  1131. list_del_init(cursor);
  1132. agg = list_entry(cursor, struct tx_agg, list);
  1133. }
  1134. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  1135. if (!agg) {
  1136. skb_queue_tail(&tp->tx_queue, skb);
  1137. return NETDEV_TX_OK;
  1138. }
  1139. tx_desc = (struct tx_desc *)agg->head;
  1140. tx_data = agg->head + sizeof(*tx_desc);
  1141. agg->skb_num = agg->skb_len = 0;
  1142. len = skb->len;
  1143. r8152_tx_csum(tp, tx_desc, skb);
  1144. memcpy(tx_data, skb->data, len);
  1145. dev_kfree_skb_any(skb);
  1146. agg->skb_num++;
  1147. agg->skb_len += len;
  1148. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1149. agg->head, len + sizeof(*tx_desc),
  1150. (usb_complete_t)write_bulk_callback, agg);
  1151. res = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1152. if (res) {
  1153. /* Can we get/handle EPIPE here? */
  1154. if (res == -ENODEV) {
  1155. netif_device_detach(tp->netdev);
  1156. } else {
  1157. netif_warn(tp, tx_err, netdev,
  1158. "failed tx_urb %d\n", res);
  1159. stats->tx_dropped++;
  1160. spin_lock_irqsave(&tp->tx_lock, lockflags);
  1161. list_add_tail(&agg->list, &tp->tx_free);
  1162. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  1163. }
  1164. }
  1165. return NETDEV_TX_OK;
  1166. }
  1167. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1168. {
  1169. u32 ocp_data;
  1170. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1171. ocp_data &= ~FMC_FCR_MCU_EN;
  1172. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1173. ocp_data |= FMC_FCR_MCU_EN;
  1174. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1175. }
  1176. static void rtl8152_nic_reset(struct r8152 *tp)
  1177. {
  1178. int i;
  1179. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1180. for (i = 0; i < 1000; i++) {
  1181. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1182. break;
  1183. udelay(100);
  1184. }
  1185. }
  1186. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1187. {
  1188. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1189. }
  1190. static int rtl8152_enable(struct r8152 *tp)
  1191. {
  1192. u32 ocp_data;
  1193. int i, ret;
  1194. u8 speed;
  1195. speed = rtl8152_get_speed(tp);
  1196. if (speed & _10bps) {
  1197. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1198. ocp_data |= EEEP_CR_EEEP_TX;
  1199. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1200. } else {
  1201. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1202. ocp_data &= ~EEEP_CR_EEEP_TX;
  1203. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1204. }
  1205. r8152b_reset_packet_filter(tp);
  1206. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1207. ocp_data |= CR_RE | CR_TE;
  1208. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1209. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1210. ocp_data &= ~RXDY_GATED_EN;
  1211. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1212. INIT_LIST_HEAD(&tp->rx_done);
  1213. ret = 0;
  1214. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1215. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1216. ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1217. }
  1218. return ret;
  1219. }
  1220. static void rtl8152_disable(struct r8152 *tp)
  1221. {
  1222. struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
  1223. struct sk_buff *skb;
  1224. u32 ocp_data;
  1225. int i;
  1226. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1227. ocp_data &= ~RCR_ACPT_ALL;
  1228. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1229. while ((skb = skb_dequeue(&tp->tx_queue))) {
  1230. dev_kfree_skb(skb);
  1231. stats->tx_dropped++;
  1232. }
  1233. for (i = 0; i < RTL8152_MAX_TX; i++)
  1234. usb_kill_urb(tp->tx_info[i].urb);
  1235. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1236. ocp_data |= RXDY_GATED_EN;
  1237. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1238. for (i = 0; i < 1000; i++) {
  1239. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1240. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1241. break;
  1242. mdelay(1);
  1243. }
  1244. for (i = 0; i < 1000; i++) {
  1245. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1246. break;
  1247. mdelay(1);
  1248. }
  1249. for (i = 0; i < RTL8152_MAX_RX; i++)
  1250. usb_kill_urb(tp->rx_info[i].urb);
  1251. rtl8152_nic_reset(tp);
  1252. }
  1253. static void r8152b_exit_oob(struct r8152 *tp)
  1254. {
  1255. u32 ocp_data;
  1256. int i;
  1257. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1258. ocp_data &= ~RCR_ACPT_ALL;
  1259. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1260. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1261. ocp_data |= RXDY_GATED_EN;
  1262. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1263. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1264. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  1265. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1266. ocp_data &= ~NOW_IS_OOB;
  1267. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1268. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1269. ocp_data &= ~MCU_BORW_EN;
  1270. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1271. for (i = 0; i < 1000; i++) {
  1272. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1273. if (ocp_data & LINK_LIST_READY)
  1274. break;
  1275. mdelay(1);
  1276. }
  1277. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1278. ocp_data |= RE_INIT_LL;
  1279. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1280. for (i = 0; i < 1000; i++) {
  1281. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1282. if (ocp_data & LINK_LIST_READY)
  1283. break;
  1284. mdelay(1);
  1285. }
  1286. rtl8152_nic_reset(tp);
  1287. /* rx share fifo credit full threshold */
  1288. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  1289. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
  1290. ocp_data &= STAT_SPEED_MASK;
  1291. if (ocp_data == STAT_SPEED_FULL) {
  1292. /* rx share fifo credit near full threshold */
  1293. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1294. RXFIFO_THR2_FULL);
  1295. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1296. RXFIFO_THR3_FULL);
  1297. } else {
  1298. /* rx share fifo credit near full threshold */
  1299. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1300. RXFIFO_THR2_HIGH);
  1301. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1302. RXFIFO_THR3_HIGH);
  1303. }
  1304. /* TX share fifo free credit full threshold */
  1305. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  1306. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  1307. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR);
  1308. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  1309. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  1310. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1311. ocp_data &= ~CPCR_RX_VLAN;
  1312. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1313. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1314. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  1315. ocp_data |= TCR0_AUTO_FIFO;
  1316. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  1317. }
  1318. static void r8152b_enter_oob(struct r8152 *tp)
  1319. {
  1320. u32 ocp_data;
  1321. int i;
  1322. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1323. ocp_data &= ~NOW_IS_OOB;
  1324. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1325. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  1326. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  1327. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  1328. rtl8152_disable(tp);
  1329. for (i = 0; i < 1000; i++) {
  1330. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1331. if (ocp_data & LINK_LIST_READY)
  1332. break;
  1333. mdelay(1);
  1334. }
  1335. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1336. ocp_data |= RE_INIT_LL;
  1337. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1338. for (i = 0; i < 1000; i++) {
  1339. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1340. if (ocp_data & LINK_LIST_READY)
  1341. break;
  1342. mdelay(1);
  1343. }
  1344. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1345. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1346. ocp_data |= MAGIC_EN;
  1347. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1348. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1349. ocp_data |= CPCR_RX_VLAN;
  1350. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1351. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  1352. ocp_data |= ALDPS_PROXY_MODE;
  1353. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  1354. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1355. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  1356. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1357. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
  1358. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1359. ocp_data &= ~RXDY_GATED_EN;
  1360. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1361. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1362. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  1363. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1364. }
  1365. static void r8152b_disable_aldps(struct r8152 *tp)
  1366. {
  1367. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1368. msleep(20);
  1369. }
  1370. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1371. {
  1372. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1373. LINKENA | DIS_SDSAVE);
  1374. }
  1375. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  1376. {
  1377. u16 bmcr, anar;
  1378. int ret = 0;
  1379. cancel_delayed_work_sync(&tp->schedule);
  1380. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1381. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  1382. ADVERTISE_100HALF | ADVERTISE_100FULL);
  1383. if (autoneg == AUTONEG_DISABLE) {
  1384. if (speed == SPEED_10) {
  1385. bmcr = 0;
  1386. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1387. } else if (speed == SPEED_100) {
  1388. bmcr = BMCR_SPEED100;
  1389. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1390. } else {
  1391. ret = -EINVAL;
  1392. goto out;
  1393. }
  1394. if (duplex == DUPLEX_FULL)
  1395. bmcr |= BMCR_FULLDPLX;
  1396. } else {
  1397. if (speed == SPEED_10) {
  1398. if (duplex == DUPLEX_FULL)
  1399. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1400. else
  1401. anar |= ADVERTISE_10HALF;
  1402. } else if (speed == SPEED_100) {
  1403. if (duplex == DUPLEX_FULL) {
  1404. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1405. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1406. } else {
  1407. anar |= ADVERTISE_10HALF;
  1408. anar |= ADVERTISE_100HALF;
  1409. }
  1410. } else {
  1411. ret = -EINVAL;
  1412. goto out;
  1413. }
  1414. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  1415. }
  1416. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1417. r8152_mdio_write(tp, MII_BMCR, bmcr);
  1418. out:
  1419. return ret;
  1420. }
  1421. static void rtl8152_down(struct r8152 *tp)
  1422. {
  1423. u32 ocp_data;
  1424. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1425. ocp_data &= ~POWER_CUT;
  1426. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1427. r8152b_disable_aldps(tp);
  1428. r8152b_enter_oob(tp);
  1429. r8152b_enable_aldps(tp);
  1430. }
  1431. static void set_carrier(struct r8152 *tp)
  1432. {
  1433. struct net_device *netdev = tp->netdev;
  1434. u8 speed;
  1435. clear_bit(RTL8152_LINK_CHG, &tp->flags);
  1436. speed = rtl8152_get_speed(tp);
  1437. if (speed & LINK_STATUS) {
  1438. if (!(tp->speed & LINK_STATUS)) {
  1439. rtl8152_enable(tp);
  1440. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1441. netif_carrier_on(netdev);
  1442. }
  1443. } else {
  1444. if (tp->speed & LINK_STATUS) {
  1445. netif_carrier_off(netdev);
  1446. tasklet_disable(&tp->tl);
  1447. rtl8152_disable(tp);
  1448. tasklet_enable(&tp->tl);
  1449. }
  1450. }
  1451. tp->speed = speed;
  1452. }
  1453. static void rtl_work_func_t(struct work_struct *work)
  1454. {
  1455. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  1456. if (!test_bit(WORK_ENABLE, &tp->flags))
  1457. goto out1;
  1458. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1459. goto out1;
  1460. if (test_bit(RTL8152_LINK_CHG, &tp->flags))
  1461. set_carrier(tp);
  1462. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  1463. _rtl8152_set_rx_mode(tp->netdev);
  1464. out1:
  1465. return;
  1466. }
  1467. static int rtl8152_open(struct net_device *netdev)
  1468. {
  1469. struct r8152 *tp = netdev_priv(netdev);
  1470. int res = 0;
  1471. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  1472. if (res) {
  1473. if (res == -ENODEV)
  1474. netif_device_detach(tp->netdev);
  1475. netif_warn(tp, ifup, netdev,
  1476. "intr_urb submit failed: %d\n", res);
  1477. return res;
  1478. }
  1479. rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
  1480. tp->speed = 0;
  1481. netif_carrier_off(netdev);
  1482. netif_start_queue(netdev);
  1483. set_bit(WORK_ENABLE, &tp->flags);
  1484. return res;
  1485. }
  1486. static int rtl8152_close(struct net_device *netdev)
  1487. {
  1488. struct r8152 *tp = netdev_priv(netdev);
  1489. int res = 0;
  1490. usb_kill_urb(tp->intr_urb);
  1491. clear_bit(WORK_ENABLE, &tp->flags);
  1492. cancel_delayed_work_sync(&tp->schedule);
  1493. netif_stop_queue(netdev);
  1494. tasklet_disable(&tp->tl);
  1495. rtl8152_disable(tp);
  1496. tasklet_enable(&tp->tl);
  1497. return res;
  1498. }
  1499. static void rtl_clear_bp(struct r8152 *tp)
  1500. {
  1501. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
  1502. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
  1503. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
  1504. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
  1505. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
  1506. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
  1507. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
  1508. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
  1509. mdelay(3);
  1510. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
  1511. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
  1512. }
  1513. static void r8152b_enable_eee(struct r8152 *tp)
  1514. {
  1515. u32 ocp_data;
  1516. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  1517. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  1518. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  1519. ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
  1520. EEE_10_CAP | EEE_NWAY_EN |
  1521. TX_QUIET_EN | RX_QUIET_EN |
  1522. SDRISETIME | RG_RXLPI_MSK_HFDUP |
  1523. SDFALLTIME);
  1524. ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
  1525. RG_LDVQUIET_EN | RG_CKRSEL |
  1526. RG_EEEPRG_EN);
  1527. ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
  1528. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
  1529. ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
  1530. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
  1531. ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
  1532. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  1533. }
  1534. static void r8152b_enable_fc(struct r8152 *tp)
  1535. {
  1536. u16 anar;
  1537. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1538. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1539. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1540. }
  1541. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1542. {
  1543. r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
  1544. r8152b_disable_aldps(tp);
  1545. }
  1546. static void r8152b_init(struct r8152 *tp)
  1547. {
  1548. u32 ocp_data;
  1549. int i;
  1550. rtl_clear_bp(tp);
  1551. if (tp->version == RTL_VER_01) {
  1552. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  1553. ocp_data &= ~LED_MODE_MASK;
  1554. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  1555. }
  1556. r8152b_hw_phy_cfg(tp);
  1557. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1558. ocp_data &= ~POWER_CUT;
  1559. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1560. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1561. ocp_data &= ~RWSUME_INDICATE;
  1562. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1563. r8152b_exit_oob(tp);
  1564. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  1565. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  1566. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  1567. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  1568. ocp_data &= ~MCU_CLK_RATIO_MASK;
  1569. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  1570. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  1571. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  1572. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  1573. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  1574. r8152b_enable_eee(tp);
  1575. r8152b_enable_aldps(tp);
  1576. r8152b_enable_fc(tp);
  1577. r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
  1578. BMCR_ANRESTART);
  1579. for (i = 0; i < 100; i++) {
  1580. udelay(100);
  1581. if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
  1582. break;
  1583. }
  1584. /* enable rx aggregation */
  1585. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  1586. ocp_data &= ~RX_AGG_DISABLE;
  1587. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  1588. }
  1589. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  1590. {
  1591. struct r8152 *tp = usb_get_intfdata(intf);
  1592. netif_device_detach(tp->netdev);
  1593. if (netif_running(tp->netdev)) {
  1594. clear_bit(WORK_ENABLE, &tp->flags);
  1595. usb_kill_urb(tp->intr_urb);
  1596. cancel_delayed_work_sync(&tp->schedule);
  1597. tasklet_disable(&tp->tl);
  1598. }
  1599. rtl8152_down(tp);
  1600. return 0;
  1601. }
  1602. static int rtl8152_resume(struct usb_interface *intf)
  1603. {
  1604. struct r8152 *tp = usb_get_intfdata(intf);
  1605. r8152b_init(tp);
  1606. netif_device_attach(tp->netdev);
  1607. if (netif_running(tp->netdev)) {
  1608. rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
  1609. tp->speed = 0;
  1610. netif_carrier_off(tp->netdev);
  1611. set_bit(WORK_ENABLE, &tp->flags);
  1612. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  1613. tasklet_enable(&tp->tl);
  1614. }
  1615. return 0;
  1616. }
  1617. static void rtl8152_get_drvinfo(struct net_device *netdev,
  1618. struct ethtool_drvinfo *info)
  1619. {
  1620. struct r8152 *tp = netdev_priv(netdev);
  1621. strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
  1622. strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
  1623. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  1624. }
  1625. static
  1626. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  1627. {
  1628. struct r8152 *tp = netdev_priv(netdev);
  1629. if (!tp->mii.mdio_read)
  1630. return -EOPNOTSUPP;
  1631. return mii_ethtool_gset(&tp->mii, cmd);
  1632. }
  1633. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1634. {
  1635. struct r8152 *tp = netdev_priv(dev);
  1636. return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  1637. }
  1638. static struct ethtool_ops ops = {
  1639. .get_drvinfo = rtl8152_get_drvinfo,
  1640. .get_settings = rtl8152_get_settings,
  1641. .set_settings = rtl8152_set_settings,
  1642. .get_link = ethtool_op_get_link,
  1643. };
  1644. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  1645. {
  1646. struct r8152 *tp = netdev_priv(netdev);
  1647. struct mii_ioctl_data *data = if_mii(rq);
  1648. int res = 0;
  1649. switch (cmd) {
  1650. case SIOCGMIIPHY:
  1651. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  1652. break;
  1653. case SIOCGMIIREG:
  1654. data->val_out = r8152_mdio_read(tp, data->reg_num);
  1655. break;
  1656. case SIOCSMIIREG:
  1657. if (!capable(CAP_NET_ADMIN)) {
  1658. res = -EPERM;
  1659. break;
  1660. }
  1661. r8152_mdio_write(tp, data->reg_num, data->val_in);
  1662. break;
  1663. default:
  1664. res = -EOPNOTSUPP;
  1665. }
  1666. return res;
  1667. }
  1668. static const struct net_device_ops rtl8152_netdev_ops = {
  1669. .ndo_open = rtl8152_open,
  1670. .ndo_stop = rtl8152_close,
  1671. .ndo_do_ioctl = rtl8152_ioctl,
  1672. .ndo_start_xmit = rtl8152_start_xmit,
  1673. .ndo_tx_timeout = rtl8152_tx_timeout,
  1674. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  1675. .ndo_set_mac_address = rtl8152_set_mac_address,
  1676. .ndo_change_mtu = eth_change_mtu,
  1677. .ndo_validate_addr = eth_validate_addr,
  1678. };
  1679. static void r8152b_get_version(struct r8152 *tp)
  1680. {
  1681. u32 ocp_data;
  1682. u16 version;
  1683. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  1684. version = (u16)(ocp_data & VERSION_MASK);
  1685. switch (version) {
  1686. case 0x4c00:
  1687. tp->version = RTL_VER_01;
  1688. break;
  1689. case 0x4c10:
  1690. tp->version = RTL_VER_02;
  1691. break;
  1692. default:
  1693. netif_info(tp, probe, tp->netdev,
  1694. "Unknown version 0x%04x\n", version);
  1695. break;
  1696. }
  1697. }
  1698. static int rtl8152_probe(struct usb_interface *intf,
  1699. const struct usb_device_id *id)
  1700. {
  1701. struct usb_device *udev = interface_to_usbdev(intf);
  1702. struct r8152 *tp;
  1703. struct net_device *netdev;
  1704. int ret;
  1705. if (udev->actconfig->desc.bConfigurationValue != 1) {
  1706. usb_driver_set_configuration(udev, 1);
  1707. return -ENODEV;
  1708. }
  1709. netdev = alloc_etherdev(sizeof(struct r8152));
  1710. if (!netdev) {
  1711. dev_err(&intf->dev, "Out of memory");
  1712. return -ENOMEM;
  1713. }
  1714. SET_NETDEV_DEV(netdev, &intf->dev);
  1715. tp = netdev_priv(netdev);
  1716. tp->msg_enable = 0x7FFF;
  1717. tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
  1718. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  1719. tp->udev = udev;
  1720. tp->netdev = netdev;
  1721. tp->intf = intf;
  1722. netdev->netdev_ops = &rtl8152_netdev_ops;
  1723. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  1724. netdev->features |= NETIF_F_IP_CSUM;
  1725. netdev->hw_features = NETIF_F_IP_CSUM;
  1726. SET_ETHTOOL_OPS(netdev, &ops);
  1727. tp->mii.dev = netdev;
  1728. tp->mii.mdio_read = read_mii_word;
  1729. tp->mii.mdio_write = write_mii_word;
  1730. tp->mii.phy_id_mask = 0x3f;
  1731. tp->mii.reg_num_mask = 0x1f;
  1732. tp->mii.phy_id = R8152_PHY_ID;
  1733. tp->mii.supports_gmii = 0;
  1734. r8152b_get_version(tp);
  1735. r8152b_init(tp);
  1736. set_ethernet_addr(tp);
  1737. ret = alloc_all_mem(tp);
  1738. if (ret)
  1739. goto out;
  1740. usb_set_intfdata(intf, tp);
  1741. ret = register_netdev(netdev);
  1742. if (ret != 0) {
  1743. netif_err(tp, probe, netdev, "couldn't register the device");
  1744. goto out1;
  1745. }
  1746. netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
  1747. return 0;
  1748. out1:
  1749. usb_set_intfdata(intf, NULL);
  1750. out:
  1751. free_netdev(netdev);
  1752. return ret;
  1753. }
  1754. static void rtl8152_unload(struct r8152 *tp)
  1755. {
  1756. u32 ocp_data;
  1757. if (tp->version != RTL_VER_01) {
  1758. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1759. ocp_data |= POWER_CUT;
  1760. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1761. }
  1762. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1763. ocp_data &= ~RWSUME_INDICATE;
  1764. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1765. }
  1766. static void rtl8152_disconnect(struct usb_interface *intf)
  1767. {
  1768. struct r8152 *tp = usb_get_intfdata(intf);
  1769. usb_set_intfdata(intf, NULL);
  1770. if (tp) {
  1771. set_bit(RTL8152_UNPLUG, &tp->flags);
  1772. tasklet_kill(&tp->tl);
  1773. unregister_netdev(tp->netdev);
  1774. rtl8152_unload(tp);
  1775. free_all_mem(tp);
  1776. free_netdev(tp->netdev);
  1777. }
  1778. }
  1779. /* table of devices that work with this driver */
  1780. static struct usb_device_id rtl8152_table[] = {
  1781. {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
  1782. {}
  1783. };
  1784. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  1785. static struct usb_driver rtl8152_driver = {
  1786. .name = MODULENAME,
  1787. .id_table = rtl8152_table,
  1788. .probe = rtl8152_probe,
  1789. .disconnect = rtl8152_disconnect,
  1790. .suspend = rtl8152_suspend,
  1791. .resume = rtl8152_resume,
  1792. .reset_resume = rtl8152_resume,
  1793. };
  1794. module_usb_driver(rtl8152_driver);
  1795. MODULE_AUTHOR(DRIVER_AUTHOR);
  1796. MODULE_DESCRIPTION(DRIVER_DESC);
  1797. MODULE_LICENSE("GPL");