pcxhr.c 38 KB

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  1. /*
  2. * Driver for Digigram pcxhr compatible soundcards
  3. *
  4. * main file with alsa callbacks
  5. *
  6. * Copyright (c) 2004 by Digigram <alsa@digigram.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <sound/driver.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/slab.h>
  26. #include <linux/pci.h>
  27. #include <linux/delay.h>
  28. #include <linux/moduleparam.h>
  29. #include <sound/core.h>
  30. #include <sound/initval.h>
  31. #include <sound/info.h>
  32. #include <sound/control.h>
  33. #include <sound/pcm.h>
  34. #include <sound/pcm_params.h>
  35. #include "pcxhr.h"
  36. #include "pcxhr_mixer.h"
  37. #include "pcxhr_hwdep.h"
  38. #include "pcxhr_core.h"
  39. #define DRIVER_NAME "pcxhr"
  40. MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>");
  41. MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
  42. MODULE_LICENSE("GPL");
  43. MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
  44. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  45. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  46. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  47. static int mono[SNDRV_CARDS]; /* capture in mono only */
  48. module_param_array(index, int, NULL, 0444);
  49. MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
  50. module_param_array(id, charp, NULL, 0444);
  51. MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
  52. module_param_array(enable, bool, NULL, 0444);
  53. MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
  54. module_param_array(mono, bool, NULL, 0444);
  55. MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
  56. enum {
  57. PCI_ID_VX882HR,
  58. PCI_ID_PCX882HR,
  59. PCI_ID_VX881HR,
  60. PCI_ID_PCX881HR,
  61. PCI_ID_PCX1222HR,
  62. PCI_ID_PCX1221HR,
  63. PCI_ID_LAST
  64. };
  65. static struct pci_device_id pcxhr_ids[] = {
  66. { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, /* VX882HR */
  67. { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, /* PCX882HR */
  68. { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, /* VX881HR */
  69. { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, /* PCX881HR */
  70. { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, /* PCX1222HR */
  71. { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, /* PCX1221HR */
  72. { 0, }
  73. };
  74. MODULE_DEVICE_TABLE(pci, pcxhr_ids);
  75. struct board_parameters {
  76. char* board_name;
  77. short playback_chips;
  78. short capture_chips;
  79. short firmware_num;
  80. };
  81. static struct board_parameters pcxhr_board_params[] = {
  82. [PCI_ID_VX882HR] = { "VX882HR", 4, 4, 41, },
  83. [PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 41, },
  84. [PCI_ID_VX881HR] = { "VX881HR", 4, 4, 41, },
  85. [PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 41, },
  86. [PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 42, },
  87. [PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 42, },
  88. };
  89. static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
  90. unsigned int* realfreq)
  91. {
  92. unsigned int reg;
  93. if (freq < 6900 || freq > 110250)
  94. return -EINVAL;
  95. reg = (28224000 * 10) / freq;
  96. reg = (reg + 5) / 10;
  97. if (reg < 0x200)
  98. *pllreg = reg + 0x800;
  99. else if (reg < 0x400)
  100. *pllreg = reg & 0x1ff;
  101. else if (reg < 0x800) {
  102. *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
  103. reg &= ~1;
  104. } else {
  105. *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
  106. reg &= ~3;
  107. }
  108. if (realfreq)
  109. *realfreq = ((28224000 * 10) / reg + 5) / 10;
  110. return 0;
  111. }
  112. #define PCXHR_FREQ_REG_MASK 0x1f
  113. #define PCXHR_FREQ_QUARTZ_48000 0x00
  114. #define PCXHR_FREQ_QUARTZ_24000 0x01
  115. #define PCXHR_FREQ_QUARTZ_12000 0x09
  116. #define PCXHR_FREQ_QUARTZ_32000 0x08
  117. #define PCXHR_FREQ_QUARTZ_16000 0x04
  118. #define PCXHR_FREQ_QUARTZ_8000 0x0c
  119. #define PCXHR_FREQ_QUARTZ_44100 0x02
  120. #define PCXHR_FREQ_QUARTZ_22050 0x0a
  121. #define PCXHR_FREQ_QUARTZ_11025 0x06
  122. #define PCXHR_FREQ_PLL 0x05
  123. #define PCXHR_FREQ_QUARTZ_192000 0x10
  124. #define PCXHR_FREQ_QUARTZ_96000 0x18
  125. #define PCXHR_FREQ_QUARTZ_176400 0x14
  126. #define PCXHR_FREQ_QUARTZ_88200 0x1c
  127. #define PCXHR_FREQ_QUARTZ_128000 0x12
  128. #define PCXHR_FREQ_QUARTZ_64000 0x1a
  129. #define PCXHR_FREQ_WORD_CLOCK 0x0f
  130. #define PCXHR_FREQ_SYNC_AES 0x0e
  131. #define PCXHR_FREQ_AES_1 0x07
  132. #define PCXHR_FREQ_AES_2 0x0b
  133. #define PCXHR_FREQ_AES_3 0x03
  134. #define PCXHR_FREQ_AES_4 0x0d
  135. #define PCXHR_MODIFY_CLOCK_S_BIT 0x04
  136. #define PCXHR_IRQ_TIMER_FREQ 92000
  137. #define PCXHR_IRQ_TIMER_PERIOD 48
  138. static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
  139. unsigned int *reg, unsigned int *freq)
  140. {
  141. unsigned int val, realfreq, pllreg;
  142. struct pcxhr_rmh rmh;
  143. int err;
  144. realfreq = rate;
  145. switch (mgr->use_clock_type) {
  146. case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */
  147. switch (rate) {
  148. case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break;
  149. case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break;
  150. case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break;
  151. case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break;
  152. case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break;
  153. case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break;
  154. case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break;
  155. case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break;
  156. case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break;
  157. case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break;
  158. case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break;
  159. case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break;
  160. case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break;
  161. case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break;
  162. case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break;
  163. default :
  164. val = PCXHR_FREQ_PLL;
  165. /* get the value for the pll register */
  166. err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
  167. if (err)
  168. return err;
  169. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
  170. rmh.cmd[0] |= IO_NUM_REG_GENCLK;
  171. rmh.cmd[1] = pllreg & MASK_DSP_WORD;
  172. rmh.cmd[2] = pllreg >> 24;
  173. rmh.cmd_len = 3;
  174. err = pcxhr_send_msg(mgr, &rmh);
  175. if (err < 0) {
  176. snd_printk(KERN_ERR
  177. "error CMD_ACCESS_IO_WRITE for PLL register : %x!\n",
  178. err );
  179. return err;
  180. }
  181. }
  182. break;
  183. case PCXHR_CLOCK_TYPE_WORD_CLOCK : val = PCXHR_FREQ_WORD_CLOCK; break;
  184. case PCXHR_CLOCK_TYPE_AES_SYNC : val = PCXHR_FREQ_SYNC_AES; break;
  185. case PCXHR_CLOCK_TYPE_AES_1 : val = PCXHR_FREQ_AES_1; break;
  186. case PCXHR_CLOCK_TYPE_AES_2 : val = PCXHR_FREQ_AES_2; break;
  187. case PCXHR_CLOCK_TYPE_AES_3 : val = PCXHR_FREQ_AES_3; break;
  188. case PCXHR_CLOCK_TYPE_AES_4 : val = PCXHR_FREQ_AES_4; break;
  189. default : return -EINVAL;
  190. }
  191. *reg = val;
  192. *freq = realfreq;
  193. return 0;
  194. }
  195. int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
  196. {
  197. unsigned int val, realfreq, speed;
  198. struct pcxhr_rmh rmh;
  199. int err, changed;
  200. if (rate == 0)
  201. return 0; /* nothing to do */
  202. err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
  203. if (err)
  204. return err;
  205. /* codec speed modes */
  206. if (rate < 55000)
  207. speed = 0; /* single speed */
  208. else if (rate < 100000)
  209. speed = 1; /* dual speed */
  210. else
  211. speed = 2; /* quad speed */
  212. if (mgr->codec_speed != speed) {
  213. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
  214. rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
  215. err = pcxhr_send_msg(mgr, &rmh);
  216. if (err)
  217. return err;
  218. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
  219. rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
  220. rmh.cmd[1] = speed;
  221. rmh.cmd_len = 2;
  222. err = pcxhr_send_msg(mgr, &rmh);
  223. if (err)
  224. return err;
  225. }
  226. /* set the new frequency */
  227. snd_printdd("clock register : set %x\n", val);
  228. err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, &changed);
  229. if (err)
  230. return err;
  231. mgr->sample_rate_real = realfreq;
  232. mgr->cur_clock_type = mgr->use_clock_type;
  233. /* unmute after codec speed modes */
  234. if (mgr->codec_speed != speed) {
  235. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
  236. rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
  237. err = pcxhr_send_msg(mgr, &rmh);
  238. if (err)
  239. return err;
  240. mgr->codec_speed = speed; /* save new codec speed */
  241. }
  242. if (changed) {
  243. pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
  244. rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */
  245. if (rate < PCXHR_IRQ_TIMER_FREQ)
  246. rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
  247. else
  248. rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
  249. rmh.cmd[2] = rate;
  250. rmh.cmd_len = 3;
  251. err = pcxhr_send_msg(mgr, &rmh);
  252. if (err)
  253. return err;
  254. }
  255. snd_printdd("pcxhr_set_clock to %dHz (realfreq=%d)\n", rate, realfreq);
  256. return 0;
  257. }
  258. int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type,
  259. int *sample_rate)
  260. {
  261. struct pcxhr_rmh rmh;
  262. unsigned char reg;
  263. int err, rate;
  264. switch (clock_type) {
  265. case PCXHR_CLOCK_TYPE_WORD_CLOCK : reg = REG_STATUS_WORD_CLOCK; break;
  266. case PCXHR_CLOCK_TYPE_AES_SYNC : reg = REG_STATUS_AES_SYNC; break;
  267. case PCXHR_CLOCK_TYPE_AES_1 : reg = REG_STATUS_AES_1; break;
  268. case PCXHR_CLOCK_TYPE_AES_2 : reg = REG_STATUS_AES_2; break;
  269. case PCXHR_CLOCK_TYPE_AES_3 : reg = REG_STATUS_AES_3; break;
  270. case PCXHR_CLOCK_TYPE_AES_4 : reg = REG_STATUS_AES_4; break;
  271. default : return -EINVAL;
  272. }
  273. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
  274. rmh.cmd_len = 2;
  275. rmh.cmd[0] |= IO_NUM_REG_STATUS;
  276. if (mgr->last_reg_stat != reg) {
  277. rmh.cmd[1] = reg;
  278. err = pcxhr_send_msg(mgr, &rmh);
  279. if (err)
  280. return err;
  281. udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */
  282. mgr->last_reg_stat = reg;
  283. }
  284. rmh.cmd[1] = REG_STATUS_CURRENT;
  285. err = pcxhr_send_msg(mgr, &rmh);
  286. if (err)
  287. return err;
  288. switch (rmh.stat[1] & 0x0f) {
  289. case REG_STATUS_SYNC_32000 : rate = 32000; break;
  290. case REG_STATUS_SYNC_44100 : rate = 44100; break;
  291. case REG_STATUS_SYNC_48000 : rate = 48000; break;
  292. case REG_STATUS_SYNC_64000 : rate = 64000; break;
  293. case REG_STATUS_SYNC_88200 : rate = 88200; break;
  294. case REG_STATUS_SYNC_96000 : rate = 96000; break;
  295. case REG_STATUS_SYNC_128000 : rate = 128000; break;
  296. case REG_STATUS_SYNC_176400 : rate = 176400; break;
  297. case REG_STATUS_SYNC_192000 : rate = 192000; break;
  298. default: rate = 0;
  299. }
  300. snd_printdd("External clock is at %d Hz\n", rate);
  301. *sample_rate = rate;
  302. return 0;
  303. }
  304. /*
  305. * start or stop playback/capture substream
  306. */
  307. static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
  308. {
  309. int err;
  310. struct snd_pcxhr *chip;
  311. struct pcxhr_rmh rmh;
  312. int stream_mask, start;
  313. if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
  314. start = 1;
  315. else {
  316. if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
  317. snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state CANNOT be stopped\n");
  318. return -EINVAL;
  319. }
  320. start = 0;
  321. }
  322. if (!stream->substream)
  323. return -EINVAL;
  324. stream->timer_abs_periods = 0;
  325. stream->timer_period_frag = 0; /* reset theoretical stream pos */
  326. stream->timer_buf_periods = 0;
  327. stream->timer_is_synced = 0;
  328. stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
  329. pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
  330. pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
  331. stream->pipe->first_audio, 0, stream_mask);
  332. chip = snd_pcm_substream_chip(stream->substream);
  333. err = pcxhr_send_msg(chip->mgr, &rmh);
  334. if (err)
  335. snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n", err);
  336. stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
  337. return err;
  338. }
  339. #define HEADER_FMT_BASE_LIN 0xfed00000
  340. #define HEADER_FMT_BASE_FLOAT 0xfad00000
  341. #define HEADER_FMT_INTEL 0x00008000
  342. #define HEADER_FMT_24BITS 0x00004000
  343. #define HEADER_FMT_16BITS 0x00002000
  344. #define HEADER_FMT_UPTO11 0x00000200
  345. #define HEADER_FMT_UPTO32 0x00000100
  346. #define HEADER_FMT_MONO 0x00000080
  347. static int pcxhr_set_format(struct pcxhr_stream *stream)
  348. {
  349. int err, is_capture, sample_rate, stream_num;
  350. struct snd_pcxhr *chip;
  351. struct pcxhr_rmh rmh;
  352. unsigned int header;
  353. switch (stream->format) {
  354. case SNDRV_PCM_FORMAT_U8:
  355. header = HEADER_FMT_BASE_LIN;
  356. break;
  357. case SNDRV_PCM_FORMAT_S16_LE:
  358. header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL;
  359. break;
  360. case SNDRV_PCM_FORMAT_S16_BE:
  361. header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
  362. break;
  363. case SNDRV_PCM_FORMAT_S24_3LE:
  364. header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL;
  365. break;
  366. case SNDRV_PCM_FORMAT_S24_3BE:
  367. header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
  368. break;
  369. case SNDRV_PCM_FORMAT_FLOAT_LE:
  370. header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
  371. break;
  372. default:
  373. snd_printk(KERN_ERR "error pcxhr_set_format() : unknown format\n");
  374. return -EINVAL;
  375. }
  376. chip = snd_pcm_substream_chip(stream->substream);
  377. sample_rate = chip->mgr->sample_rate;
  378. if (sample_rate <= 32000 && sample_rate !=0) {
  379. if (sample_rate <= 11025)
  380. header |= HEADER_FMT_UPTO11;
  381. else
  382. header |= HEADER_FMT_UPTO32;
  383. }
  384. if (stream->channels == 1)
  385. header |= HEADER_FMT_MONO;
  386. is_capture = stream->pipe->is_capture;
  387. stream_num = is_capture ? 0 : stream->substream->number;
  388. pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
  389. pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
  390. if (is_capture)
  391. rmh.cmd[0] |= 1<<12;
  392. rmh.cmd[1] = 0;
  393. rmh.cmd[2] = header >> 8;
  394. rmh.cmd[3] = (header & 0xff) << 16;
  395. rmh.cmd_len = 4;
  396. err = pcxhr_send_msg(chip->mgr, &rmh);
  397. if (err)
  398. snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err);
  399. return err;
  400. }
  401. static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
  402. {
  403. int err, is_capture, stream_num;
  404. struct pcxhr_rmh rmh;
  405. struct snd_pcm_substream *subs = stream->substream;
  406. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  407. is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
  408. stream_num = is_capture ? 0 : subs->number;
  409. snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%x) subs(%d)\n",
  410. is_capture ? 'c' : 'p',
  411. chip->chip_idx, (void*)subs->runtime->dma_addr,
  412. subs->runtime->dma_bytes, subs->number);
  413. pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
  414. pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
  415. snd_assert(subs->runtime->dma_bytes < 0x200000); /* max buffer size is 2 MByte */
  416. rmh.cmd[1] = subs->runtime->dma_bytes * 8; /* size in bits */
  417. rmh.cmd[2] = subs->runtime->dma_addr >> 24; /* most significant byte */
  418. rmh.cmd[2] |= 1<<19; /* this is a circular buffer */
  419. rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; /* least 3 significant bytes */
  420. rmh.cmd_len = 4;
  421. err = pcxhr_send_msg(chip->mgr, &rmh);
  422. if (err)
  423. snd_printk(KERN_ERR "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
  424. return err;
  425. }
  426. #if 0
  427. static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, snd_pcm_uframes_t *sample_count)
  428. {
  429. struct pcxhr_rmh rmh;
  430. int err;
  431. pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
  432. pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
  433. pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
  434. 1<<stream->pipe->first_audio);
  435. err = pcxhr_send_msg(chip->mgr, &rmh);
  436. if (err == 0) {
  437. *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
  438. *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
  439. }
  440. snd_printdd("PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
  441. return err;
  442. }
  443. #endif
  444. static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
  445. struct pcxhr_pipe **pipe)
  446. {
  447. if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
  448. *pipe = stream->pipe;
  449. return 1;
  450. }
  451. return 0;
  452. }
  453. static void pcxhr_trigger_tasklet(unsigned long arg)
  454. {
  455. unsigned long flags;
  456. int i, j, err;
  457. struct pcxhr_pipe *pipe;
  458. struct snd_pcxhr *chip;
  459. struct pcxhr_mgr *mgr = (struct pcxhr_mgr*)(arg);
  460. int capture_mask = 0;
  461. int playback_mask = 0;
  462. #ifdef CONFIG_SND_DEBUG_DETECT
  463. struct timeval my_tv1, my_tv2;
  464. do_gettimeofday(&my_tv1);
  465. #endif
  466. down(&mgr->setup_mutex);
  467. /* check the pipes concerned and build pipe_array */
  468. for (i = 0; i < mgr->num_cards; i++) {
  469. chip = mgr->chip[i];
  470. for (j = 0; j < chip->nb_streams_capt; j++) {
  471. if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
  472. capture_mask |= (1 << pipe->first_audio);
  473. }
  474. for (j = 0; j < chip->nb_streams_play; j++) {
  475. if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
  476. playback_mask |= (1 << pipe->first_audio);
  477. break; /* add only once, as all playback streams of
  478. * one chip use the same pipe
  479. */
  480. }
  481. }
  482. }
  483. if (capture_mask == 0 && playback_mask == 0) {
  484. up(&mgr->setup_mutex);
  485. snd_printk(KERN_ERR "pcxhr_trigger_tasklet : no pipes\n");
  486. return;
  487. }
  488. snd_printdd("pcxhr_trigger_tasklet : playback_mask=%x capture_mask=%x\n",
  489. playback_mask, capture_mask);
  490. /* synchronous stop of all the pipes concerned */
  491. err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
  492. if (err) {
  493. up(&mgr->setup_mutex);
  494. snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error stop pipes (P%x C%x)\n",
  495. playback_mask, capture_mask);
  496. return;
  497. }
  498. /* unfortunately the dsp lost format and buffer info with the stop pipe */
  499. for (i = 0; i < mgr->num_cards; i++) {
  500. struct pcxhr_stream *stream;
  501. chip = mgr->chip[i];
  502. for (j = 0; j < chip->nb_streams_capt; j++) {
  503. stream = &chip->capture_stream[j];
  504. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
  505. err = pcxhr_set_format(stream);
  506. err = pcxhr_update_r_buffer(stream);
  507. }
  508. }
  509. for (j = 0; j < chip->nb_streams_play; j++) {
  510. stream = &chip->playback_stream[j];
  511. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
  512. err = pcxhr_set_format(stream);
  513. err = pcxhr_update_r_buffer(stream);
  514. }
  515. }
  516. }
  517. /* start all the streams */
  518. for (i = 0; i < mgr->num_cards; i++) {
  519. struct pcxhr_stream *stream;
  520. chip = mgr->chip[i];
  521. for (j = 0; j < chip->nb_streams_capt; j++) {
  522. stream = &chip->capture_stream[j];
  523. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
  524. err = pcxhr_set_stream_state(stream);
  525. }
  526. for (j = 0; j < chip->nb_streams_play; j++) {
  527. stream = &chip->playback_stream[j];
  528. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
  529. err = pcxhr_set_stream_state(stream);
  530. }
  531. }
  532. /* synchronous start of all the pipes concerned */
  533. err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
  534. if (err) {
  535. up(&mgr->setup_mutex);
  536. snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error start pipes (P%x C%x)\n",
  537. playback_mask, capture_mask);
  538. return;
  539. }
  540. /* put the streams into the running state now (increment pointer by interrupt) */
  541. spin_lock_irqsave(&mgr->lock, flags);
  542. for ( i =0; i < mgr->num_cards; i++) {
  543. struct pcxhr_stream *stream;
  544. chip = mgr->chip[i];
  545. for(j = 0; j < chip->nb_streams_capt; j++) {
  546. stream = &chip->capture_stream[j];
  547. if(stream->status == PCXHR_STREAM_STATUS_STARTED)
  548. stream->status = PCXHR_STREAM_STATUS_RUNNING;
  549. }
  550. for (j = 0; j < chip->nb_streams_play; j++) {
  551. stream = &chip->playback_stream[j];
  552. if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
  553. /* playback will already have advanced ! */
  554. stream->timer_period_frag += PCXHR_GRANULARITY;
  555. stream->status = PCXHR_STREAM_STATUS_RUNNING;
  556. }
  557. }
  558. }
  559. spin_unlock_irqrestore(&mgr->lock, flags);
  560. up(&mgr->setup_mutex);
  561. #ifdef CONFIG_SND_DEBUG_DETECT
  562. do_gettimeofday(&my_tv2);
  563. snd_printdd("***TRIGGER TASKLET*** TIME = %ld (err = %x)\n",
  564. my_tv2.tv_usec - my_tv1.tv_usec, err);
  565. #endif
  566. }
  567. /*
  568. * trigger callback
  569. */
  570. static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
  571. {
  572. struct pcxhr_stream *stream;
  573. struct list_head *pos;
  574. struct snd_pcm_substream *s;
  575. int i;
  576. switch (cmd) {
  577. case SNDRV_PCM_TRIGGER_START:
  578. snd_printdd("SNDRV_PCM_TRIGGER_START\n");
  579. i = 0;
  580. snd_pcm_group_for_each(pos, subs) {
  581. s = snd_pcm_group_substream_entry(pos);
  582. stream = s->runtime->private_data;
  583. stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
  584. snd_pcm_trigger_done(s, subs);
  585. i++;
  586. }
  587. if (i==1) {
  588. snd_printdd("Only one Substream %c %d\n",
  589. stream->pipe->is_capture ? 'C' : 'P',
  590. stream->pipe->first_audio);
  591. if (pcxhr_set_format(stream))
  592. return -EINVAL;
  593. if (pcxhr_update_r_buffer(stream))
  594. return -EINVAL;
  595. if (pcxhr_set_stream_state(stream))
  596. return -EINVAL;
  597. stream->status = PCXHR_STREAM_STATUS_RUNNING;
  598. } else {
  599. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  600. tasklet_hi_schedule(&chip->mgr->trigger_taskq);
  601. }
  602. break;
  603. case SNDRV_PCM_TRIGGER_STOP:
  604. snd_printdd("SNDRV_PCM_TRIGGER_STOP\n");
  605. snd_pcm_group_for_each(pos, subs) {
  606. s = snd_pcm_group_substream_entry(pos);
  607. stream = s->runtime->private_data;
  608. stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
  609. if (pcxhr_set_stream_state(stream))
  610. return -EINVAL;
  611. snd_pcm_trigger_done(s, subs);
  612. }
  613. break;
  614. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  615. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  616. /* TODO */
  617. default:
  618. return -EINVAL;
  619. }
  620. return 0;
  621. }
  622. static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
  623. {
  624. struct pcxhr_rmh rmh;
  625. int err;
  626. pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
  627. if (start) {
  628. mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; /* last dsp time invalid */
  629. rmh.cmd[0] |= PCXHR_GRANULARITY;
  630. }
  631. err = pcxhr_send_msg(mgr, &rmh);
  632. if (err < 0)
  633. snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n", err);
  634. return err;
  635. }
  636. /*
  637. * prepare callback for all pcms
  638. */
  639. static int pcxhr_prepare(struct snd_pcm_substream *subs)
  640. {
  641. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  642. struct pcxhr_mgr *mgr = chip->mgr;
  643. /*
  644. struct pcxhr_stream *stream = (pcxhr_stream_t*)subs->runtime->private_data;
  645. */
  646. int err = 0;
  647. snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
  648. subs->runtime->period_size, subs->runtime->periods,
  649. subs->runtime->buffer_size);
  650. /*
  651. if(subs->runtime->period_size <= PCXHR_GRANULARITY) {
  652. snd_printk(KERN_ERR "pcxhr_prepare : error period_size too small (%x)\n",
  653. (unsigned int)subs->runtime->period_size);
  654. return -EINVAL;
  655. }
  656. */
  657. down(&mgr->setup_mutex);
  658. do {
  659. /* if the stream was stopped before, format and buffer were reset */
  660. /*
  661. if(stream->status == PCXHR_STREAM_STATUS_STOPPED) {
  662. err = pcxhr_set_format(stream);
  663. if(err) break;
  664. err = pcxhr_update_r_buffer(stream);
  665. if(err) break;
  666. }
  667. */
  668. /* only the first stream can choose the sample rate */
  669. /* the further opened streams will be limited to its frequency (see open) */
  670. /* set the clock only once (first stream) */
  671. if (mgr->sample_rate == 0) {
  672. err = pcxhr_set_clock(mgr, subs->runtime->rate);
  673. if (err)
  674. break;
  675. mgr->sample_rate = subs->runtime->rate;
  676. err = pcxhr_hardware_timer(mgr, 1); /* start the DSP-timer */
  677. }
  678. } while(0); /* do only once (so we can use break instead of goto) */
  679. up(&mgr->setup_mutex);
  680. return err;
  681. }
  682. /*
  683. * HW_PARAMS callback for all pcms
  684. */
  685. static int pcxhr_hw_params(struct snd_pcm_substream *subs,
  686. struct snd_pcm_hw_params *hw)
  687. {
  688. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  689. struct pcxhr_mgr *mgr = chip->mgr;
  690. struct pcxhr_stream *stream = subs->runtime->private_data;
  691. snd_pcm_format_t format;
  692. int err;
  693. int channels;
  694. /* set up channels */
  695. channels = params_channels(hw);
  696. /* set up format for the stream */
  697. format = params_format(hw);
  698. down(&mgr->setup_mutex);
  699. stream->channels = channels;
  700. stream->format = format;
  701. /* set the format to the board */
  702. /*
  703. err = pcxhr_set_format(stream);
  704. if(err) {
  705. up(&mgr->setup_mutex);
  706. return err;
  707. }
  708. */
  709. /* allocate buffer */
  710. err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
  711. /*
  712. if (err > 0) {
  713. err = pcxhr_update_r_buffer(stream);
  714. }
  715. */
  716. up(&mgr->setup_mutex);
  717. return err;
  718. }
  719. static int pcxhr_hw_free(struct snd_pcm_substream *subs)
  720. {
  721. snd_pcm_lib_free_pages(subs);
  722. return 0;
  723. }
  724. /*
  725. * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
  726. */
  727. static struct snd_pcm_hardware pcxhr_caps =
  728. {
  729. .info = ( SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  730. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START |
  731. 0 /*SNDRV_PCM_INFO_PAUSE*/),
  732. .formats = ( SNDRV_PCM_FMTBIT_U8 |
  733. SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
  734. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE |
  735. SNDRV_PCM_FMTBIT_FLOAT_LE ),
  736. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000,
  737. .rate_min = 8000,
  738. .rate_max = 192000,
  739. .channels_min = 1,
  740. .channels_max = 2,
  741. .buffer_bytes_max = (32*1024),
  742. /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
  743. .period_bytes_min = (2*PCXHR_GRANULARITY),
  744. .period_bytes_max = (16*1024),
  745. .periods_min = 2,
  746. .periods_max = (32*1024/PCXHR_GRANULARITY),
  747. };
  748. static int pcxhr_open(struct snd_pcm_substream *subs)
  749. {
  750. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  751. struct pcxhr_mgr *mgr = chip->mgr;
  752. struct snd_pcm_runtime *runtime = subs->runtime;
  753. struct pcxhr_stream *stream;
  754. int is_capture;
  755. down(&mgr->setup_mutex);
  756. /* copy the struct snd_pcm_hardware struct */
  757. runtime->hw = pcxhr_caps;
  758. if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
  759. snd_printdd("pcxhr_open playback chip%d subs%d\n",
  760. chip->chip_idx, subs->number);
  761. is_capture = 0;
  762. stream = &chip->playback_stream[subs->number];
  763. } else {
  764. snd_printdd("pcxhr_open capture chip%d subs%d\n",
  765. chip->chip_idx, subs->number);
  766. is_capture = 1;
  767. if (mgr->mono_capture)
  768. runtime->hw.channels_max = 1;
  769. else
  770. runtime->hw.channels_min = 2;
  771. stream = &chip->capture_stream[subs->number];
  772. }
  773. if (stream->status != PCXHR_STREAM_STATUS_FREE){
  774. /* streams in use */
  775. snd_printk(KERN_ERR "pcxhr_open chip%d subs%d in use\n",
  776. chip->chip_idx, subs->number);
  777. up(&mgr->setup_mutex);
  778. return -EBUSY;
  779. }
  780. /* if a sample rate is already used or fixed by external clock,
  781. * the stream cannot change
  782. */
  783. if (mgr->sample_rate)
  784. runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
  785. else {
  786. if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
  787. int external_rate;
  788. if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
  789. &external_rate) ||
  790. external_rate == 0) {
  791. /* cannot detect the external clock rate */
  792. up(&mgr->setup_mutex);
  793. return -EBUSY;
  794. }
  795. runtime->hw.rate_min = runtime->hw.rate_max = external_rate;
  796. }
  797. }
  798. stream->status = PCXHR_STREAM_STATUS_OPEN;
  799. stream->substream = subs;
  800. stream->channels = 0; /* not configured yet */
  801. runtime->private_data = stream;
  802. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4);
  803. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
  804. mgr->ref_count_rate++;
  805. up(&mgr->setup_mutex);
  806. return 0;
  807. }
  808. static int pcxhr_close(struct snd_pcm_substream *subs)
  809. {
  810. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  811. struct pcxhr_mgr *mgr = chip->mgr;
  812. struct pcxhr_stream *stream = subs->runtime->private_data;
  813. down(&mgr->setup_mutex);
  814. snd_printdd("pcxhr_close chip%d subs%d\n", chip->chip_idx, subs->number);
  815. /* sample rate released */
  816. if (--mgr->ref_count_rate == 0) {
  817. mgr->sample_rate = 0; /* the sample rate is no more locked */
  818. pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */
  819. }
  820. stream->status = PCXHR_STREAM_STATUS_FREE;
  821. stream->substream = NULL;
  822. up(&mgr->setup_mutex);
  823. return 0;
  824. }
  825. static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
  826. {
  827. unsigned long flags;
  828. u_int32_t timer_period_frag;
  829. int timer_buf_periods;
  830. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  831. struct snd_pcm_runtime *runtime = subs->runtime;
  832. struct pcxhr_stream *stream = runtime->private_data;
  833. spin_lock_irqsave(&chip->mgr->lock, flags);
  834. /* get the period fragment and the nb of periods in the buffer */
  835. timer_period_frag = stream->timer_period_frag;
  836. timer_buf_periods = stream->timer_buf_periods;
  837. spin_unlock_irqrestore(&chip->mgr->lock, flags);
  838. return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
  839. timer_period_frag);
  840. }
  841. static struct snd_pcm_ops pcxhr_ops = {
  842. .open = pcxhr_open,
  843. .close = pcxhr_close,
  844. .ioctl = snd_pcm_lib_ioctl,
  845. .prepare = pcxhr_prepare,
  846. .hw_params = pcxhr_hw_params,
  847. .hw_free = pcxhr_hw_free,
  848. .trigger = pcxhr_trigger,
  849. .pointer = pcxhr_stream_pointer,
  850. };
  851. /*
  852. */
  853. int pcxhr_create_pcm(struct snd_pcxhr *chip)
  854. {
  855. int err;
  856. struct snd_pcm *pcm;
  857. char name[32];
  858. sprintf(name, "pcxhr %d", chip->chip_idx);
  859. if ((err = snd_pcm_new(chip->card, name, 0,
  860. chip->nb_streams_play,
  861. chip->nb_streams_capt, &pcm)) < 0) {
  862. snd_printk(KERN_ERR "cannot create pcm %s\n", name);
  863. return err;
  864. }
  865. pcm->private_data = chip;
  866. if (chip->nb_streams_play)
  867. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
  868. if (chip->nb_streams_capt)
  869. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
  870. pcm->info_flags = 0;
  871. strcpy(pcm->name, name);
  872. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  873. snd_dma_pci_data(chip->mgr->pci),
  874. 32*1024, 32*1024);
  875. chip->pcm = pcm;
  876. return 0;
  877. }
  878. static int pcxhr_chip_free(struct snd_pcxhr *chip)
  879. {
  880. kfree(chip);
  881. return 0;
  882. }
  883. static int pcxhr_chip_dev_free(struct snd_device *device)
  884. {
  885. struct snd_pcxhr *chip = device->device_data;
  886. return pcxhr_chip_free(chip);
  887. }
  888. /*
  889. */
  890. static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx)
  891. {
  892. int err;
  893. struct snd_pcxhr *chip;
  894. static struct snd_device_ops ops = {
  895. .dev_free = pcxhr_chip_dev_free,
  896. };
  897. mgr->chip[idx] = chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  898. if (! chip) {
  899. snd_printk(KERN_ERR "cannot allocate chip\n");
  900. return -ENOMEM;
  901. }
  902. chip->card = card;
  903. chip->chip_idx = idx;
  904. chip->mgr = mgr;
  905. if (idx < mgr->playback_chips)
  906. /* stereo or mono streams */
  907. chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
  908. if (idx < mgr->capture_chips) {
  909. if (mgr->mono_capture)
  910. chip->nb_streams_capt = 2; /* 2 mono streams (left+right) */
  911. else
  912. chip->nb_streams_capt = 1; /* or 1 stereo stream */
  913. }
  914. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  915. pcxhr_chip_free(chip);
  916. return err;
  917. }
  918. snd_card_set_dev(card, &mgr->pci->dev);
  919. return 0;
  920. }
  921. /* proc interface */
  922. static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  923. {
  924. struct snd_pcxhr *chip = entry->private_data;
  925. struct pcxhr_mgr *mgr = chip->mgr;
  926. snd_iprintf(buffer, "\n%s\n", mgr->longname);
  927. /* stats available when embedded DSP is running */
  928. if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
  929. struct pcxhr_rmh rmh;
  930. short ver_maj = (mgr->dsp_version >> 16) & 0xff;
  931. short ver_min = (mgr->dsp_version >> 8) & 0xff;
  932. short ver_build = mgr->dsp_version & 0xff;
  933. snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING);
  934. snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build);
  935. if (mgr->board_has_analog)
  936. snd_iprintf(buffer, "analog io available\n");
  937. else
  938. snd_iprintf(buffer, "digital only board\n");
  939. /* calc cpu load of the dsp */
  940. pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
  941. if( ! pcxhr_send_msg(mgr, &rmh) ) {
  942. int cur = rmh.stat[0];
  943. int ref = rmh.stat[1];
  944. if (ref > 0) {
  945. if (mgr->sample_rate_real != 0 &&
  946. mgr->sample_rate_real != 48000) {
  947. ref = (ref * 48000) / mgr->sample_rate_real;
  948. if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ)
  949. ref *= 2;
  950. }
  951. cur = 100 - (100 * cur) / ref;
  952. snd_iprintf(buffer, "cpu load %d%%\n", cur);
  953. snd_iprintf(buffer, "buffer pool %d/%d kWords\n",
  954. rmh.stat[2], rmh.stat[3]);
  955. }
  956. }
  957. snd_iprintf(buffer, "dma granularity : %d\n", PCXHR_GRANULARITY);
  958. snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err);
  959. snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
  960. mgr->async_err_pipe_xrun);
  961. snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
  962. mgr->async_err_stream_xrun);
  963. snd_iprintf(buffer, "dsp async last other error : %x\n",
  964. mgr->async_err_other_last);
  965. /* debug zone dsp */
  966. rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
  967. rmh.cmd_len = 1;
  968. rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
  969. rmh.dsp_stat = 0;
  970. rmh.cmd_idx = CMD_LAST_INDEX;
  971. if( ! pcxhr_send_msg(mgr, &rmh) ) {
  972. int i;
  973. for (i = 0; i < rmh.stat_len; i++)
  974. snd_iprintf(buffer, "debug[%02d] = %06x\n", i, rmh.stat[i]);
  975. }
  976. } else
  977. snd_iprintf(buffer, "no firmware loaded\n");
  978. snd_iprintf(buffer, "\n");
  979. }
  980. static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  981. {
  982. struct snd_pcxhr *chip = entry->private_data;
  983. struct pcxhr_mgr *mgr = chip->mgr;
  984. static char *texts[7] = {
  985. "Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4"
  986. };
  987. snd_iprintf(buffer, "\n%s\n", mgr->longname);
  988. snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]);
  989. snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real);
  990. /* commands available when embedded DSP is running */
  991. if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
  992. int i, err, sample_rate;
  993. for (i = PCXHR_CLOCK_TYPE_WORD_CLOCK; i< (3 + mgr->capture_chips); i++) {
  994. err = pcxhr_get_external_clock(mgr, i, &sample_rate);
  995. if (err)
  996. break;
  997. snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate);
  998. }
  999. } else
  1000. snd_iprintf(buffer, "no firmware loaded\n");
  1001. snd_iprintf(buffer, "\n");
  1002. }
  1003. static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip)
  1004. {
  1005. struct snd_info_entry *entry;
  1006. if (! snd_card_proc_new(chip->card, "info", &entry))
  1007. snd_info_set_text_ops(entry, chip, 1024, pcxhr_proc_info);
  1008. if (! snd_card_proc_new(chip->card, "sync", &entry))
  1009. snd_info_set_text_ops(entry, chip, 1024, pcxhr_proc_sync);
  1010. }
  1011. /* end of proc interface */
  1012. /*
  1013. * release all the cards assigned to a manager instance
  1014. */
  1015. static int pcxhr_free(struct pcxhr_mgr *mgr)
  1016. {
  1017. unsigned int i;
  1018. for (i = 0; i < mgr->num_cards; i++) {
  1019. if (mgr->chip[i])
  1020. snd_card_free(mgr->chip[i]->card);
  1021. }
  1022. /* reset board if some firmware was loaded */
  1023. if(mgr->dsp_loaded) {
  1024. pcxhr_reset_board(mgr);
  1025. snd_printdd("reset pcxhr !\n");
  1026. }
  1027. /* release irq */
  1028. if (mgr->irq >= 0)
  1029. free_irq(mgr->irq, mgr);
  1030. pci_release_regions(mgr->pci);
  1031. /* free hostport purgebuffer */
  1032. if (mgr->hostport.area) {
  1033. snd_dma_free_pages(&mgr->hostport);
  1034. mgr->hostport.area = NULL;
  1035. }
  1036. kfree(mgr->prmh);
  1037. pci_disable_device(mgr->pci);
  1038. kfree(mgr);
  1039. return 0;
  1040. }
  1041. /*
  1042. * probe function - creates the card manager
  1043. */
  1044. static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1045. {
  1046. static int dev;
  1047. struct pcxhr_mgr *mgr;
  1048. unsigned int i;
  1049. int err;
  1050. size_t size;
  1051. char *card_name;
  1052. if (dev >= SNDRV_CARDS)
  1053. return -ENODEV;
  1054. if (! enable[dev]) {
  1055. dev++;
  1056. return -ENOENT;
  1057. }
  1058. /* enable PCI device */
  1059. if ((err = pci_enable_device(pci)) < 0)
  1060. return err;
  1061. pci_set_master(pci);
  1062. /* check if we can restrict PCI DMA transfers to 32 bits */
  1063. if (pci_set_dma_mask(pci, 0xffffffff) < 0) {
  1064. snd_printk(KERN_ERR "architecture does not support 32bit PCI busmaster DMA\n");
  1065. pci_disable_device(pci);
  1066. return -ENXIO;
  1067. }
  1068. /* alloc card manager */
  1069. mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
  1070. if (! mgr) {
  1071. pci_disable_device(pci);
  1072. return -ENOMEM;
  1073. }
  1074. snd_assert(pci_id->driver_data < PCI_ID_LAST, return -ENODEV);
  1075. card_name = pcxhr_board_params[pci_id->driver_data].board_name;
  1076. mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips;
  1077. mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips;
  1078. mgr->firmware_num = pcxhr_board_params[pci_id->driver_data].firmware_num;
  1079. mgr->mono_capture = mono[dev];
  1080. /* resource assignment */
  1081. if ((err = pci_request_regions(pci, card_name)) < 0) {
  1082. kfree(mgr);
  1083. pci_disable_device(pci);
  1084. return err;
  1085. }
  1086. for (i = 0; i < 3; i++)
  1087. mgr->port[i] = pci_resource_start(pci, i);
  1088. mgr->pci = pci;
  1089. mgr->irq = -1;
  1090. if (request_irq(pci->irq, pcxhr_interrupt, SA_INTERRUPT|SA_SHIRQ,
  1091. card_name, mgr)) {
  1092. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1093. pcxhr_free(mgr);
  1094. return -EBUSY;
  1095. }
  1096. mgr->irq = pci->irq;
  1097. sprintf(mgr->shortname, "Digigram %s", card_name);
  1098. sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->shortname,
  1099. mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
  1100. /* ISR spinlock */
  1101. spin_lock_init(&mgr->lock);
  1102. spin_lock_init(&mgr->msg_lock);
  1103. /* init setup mutex*/
  1104. init_MUTEX(&mgr->setup_mutex);
  1105. /* init taslket */
  1106. tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet, (unsigned long) mgr);
  1107. tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet, (unsigned long) mgr);
  1108. mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
  1109. sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS),
  1110. GFP_KERNEL);
  1111. if (! mgr->prmh) {
  1112. pcxhr_free(mgr);
  1113. return -ENOMEM;
  1114. }
  1115. for (i=0; i < PCXHR_MAX_CARDS; i++) {
  1116. struct snd_card *card;
  1117. char tmpid[16];
  1118. int idx;
  1119. if (i >= max(mgr->playback_chips, mgr->capture_chips))
  1120. break;
  1121. mgr->num_cards++;
  1122. if (index[dev] < 0)
  1123. idx = index[dev];
  1124. else
  1125. idx = index[dev] + i;
  1126. snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i);
  1127. card = snd_card_new(idx, tmpid, THIS_MODULE, 0);
  1128. if (! card) {
  1129. snd_printk(KERN_ERR "cannot allocate the card %d\n", i);
  1130. pcxhr_free(mgr);
  1131. return -ENOMEM;
  1132. }
  1133. strcpy(card->driver, DRIVER_NAME);
  1134. sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i);
  1135. sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i);
  1136. if ((err = pcxhr_create(mgr, card, i)) < 0) {
  1137. pcxhr_free(mgr);
  1138. return err;
  1139. }
  1140. if (i == 0)
  1141. /* init proc interface only for chip0 */
  1142. pcxhr_proc_init(mgr->chip[i]);
  1143. if ((err = snd_card_register(card)) < 0) {
  1144. pcxhr_free(mgr);
  1145. return err;
  1146. }
  1147. }
  1148. /* create hostport purgebuffer */
  1149. size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
  1150. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
  1151. size, &mgr->hostport) < 0) {
  1152. pcxhr_free(mgr);
  1153. return -ENOMEM;
  1154. }
  1155. /* init purgebuffer */
  1156. memset(mgr->hostport.area, 0, size);
  1157. /* create a DSP loader */
  1158. err = pcxhr_setup_firmware(mgr);
  1159. if (err < 0) {
  1160. pcxhr_free(mgr);
  1161. return err;
  1162. }
  1163. pci_set_drvdata(pci, mgr);
  1164. dev++;
  1165. return 0;
  1166. }
  1167. static void __devexit pcxhr_remove(struct pci_dev *pci)
  1168. {
  1169. pcxhr_free(pci_get_drvdata(pci));
  1170. pci_set_drvdata(pci, NULL);
  1171. }
  1172. static struct pci_driver driver = {
  1173. .name = "Digigram pcxhr",
  1174. .id_table = pcxhr_ids,
  1175. .probe = pcxhr_probe,
  1176. .remove = __devexit_p(pcxhr_remove),
  1177. };
  1178. static int __init pcxhr_module_init(void)
  1179. {
  1180. return pci_register_driver(&driver);
  1181. }
  1182. static void __exit pcxhr_module_exit(void)
  1183. {
  1184. pci_unregister_driver(&driver);
  1185. }
  1186. module_init(pcxhr_module_init)
  1187. module_exit(pcxhr_module_exit)