ppc4xx_dma.h 19 KB

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  1. /*
  2. * include/asm-ppc/ppc4xx_dma.h
  3. *
  4. * IBM PPC4xx DMA engine library
  5. *
  6. * Copyright 2000-2004 MontaVista Software Inc.
  7. *
  8. * Cleaned up a bit more, Matt Porter <mporter@kernel.crashing.org>
  9. *
  10. * Original code by Armin Kuster <akuster@mvista.com>
  11. * and Pete Popov <ppopov@mvista.com>
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. *
  18. * You should have received a copy of the GNU General Public License along
  19. * with this program; if not, write to the Free Software Foundation, Inc.,
  20. * 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #ifdef __KERNEL__
  23. #ifndef __ASMPPC_PPC4xx_DMA_H
  24. #define __ASMPPC_PPC4xx_DMA_H
  25. #include <linux/config.h>
  26. #include <linux/types.h>
  27. #include <asm/mmu.h>
  28. #include <asm/ibm4xx.h>
  29. #undef DEBUG_4xxDMA
  30. #define MAX_PPC4xx_DMA_CHANNELS 4
  31. /*
  32. * Function return status codes
  33. * These values are used to indicate whether or not the function
  34. * call was successful, or a bad/invalid parameter was passed.
  35. */
  36. #define DMA_STATUS_GOOD 0
  37. #define DMA_STATUS_BAD_CHANNEL 1
  38. #define DMA_STATUS_BAD_HANDLE 2
  39. #define DMA_STATUS_BAD_MODE 3
  40. #define DMA_STATUS_NULL_POINTER 4
  41. #define DMA_STATUS_OUT_OF_MEMORY 5
  42. #define DMA_STATUS_SGL_LIST_EMPTY 6
  43. #define DMA_STATUS_GENERAL_ERROR 7
  44. #define DMA_STATUS_CHANNEL_NOTFREE 8
  45. #define DMA_CHANNEL_BUSY 0x80000000
  46. /*
  47. * These indicate status as returned from the DMA Status Register.
  48. */
  49. #define DMA_STATUS_NO_ERROR 0
  50. #define DMA_STATUS_CS 1 /* Count Status */
  51. #define DMA_STATUS_TS 2 /* Transfer Status */
  52. #define DMA_STATUS_DMA_ERROR 3 /* DMA Error Occurred */
  53. #define DMA_STATUS_DMA_BUSY 4 /* The channel is busy */
  54. /*
  55. * DMA Channel Control Registers
  56. */
  57. #ifdef CONFIG_44x
  58. #define PPC4xx_DMA_64BIT
  59. #define DMA_CR_OFFSET 1
  60. #else
  61. #define DMA_CR_OFFSET 0
  62. #endif
  63. #define DMA_CE_ENABLE (1<<31) /* DMA Channel Enable */
  64. #define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31)
  65. #define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31)
  66. #define DMA_CIE_ENABLE (1<<30) /* DMA Channel Interrupt Enable */
  67. #define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30)
  68. #define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30)
  69. #define DMA_TD (1<<29)
  70. #define SET_DMA_TD(x) (((x)&0x1)<<29)
  71. #define GET_DMA_TD(x) (((x)&DMA_TD)>>29)
  72. #define DMA_PL (1<<28) /* Peripheral Location */
  73. #define SET_DMA_PL(x) (((x)&0x1)<<28)
  74. #define GET_DMA_PL(x) (((x)&DMA_PL)>>28)
  75. #define EXTERNAL_PERIPHERAL 0
  76. #define INTERNAL_PERIPHERAL 1
  77. #define SET_DMA_PW(x) (((x)&0x3)<<(26-DMA_CR_OFFSET)) /* Peripheral Width */
  78. #define DMA_PW_MASK SET_DMA_PW(3)
  79. #define PW_8 0
  80. #define PW_16 1
  81. #define PW_32 2
  82. #define PW_64 3
  83. /* FIXME: Add PW_128 support for 440GP DMA block */
  84. #define GET_DMA_PW(x) (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET))
  85. #define DMA_DAI (1<<(25-DMA_CR_OFFSET)) /* Destination Address Increment */
  86. #define SET_DMA_DAI(x) (((x)&0x1)<<(25-DMA_CR_OFFSET))
  87. #define DMA_SAI (1<<(24-DMA_CR_OFFSET)) /* Source Address Increment */
  88. #define SET_DMA_SAI(x) (((x)&0x1)<<(24-DMA_CR_OFFSET))
  89. #define DMA_BEN (1<<(23-DMA_CR_OFFSET)) /* Buffer Enable */
  90. #define SET_DMA_BEN(x) (((x)&0x1)<<(23-DMA_CR_OFFSET))
  91. #define SET_DMA_TM(x) (((x)&0x3)<<(21-DMA_CR_OFFSET)) /* Transfer Mode */
  92. #define DMA_TM_MASK SET_DMA_TM(3)
  93. #define TM_PERIPHERAL 0 /* Peripheral */
  94. #define TM_RESERVED 1 /* Reserved */
  95. #define TM_S_MM 2 /* Memory to Memory */
  96. #define TM_D_MM 3 /* Device Paced Memory to Memory */
  97. #define GET_DMA_TM(x) (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET))
  98. #define SET_DMA_PSC(x) (((x)&0x3)<<(19-DMA_CR_OFFSET)) /* Peripheral Setup Cycles */
  99. #define DMA_PSC_MASK SET_DMA_PSC(3)
  100. #define GET_DMA_PSC(x) (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET))
  101. #define SET_DMA_PWC(x) (((x)&0x3F)<<(13-DMA_CR_OFFSET)) /* Peripheral Wait Cycles */
  102. #define DMA_PWC_MASK SET_DMA_PWC(0x3F)
  103. #define GET_DMA_PWC(x) (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET))
  104. #define SET_DMA_PHC(x) (((x)&0x7)<<(10-DMA_CR_OFFSET)) /* Peripheral Hold Cycles */
  105. #define DMA_PHC_MASK SET_DMA_PHC(0x7)
  106. #define GET_DMA_PHC(x) (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET))
  107. #define DMA_ETD_OUTPUT (1<<(9-DMA_CR_OFFSET)) /* EOT pin is a TC output */
  108. #define SET_DMA_ETD(x) (((x)&0x1)<<(9-DMA_CR_OFFSET))
  109. #define DMA_TCE_ENABLE (1<<(8-DMA_CR_OFFSET))
  110. #define SET_DMA_TCE(x) (((x)&0x1)<<(8-DMA_CR_OFFSET))
  111. #define DMA_DEC (1<<(2)) /* Address Decrement */
  112. #define SET_DMA_DEC(x) (((x)&0x1)<<2)
  113. #define GET_DMA_DEC(x) (((x)&DMA_DEC)>>2)
  114. /*
  115. * Transfer Modes
  116. * These modes are defined in a way that makes it possible to
  117. * simply "or" in the value in the control register.
  118. */
  119. #define DMA_MODE_MM (SET_DMA_TM(TM_S_MM)) /* memory to memory */
  120. /* Device-paced memory to memory, */
  121. /* device is at source address */
  122. #define DMA_MODE_MM_DEVATSRC (DMA_TD | SET_DMA_TM(TM_D_MM))
  123. /* Device-paced memory to memory, */
  124. /* device is at destination address */
  125. #define DMA_MODE_MM_DEVATDST (SET_DMA_TM(TM_D_MM))
  126. /* 405gp/440gp */
  127. #define SET_DMA_PREFETCH(x) (((x)&0x3)<<(4-DMA_CR_OFFSET)) /* Memory Read Prefetch */
  128. #define DMA_PREFETCH_MASK SET_DMA_PREFETCH(3)
  129. #define PREFETCH_1 0 /* Prefetch 1 Double Word */
  130. #define PREFETCH_2 1
  131. #define PREFETCH_4 2
  132. #define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET))
  133. #define DMA_PCE (1<<(3-DMA_CR_OFFSET)) /* Parity Check Enable */
  134. #define SET_DMA_PCE(x) (((x)&0x1)<<(3-DMA_CR_OFFSET))
  135. #define GET_DMA_PCE(x) (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET))
  136. /* stb3x */
  137. #define DMA_ECE_ENABLE (1<<5)
  138. #define SET_DMA_ECE(x) (((x)&0x1)<<5)
  139. #define GET_DMA_ECE(x) (((x)&DMA_ECE_ENABLE)>>5)
  140. #define DMA_TCD_DISABLE (1<<4)
  141. #define SET_DMA_TCD(x) (((x)&0x1)<<4)
  142. #define GET_DMA_TCD(x) (((x)&DMA_TCD_DISABLE)>>4)
  143. typedef uint32_t sgl_handle_t;
  144. #ifdef CONFIG_PPC4xx_EDMA
  145. #define SGL_LIST_SIZE 4096
  146. #define DMA_PPC4xx_SIZE SGL_LIST_SIZE
  147. #define SET_DMA_PRIORITY(x) (((x)&0x3)<<(6-DMA_CR_OFFSET)) /* DMA Channel Priority */
  148. #define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3)
  149. #define PRIORITY_LOW 0
  150. #define PRIORITY_MID_LOW 1
  151. #define PRIORITY_MID_HIGH 2
  152. #define PRIORITY_HIGH 3
  153. #define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET))
  154. /*
  155. * DMA Polarity Configuration Register
  156. */
  157. #define DMAReq_ActiveLow(chan) (1<<(31-(chan*3)))
  158. #define DMAAck_ActiveLow(chan) (1<<(30-(chan*3)))
  159. #define EOT_ActiveLow(chan) (1<<(29-(chan*3))) /* End of Transfer */
  160. /*
  161. * DMA Sleep Mode Register
  162. */
  163. #define SLEEP_MODE_ENABLE (1<<21)
  164. /*
  165. * DMA Status Register
  166. */
  167. #define DMA_CS0 (1<<31) /* Terminal Count has been reached */
  168. #define DMA_CS1 (1<<30)
  169. #define DMA_CS2 (1<<29)
  170. #define DMA_CS3 (1<<28)
  171. #define DMA_TS0 (1<<27) /* End of Transfer has been requested */
  172. #define DMA_TS1 (1<<26)
  173. #define DMA_TS2 (1<<25)
  174. #define DMA_TS3 (1<<24)
  175. #define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */
  176. #define DMA_CH1_ERR (1<<22)
  177. #define DMA_CH2_ERR (1<<21)
  178. #define DMA_CH3_ERR (1<<20)
  179. #define DMA_IN_DMA_REQ0 (1<<19) /* Internal DMA Request is pending */
  180. #define DMA_IN_DMA_REQ1 (1<<18)
  181. #define DMA_IN_DMA_REQ2 (1<<17)
  182. #define DMA_IN_DMA_REQ3 (1<<16)
  183. #define DMA_EXT_DMA_REQ0 (1<<15) /* External DMA Request is pending */
  184. #define DMA_EXT_DMA_REQ1 (1<<14)
  185. #define DMA_EXT_DMA_REQ2 (1<<13)
  186. #define DMA_EXT_DMA_REQ3 (1<<12)
  187. #define DMA_CH0_BUSY (1<<11) /* DMA Channel 0 Busy */
  188. #define DMA_CH1_BUSY (1<<10)
  189. #define DMA_CH2_BUSY (1<<9)
  190. #define DMA_CH3_BUSY (1<<8)
  191. #define DMA_SG0 (1<<7) /* DMA Channel 0 Scatter/Gather in progress */
  192. #define DMA_SG1 (1<<6)
  193. #define DMA_SG2 (1<<5)
  194. #define DMA_SG3 (1<<4)
  195. /* DMA Channel Count Register */
  196. #define DMA_CTC_BTEN (1<<23) /* Burst Enable/Disable bit */
  197. #define DMA_CTC_BSIZ_MSK (3<<21) /* Mask of the Burst size bits */
  198. #define DMA_CTC_BSIZ_2 (0)
  199. #define DMA_CTC_BSIZ_4 (1<<21)
  200. #define DMA_CTC_BSIZ_8 (2<<21)
  201. #define DMA_CTC_BSIZ_16 (3<<21)
  202. /*
  203. * DMA SG Command Register
  204. */
  205. #define SSG_ENABLE(chan) (1<<(31-chan)) /* Start Scatter Gather */
  206. #define SSG_MASK_ENABLE(chan) (1<<(15-chan)) /* Enable writing to SSG0 bit */
  207. /*
  208. * DMA Scatter/Gather Descriptor Bit fields
  209. */
  210. #define SG_LINK (1<<31) /* Link */
  211. #define SG_TCI_ENABLE (1<<29) /* Enable Terminal Count Interrupt */
  212. #define SG_ETI_ENABLE (1<<28) /* Enable End of Transfer Interrupt */
  213. #define SG_ERI_ENABLE (1<<27) /* Enable Error Interrupt */
  214. #define SG_COUNT_MASK 0xFFFF /* Count Field */
  215. #define SET_DMA_CONTROL \
  216. (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \
  217. SET_DMA_BEN(p_init->buffer_enable) | /* buffer enable */\
  218. SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \
  219. SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \
  220. SET_DMA_PL(p_init->pl) | /* peripheral location */ \
  221. SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \
  222. SET_DMA_SAI(p_init->sai) | /* src addr increment */ \
  223. SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \
  224. SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \
  225. SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \
  226. SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \
  227. SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \
  228. SET_DMA_PREFETCH(p_init->pf) /* read prefetch */)
  229. #define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan))
  230. #elif defined(CONFIG_STB03xxx) /* stb03xxx */
  231. #define DMA_PPC4xx_SIZE 4096
  232. /*
  233. * DMA Status Register
  234. */
  235. #define SET_DMA_PRIORITY(x) (((x)&0x00800001)) /* DMA Channel Priority */
  236. #define DMA_PRIORITY_MASK 0x00800001
  237. #define PRIORITY_LOW 0x00000000
  238. #define PRIORITY_MID_LOW 0x00000001
  239. #define PRIORITY_MID_HIGH 0x00800000
  240. #define PRIORITY_HIGH 0x00800001
  241. #define GET_DMA_PRIORITY(x) (((((x)&DMA_PRIORITY_MASK) &0x00800000) >> 22 ) | (((x)&DMA_PRIORITY_MASK) &0x00000001))
  242. #define DMA_CS0 (1<<31) /* Terminal Count has been reached */
  243. #define DMA_CS1 (1<<30)
  244. #define DMA_CS2 (1<<29)
  245. #define DMA_CS3 (1<<28)
  246. #define DMA_TS0 (1<<27) /* End of Transfer has been requested */
  247. #define DMA_TS1 (1<<26)
  248. #define DMA_TS2 (1<<25)
  249. #define DMA_TS3 (1<<24)
  250. #define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */
  251. #define DMA_CH1_ERR (1<<22)
  252. #define DMA_CH2_ERR (1<<21)
  253. #define DMA_CH3_ERR (1<<20)
  254. #define DMA_CT0 (1<<19) /* Chained transfere */
  255. #define DMA_IN_DMA_REQ0 (1<<18) /* Internal DMA Request is pending */
  256. #define DMA_IN_DMA_REQ1 (1<<17)
  257. #define DMA_IN_DMA_REQ2 (1<<16)
  258. #define DMA_IN_DMA_REQ3 (1<<15)
  259. #define DMA_EXT_DMA_REQ0 (1<<14) /* External DMA Request is pending */
  260. #define DMA_EXT_DMA_REQ1 (1<<13)
  261. #define DMA_EXT_DMA_REQ2 (1<<12)
  262. #define DMA_EXT_DMA_REQ3 (1<<11)
  263. #define DMA_CH0_BUSY (1<<10) /* DMA Channel 0 Busy */
  264. #define DMA_CH1_BUSY (1<<9)
  265. #define DMA_CH2_BUSY (1<<8)
  266. #define DMA_CH3_BUSY (1<<7)
  267. #define DMA_CT1 (1<<6) /* Chained transfere */
  268. #define DMA_CT2 (1<<5)
  269. #define DMA_CT3 (1<<4)
  270. #define DMA_CH_ENABLE (1<<7)
  271. #define SET_DMA_CH(x) (((x)&0x1)<<7)
  272. #define GET_DMA_CH(x) (((x)&DMA_CH_ENABLE)>>7)
  273. /* STBx25xxx dma unique */
  274. /* enable device port on a dma channel
  275. * example ext 0 on dma 1
  276. */
  277. #define SSP0_RECV 15
  278. #define SSP0_XMIT 14
  279. #define EXT_DMA_0 12
  280. #define SC1_XMIT 11
  281. #define SC1_RECV 10
  282. #define EXT_DMA_2 9
  283. #define EXT_DMA_3 8
  284. #define SERIAL2_XMIT 7
  285. #define SERIAL2_RECV 6
  286. #define SC0_XMIT 5
  287. #define SC0_RECV 4
  288. #define SERIAL1_XMIT 3
  289. #define SERIAL1_RECV 2
  290. #define SERIAL0_XMIT 1
  291. #define SERIAL0_RECV 0
  292. #define DMA_CHAN_0 1
  293. #define DMA_CHAN_1 2
  294. #define DMA_CHAN_2 3
  295. #define DMA_CHAN_3 4
  296. /* end STBx25xx */
  297. /*
  298. * Bit 30 must be one for Redwoods, otherwise transfers may receive errors.
  299. */
  300. #define DMA_CR_MB0 0x2
  301. #define SET_DMA_CONTROL \
  302. (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable */ \
  303. SET_DMA_ETD(p_init->etd_output) | /* end of transfer pin */ \
  304. SET_DMA_TCE(p_init->tce_enable) | /* terminal count enable */ \
  305. SET_DMA_PL(p_init->pl) | /* peripheral location */ \
  306. SET_DMA_DAI(p_init->dai) | /* dest addr increment */ \
  307. SET_DMA_SAI(p_init->sai) | /* src addr increment */ \
  308. SET_DMA_PRIORITY(p_init->cp) | /* channel priority */ \
  309. SET_DMA_PW(p_init->pwidth) | /* peripheral/bus width */ \
  310. SET_DMA_PSC(p_init->psc) | /* peripheral setup cycles */ \
  311. SET_DMA_PWC(p_init->pwc) | /* peripheral wait cycles */ \
  312. SET_DMA_PHC(p_init->phc) | /* peripheral hold cycles */ \
  313. SET_DMA_TCD(p_init->tcd_disable) | /* TC chain mode disable */ \
  314. SET_DMA_ECE(p_init->ece_enable) | /* ECE chanin mode enable */ \
  315. SET_DMA_CH(p_init->ch_enable) | /* Chain enable */ \
  316. DMA_CR_MB0 /* must be one */)
  317. #define GET_DMA_POLARITY(chan) chan
  318. #endif
  319. typedef struct {
  320. unsigned short in_use; /* set when channel is being used, clr when
  321. * available.
  322. */
  323. /*
  324. * Valid polarity settings:
  325. * DMAReq_ActiveLow(n)
  326. * DMAAck_ActiveLow(n)
  327. * EOT_ActiveLow(n)
  328. *
  329. * n is 0 to max dma chans
  330. */
  331. unsigned int polarity;
  332. char buffer_enable; /* Boolean: buffer enable */
  333. char tce_enable; /* Boolean: terminal count enable */
  334. char etd_output; /* Boolean: eot pin is a tc output */
  335. char pce; /* Boolean: parity check enable */
  336. /*
  337. * Peripheral location:
  338. * INTERNAL_PERIPHERAL (UART0 on the 405GP)
  339. * EXTERNAL_PERIPHERAL
  340. */
  341. char pl; /* internal/external peripheral */
  342. /*
  343. * Valid pwidth settings:
  344. * PW_8
  345. * PW_16
  346. * PW_32
  347. * PW_64
  348. */
  349. unsigned int pwidth;
  350. char dai; /* Boolean: dst address increment */
  351. char sai; /* Boolean: src address increment */
  352. /*
  353. * Valid psc settings: 0-3
  354. */
  355. unsigned int psc; /* Peripheral Setup Cycles */
  356. /*
  357. * Valid pwc settings:
  358. * 0-63
  359. */
  360. unsigned int pwc; /* Peripheral Wait Cycles */
  361. /*
  362. * Valid phc settings:
  363. * 0-7
  364. */
  365. unsigned int phc; /* Peripheral Hold Cycles */
  366. /*
  367. * Valid cp (channel priority) settings:
  368. * PRIORITY_LOW
  369. * PRIORITY_MID_LOW
  370. * PRIORITY_MID_HIGH
  371. * PRIORITY_HIGH
  372. */
  373. unsigned int cp; /* channel priority */
  374. /*
  375. * Valid pf (memory read prefetch) settings:
  376. *
  377. * PREFETCH_1
  378. * PREFETCH_2
  379. * PREFETCH_4
  380. */
  381. unsigned int pf; /* memory read prefetch */
  382. /*
  383. * Boolean: channel interrupt enable
  384. * NOTE: for sgl transfers, only the last descriptor will be setup to
  385. * interrupt.
  386. */
  387. char int_enable;
  388. char shift; /* easy access to byte_count shift, based on */
  389. /* the width of the channel */
  390. uint32_t control; /* channel control word */
  391. /* These variabled are used ONLY in single dma transfers */
  392. unsigned int mode; /* transfer mode */
  393. phys_addr_t addr;
  394. char ce; /* channel enable */
  395. #ifdef CONFIG_STB03xxx
  396. char ch_enable;
  397. char tcd_disable;
  398. char ece_enable;
  399. char td; /* transfer direction */
  400. #endif
  401. char int_on_final_sg;/* for scatter/gather - only interrupt on last sg */
  402. } ppc_dma_ch_t;
  403. /*
  404. * PPC44x DMA implementations have a slightly different
  405. * descriptor layout. Probably moved about due to the
  406. * change to 64-bit addresses and link pointer. I don't
  407. * know why they didn't just leave control_count after
  408. * the dst_addr.
  409. */
  410. #ifdef PPC4xx_DMA_64BIT
  411. typedef struct {
  412. uint32_t control;
  413. uint32_t control_count;
  414. phys_addr_t src_addr;
  415. phys_addr_t dst_addr;
  416. phys_addr_t next;
  417. } ppc_sgl_t;
  418. #else
  419. typedef struct {
  420. uint32_t control;
  421. phys_addr_t src_addr;
  422. phys_addr_t dst_addr;
  423. uint32_t control_count;
  424. uint32_t next;
  425. } ppc_sgl_t;
  426. #endif
  427. typedef struct {
  428. unsigned int dmanr;
  429. uint32_t control; /* channel ctrl word; loaded from each descrptr */
  430. uint32_t sgl_control; /* LK, TCI, ETI, and ERI bits in sgl descriptor */
  431. dma_addr_t dma_addr; /* dma (physical) address of this list */
  432. ppc_sgl_t *phead;
  433. dma_addr_t phead_dma;
  434. ppc_sgl_t *ptail;
  435. dma_addr_t ptail_dma;
  436. } sgl_list_info_t;
  437. typedef struct {
  438. phys_addr_t *src_addr;
  439. phys_addr_t *dst_addr;
  440. phys_addr_t dma_src_addr;
  441. phys_addr_t dma_dst_addr;
  442. } pci_alloc_desc_t;
  443. extern ppc_dma_ch_t dma_channels[];
  444. /*
  445. * The DMA API are in ppc4xx_dma.c and ppc4xx_sgdma.c
  446. */
  447. extern int ppc4xx_init_dma_channel(unsigned int, ppc_dma_ch_t *);
  448. extern int ppc4xx_get_channel_config(unsigned int, ppc_dma_ch_t *);
  449. extern int ppc4xx_set_channel_priority(unsigned int, unsigned int);
  450. extern unsigned int ppc4xx_get_peripheral_width(unsigned int);
  451. extern void ppc4xx_set_sg_addr(int, phys_addr_t);
  452. extern int ppc4xx_add_dma_sgl(sgl_handle_t, phys_addr_t, phys_addr_t, unsigned int);
  453. extern void ppc4xx_enable_dma_sgl(sgl_handle_t);
  454. extern void ppc4xx_disable_dma_sgl(sgl_handle_t);
  455. extern int ppc4xx_get_dma_sgl_residue(sgl_handle_t, phys_addr_t *, phys_addr_t *);
  456. extern int ppc4xx_delete_dma_sgl_element(sgl_handle_t, phys_addr_t *, phys_addr_t *);
  457. extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int);
  458. extern void ppc4xx_free_dma_handle(sgl_handle_t);
  459. extern int ppc4xx_get_dma_status(void);
  460. extern int ppc4xx_enable_burst(unsigned int);
  461. extern int ppc4xx_disable_burst(unsigned int);
  462. extern int ppc4xx_set_burst_size(unsigned int, unsigned int);
  463. extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr);
  464. extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr);
  465. extern void ppc4xx_enable_dma(unsigned int dmanr);
  466. extern void ppc4xx_disable_dma(unsigned int dmanr);
  467. extern void ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count);
  468. extern int ppc4xx_get_dma_residue(unsigned int dmanr);
  469. extern void ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr,
  470. phys_addr_t dst_dma_addr);
  471. extern int ppc4xx_enable_dma_interrupt(unsigned int dmanr);
  472. extern int ppc4xx_disable_dma_interrupt(unsigned int dmanr);
  473. extern int ppc4xx_clr_dma_status(unsigned int dmanr);
  474. extern int ppc4xx_map_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan);
  475. extern int ppc4xx_disable_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan);
  476. extern int ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode);
  477. /* These are in kernel/dma.c: */
  478. /* reserve a DMA channel */
  479. extern int request_dma(unsigned int dmanr, const char *device_id);
  480. /* release it again */
  481. extern void free_dma(unsigned int dmanr);
  482. #endif
  483. #endif /* __KERNEL__ */