pgtable-3level.h 4.1 KB

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  1. #ifndef _I386_PGTABLE_3LEVEL_H
  2. #define _I386_PGTABLE_3LEVEL_H
  3. #include <asm-generic/pgtable-nopud.h>
  4. /*
  5. * Intel Physical Address Extension (PAE) Mode - three-level page
  6. * tables on PPro+ CPUs.
  7. *
  8. * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
  9. */
  10. #define pte_ERROR(e) \
  11. printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
  12. #define pmd_ERROR(e) \
  13. printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
  14. #define pgd_ERROR(e) \
  15. printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
  16. #define pud_none(pud) 0
  17. #define pud_bad(pud) 0
  18. #define pud_present(pud) 1
  19. /*
  20. * Is the pte executable?
  21. */
  22. static inline int pte_x(pte_t pte)
  23. {
  24. return !(pte_val(pte) & _PAGE_NX);
  25. }
  26. /*
  27. * All present user-pages with !NX bit are user-executable:
  28. */
  29. static inline int pte_exec(pte_t pte)
  30. {
  31. return pte_user(pte) && pte_x(pte);
  32. }
  33. /*
  34. * All present pages with !NX bit are kernel-executable:
  35. */
  36. static inline int pte_exec_kernel(pte_t pte)
  37. {
  38. return pte_x(pte);
  39. }
  40. /* Rules for using set_pte: the pte being assigned *must* be
  41. * either not present or in a state where the hardware will
  42. * not attempt to update the pte. In places where this is
  43. * not possible, use pte_get_and_clear to obtain the old pte
  44. * value and then use set_pte to update it. -ben
  45. */
  46. static inline void set_pte(pte_t *ptep, pte_t pte)
  47. {
  48. ptep->pte_high = pte.pte_high;
  49. smp_wmb();
  50. ptep->pte_low = pte.pte_low;
  51. }
  52. #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
  53. #define __HAVE_ARCH_SET_PTE_ATOMIC
  54. #define set_pte_atomic(pteptr,pteval) \
  55. set_64bit((unsigned long long *)(pteptr),pte_val(pteval))
  56. #define set_pmd(pmdptr,pmdval) \
  57. set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
  58. #define set_pud(pudptr,pudval) \
  59. (*(pudptr) = (pudval))
  60. /*
  61. * Pentium-II erratum A13: in PAE mode we explicitly have to flush
  62. * the TLB via cr3 if the top-level pgd is changed...
  63. * We do not let the generic code free and clear pgd entries due to
  64. * this erratum.
  65. */
  66. static inline void pud_clear (pud_t * pud) { }
  67. #define pud_page(pud) \
  68. ((struct page *) __va(pud_val(pud) & PAGE_MASK))
  69. #define pud_page_kernel(pud) \
  70. ((unsigned long) __va(pud_val(pud) & PAGE_MASK))
  71. /* Find an entry in the second-level page table.. */
  72. #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
  73. pmd_index(address))
  74. static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
  75. {
  76. pte_t res;
  77. /* xchg acts as a barrier before the setting of the high bits */
  78. res.pte_low = xchg(&ptep->pte_low, 0);
  79. res.pte_high = ptep->pte_high;
  80. ptep->pte_high = 0;
  81. return res;
  82. }
  83. static inline int pte_same(pte_t a, pte_t b)
  84. {
  85. return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
  86. }
  87. #define pte_page(x) pfn_to_page(pte_pfn(x))
  88. static inline int pte_none(pte_t pte)
  89. {
  90. return !pte.pte_low && !pte.pte_high;
  91. }
  92. static inline unsigned long pte_pfn(pte_t pte)
  93. {
  94. return (pte.pte_low >> PAGE_SHIFT) |
  95. (pte.pte_high << (32 - PAGE_SHIFT));
  96. }
  97. extern unsigned long long __supported_pte_mask;
  98. static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
  99. {
  100. pte_t pte;
  101. pte.pte_high = (page_nr >> (32 - PAGE_SHIFT)) | \
  102. (pgprot_val(pgprot) >> 32);
  103. pte.pte_high &= (__supported_pte_mask >> 32);
  104. pte.pte_low = ((page_nr << PAGE_SHIFT) | pgprot_val(pgprot)) & \
  105. __supported_pte_mask;
  106. return pte;
  107. }
  108. static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
  109. {
  110. return __pmd((((unsigned long long)page_nr << PAGE_SHIFT) | \
  111. pgprot_val(pgprot)) & __supported_pte_mask);
  112. }
  113. /*
  114. * Bits 0, 6 and 7 are taken in the low part of the pte,
  115. * put the 32 bits of offset into the high part.
  116. */
  117. #define pte_to_pgoff(pte) ((pte).pte_high)
  118. #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
  119. #define PTE_FILE_MAX_BITS 32
  120. /* Encode and de-code a swap entry */
  121. #define __swp_type(x) (((x).val) & 0x1f)
  122. #define __swp_offset(x) ((x).val >> 5)
  123. #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
  124. #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
  125. #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
  126. #define __pmd_free_tlb(tlb, x) do { } while (0)
  127. #endif /* _I386_PGTABLE_3LEVEL_H */