megaraid_sas.h 23 KB

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  1. /*
  2. *
  3. * Linux MegaRAID driver for SAS based RAID controllers
  4. *
  5. * Copyright (c) 2003-2005 LSI Logic Corporation.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. *
  12. * FILE : megaraid_sas.h
  13. */
  14. #ifndef LSI_MEGARAID_SAS_H
  15. #define LSI_MEGARAID_SAS_H
  16. /**
  17. * MegaRAID SAS Driver meta data
  18. */
  19. #define MEGASAS_VERSION "00.00.02.00-rc4"
  20. #define MEGASAS_RELDATE "Sep 16, 2005"
  21. #define MEGASAS_EXT_VERSION "Fri Sep 16 12:37:08 EDT 2005"
  22. /*
  23. * =====================================
  24. * MegaRAID SAS MFI firmware definitions
  25. * =====================================
  26. */
  27. /*
  28. * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
  29. * protocol between the software and firmware. Commands are issued using
  30. * "message frames"
  31. */
  32. /**
  33. * FW posts its state in upper 4 bits of outbound_msg_0 register
  34. */
  35. #define MFI_STATE_MASK 0xF0000000
  36. #define MFI_STATE_UNDEFINED 0x00000000
  37. #define MFI_STATE_BB_INIT 0x10000000
  38. #define MFI_STATE_FW_INIT 0x40000000
  39. #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
  40. #define MFI_STATE_FW_INIT_2 0x70000000
  41. #define MFI_STATE_DEVICE_SCAN 0x80000000
  42. #define MFI_STATE_FLUSH_CACHE 0xA0000000
  43. #define MFI_STATE_READY 0xB0000000
  44. #define MFI_STATE_OPERATIONAL 0xC0000000
  45. #define MFI_STATE_FAULT 0xF0000000
  46. #define MEGAMFI_FRAME_SIZE 64
  47. /**
  48. * During FW init, clear pending cmds & reset state using inbound_msg_0
  49. *
  50. * ABORT : Abort all pending cmds
  51. * READY : Move from OPERATIONAL to READY state; discard queue info
  52. * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
  53. * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
  54. */
  55. #define MFI_INIT_ABORT 0x00000000
  56. #define MFI_INIT_READY 0x00000002
  57. #define MFI_INIT_MFIMODE 0x00000004
  58. #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
  59. #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE
  60. /**
  61. * MFI frame flags
  62. */
  63. #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
  64. #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
  65. #define MFI_FRAME_SGL32 0x0000
  66. #define MFI_FRAME_SGL64 0x0002
  67. #define MFI_FRAME_SENSE32 0x0000
  68. #define MFI_FRAME_SENSE64 0x0004
  69. #define MFI_FRAME_DIR_NONE 0x0000
  70. #define MFI_FRAME_DIR_WRITE 0x0008
  71. #define MFI_FRAME_DIR_READ 0x0010
  72. #define MFI_FRAME_DIR_BOTH 0x0018
  73. /**
  74. * Definition for cmd_status
  75. */
  76. #define MFI_CMD_STATUS_POLL_MODE 0xFF
  77. /**
  78. * MFI command opcodes
  79. */
  80. #define MFI_CMD_INIT 0x00
  81. #define MFI_CMD_LD_READ 0x01
  82. #define MFI_CMD_LD_WRITE 0x02
  83. #define MFI_CMD_LD_SCSI_IO 0x03
  84. #define MFI_CMD_PD_SCSI_IO 0x04
  85. #define MFI_CMD_DCMD 0x05
  86. #define MFI_CMD_ABORT 0x06
  87. #define MFI_CMD_SMP 0x07
  88. #define MFI_CMD_STP 0x08
  89. #define MR_DCMD_CTRL_GET_INFO 0x01010000
  90. #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
  91. #define MR_FLUSH_CTRL_CACHE 0x01
  92. #define MR_FLUSH_DISK_CACHE 0x02
  93. #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
  94. #define MR_ENABLE_DRIVE_SPINDOWN 0x01
  95. #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
  96. #define MR_DCMD_CTRL_EVENT_GET 0x01040300
  97. #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
  98. #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
  99. #define MR_DCMD_CLUSTER 0x08000000
  100. #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
  101. #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
  102. /**
  103. * MFI command completion codes
  104. */
  105. enum MFI_STAT {
  106. MFI_STAT_OK = 0x00,
  107. MFI_STAT_INVALID_CMD = 0x01,
  108. MFI_STAT_INVALID_DCMD = 0x02,
  109. MFI_STAT_INVALID_PARAMETER = 0x03,
  110. MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
  111. MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
  112. MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
  113. MFI_STAT_APP_IN_USE = 0x07,
  114. MFI_STAT_APP_NOT_INITIALIZED = 0x08,
  115. MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
  116. MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
  117. MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
  118. MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
  119. MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
  120. MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
  121. MFI_STAT_FLASH_BUSY = 0x0f,
  122. MFI_STAT_FLASH_ERROR = 0x10,
  123. MFI_STAT_FLASH_IMAGE_BAD = 0x11,
  124. MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
  125. MFI_STAT_FLASH_NOT_OPEN = 0x13,
  126. MFI_STAT_FLASH_NOT_STARTED = 0x14,
  127. MFI_STAT_FLUSH_FAILED = 0x15,
  128. MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
  129. MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
  130. MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
  131. MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
  132. MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
  133. MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
  134. MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
  135. MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
  136. MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
  137. MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
  138. MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
  139. MFI_STAT_MFC_HW_ERROR = 0x21,
  140. MFI_STAT_NO_HW_PRESENT = 0x22,
  141. MFI_STAT_NOT_FOUND = 0x23,
  142. MFI_STAT_NOT_IN_ENCL = 0x24,
  143. MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
  144. MFI_STAT_PD_TYPE_WRONG = 0x26,
  145. MFI_STAT_PR_DISABLED = 0x27,
  146. MFI_STAT_ROW_INDEX_INVALID = 0x28,
  147. MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
  148. MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
  149. MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
  150. MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
  151. MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
  152. MFI_STAT_SCSI_IO_FAILED = 0x2e,
  153. MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
  154. MFI_STAT_SHUTDOWN_FAILED = 0x30,
  155. MFI_STAT_TIME_NOT_SET = 0x31,
  156. MFI_STAT_WRONG_STATE = 0x32,
  157. MFI_STAT_LD_OFFLINE = 0x33,
  158. MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
  159. MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
  160. MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
  161. MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
  162. MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
  163. MFI_STAT_INVALID_STATUS = 0xFF
  164. };
  165. /*
  166. * Number of mailbox bytes in DCMD message frame
  167. */
  168. #define MFI_MBOX_SIZE 12
  169. enum MR_EVT_CLASS {
  170. MR_EVT_CLASS_DEBUG = -2,
  171. MR_EVT_CLASS_PROGRESS = -1,
  172. MR_EVT_CLASS_INFO = 0,
  173. MR_EVT_CLASS_WARNING = 1,
  174. MR_EVT_CLASS_CRITICAL = 2,
  175. MR_EVT_CLASS_FATAL = 3,
  176. MR_EVT_CLASS_DEAD = 4,
  177. };
  178. enum MR_EVT_LOCALE {
  179. MR_EVT_LOCALE_LD = 0x0001,
  180. MR_EVT_LOCALE_PD = 0x0002,
  181. MR_EVT_LOCALE_ENCL = 0x0004,
  182. MR_EVT_LOCALE_BBU = 0x0008,
  183. MR_EVT_LOCALE_SAS = 0x0010,
  184. MR_EVT_LOCALE_CTRL = 0x0020,
  185. MR_EVT_LOCALE_CONFIG = 0x0040,
  186. MR_EVT_LOCALE_CLUSTER = 0x0080,
  187. MR_EVT_LOCALE_ALL = 0xffff,
  188. };
  189. enum MR_EVT_ARGS {
  190. MR_EVT_ARGS_NONE,
  191. MR_EVT_ARGS_CDB_SENSE,
  192. MR_EVT_ARGS_LD,
  193. MR_EVT_ARGS_LD_COUNT,
  194. MR_EVT_ARGS_LD_LBA,
  195. MR_EVT_ARGS_LD_OWNER,
  196. MR_EVT_ARGS_LD_LBA_PD_LBA,
  197. MR_EVT_ARGS_LD_PROG,
  198. MR_EVT_ARGS_LD_STATE,
  199. MR_EVT_ARGS_LD_STRIP,
  200. MR_EVT_ARGS_PD,
  201. MR_EVT_ARGS_PD_ERR,
  202. MR_EVT_ARGS_PD_LBA,
  203. MR_EVT_ARGS_PD_LBA_LD,
  204. MR_EVT_ARGS_PD_PROG,
  205. MR_EVT_ARGS_PD_STATE,
  206. MR_EVT_ARGS_PCI,
  207. MR_EVT_ARGS_RATE,
  208. MR_EVT_ARGS_STR,
  209. MR_EVT_ARGS_TIME,
  210. MR_EVT_ARGS_ECC,
  211. };
  212. /*
  213. * SAS controller properties
  214. */
  215. struct megasas_ctrl_prop {
  216. u16 seq_num;
  217. u16 pred_fail_poll_interval;
  218. u16 intr_throttle_count;
  219. u16 intr_throttle_timeouts;
  220. u8 rebuild_rate;
  221. u8 patrol_read_rate;
  222. u8 bgi_rate;
  223. u8 cc_rate;
  224. u8 recon_rate;
  225. u8 cache_flush_interval;
  226. u8 spinup_drv_count;
  227. u8 spinup_delay;
  228. u8 cluster_enable;
  229. u8 coercion_mode;
  230. u8 alarm_enable;
  231. u8 disable_auto_rebuild;
  232. u8 disable_battery_warn;
  233. u8 ecc_bucket_size;
  234. u16 ecc_bucket_leak_rate;
  235. u8 restore_hotspare_on_insertion;
  236. u8 expose_encl_devices;
  237. u8 reserved[38];
  238. } __attribute__ ((packed));
  239. /*
  240. * SAS controller information
  241. */
  242. struct megasas_ctrl_info {
  243. /*
  244. * PCI device information
  245. */
  246. struct {
  247. u16 vendor_id;
  248. u16 device_id;
  249. u16 sub_vendor_id;
  250. u16 sub_device_id;
  251. u8 reserved[24];
  252. } __attribute__ ((packed)) pci;
  253. /*
  254. * Host interface information
  255. */
  256. struct {
  257. u8 PCIX:1;
  258. u8 PCIE:1;
  259. u8 iSCSI:1;
  260. u8 SAS_3G:1;
  261. u8 reserved_0:4;
  262. u8 reserved_1[6];
  263. u8 port_count;
  264. u64 port_addr[8];
  265. } __attribute__ ((packed)) host_interface;
  266. /*
  267. * Device (backend) interface information
  268. */
  269. struct {
  270. u8 SPI:1;
  271. u8 SAS_3G:1;
  272. u8 SATA_1_5G:1;
  273. u8 SATA_3G:1;
  274. u8 reserved_0:4;
  275. u8 reserved_1[6];
  276. u8 port_count;
  277. u64 port_addr[8];
  278. } __attribute__ ((packed)) device_interface;
  279. /*
  280. * List of components residing in flash. All str are null terminated
  281. */
  282. u32 image_check_word;
  283. u32 image_component_count;
  284. struct {
  285. char name[8];
  286. char version[32];
  287. char build_date[16];
  288. char built_time[16];
  289. } __attribute__ ((packed)) image_component[8];
  290. /*
  291. * List of flash components that have been flashed on the card, but
  292. * are not in use, pending reset of the adapter. This list will be
  293. * empty if a flash operation has not occurred. All stings are null
  294. * terminated
  295. */
  296. u32 pending_image_component_count;
  297. struct {
  298. char name[8];
  299. char version[32];
  300. char build_date[16];
  301. char build_time[16];
  302. } __attribute__ ((packed)) pending_image_component[8];
  303. u8 max_arms;
  304. u8 max_spans;
  305. u8 max_arrays;
  306. u8 max_lds;
  307. char product_name[80];
  308. char serial_no[32];
  309. /*
  310. * Other physical/controller/operation information. Indicates the
  311. * presence of the hardware
  312. */
  313. struct {
  314. u32 bbu:1;
  315. u32 alarm:1;
  316. u32 nvram:1;
  317. u32 uart:1;
  318. u32 reserved:28;
  319. } __attribute__ ((packed)) hw_present;
  320. u32 current_fw_time;
  321. /*
  322. * Maximum data transfer sizes
  323. */
  324. u16 max_concurrent_cmds;
  325. u16 max_sge_count;
  326. u32 max_request_size;
  327. /*
  328. * Logical and physical device counts
  329. */
  330. u16 ld_present_count;
  331. u16 ld_degraded_count;
  332. u16 ld_offline_count;
  333. u16 pd_present_count;
  334. u16 pd_disk_present_count;
  335. u16 pd_disk_pred_failure_count;
  336. u16 pd_disk_failed_count;
  337. /*
  338. * Memory size information
  339. */
  340. u16 nvram_size;
  341. u16 memory_size;
  342. u16 flash_size;
  343. /*
  344. * Error counters
  345. */
  346. u16 mem_correctable_error_count;
  347. u16 mem_uncorrectable_error_count;
  348. /*
  349. * Cluster information
  350. */
  351. u8 cluster_permitted;
  352. u8 cluster_active;
  353. /*
  354. * Additional max data transfer sizes
  355. */
  356. u16 max_strips_per_io;
  357. /*
  358. * Controller capabilities structures
  359. */
  360. struct {
  361. u32 raid_level_0:1;
  362. u32 raid_level_1:1;
  363. u32 raid_level_5:1;
  364. u32 raid_level_1E:1;
  365. u32 raid_level_6:1;
  366. u32 reserved:27;
  367. } __attribute__ ((packed)) raid_levels;
  368. struct {
  369. u32 rbld_rate:1;
  370. u32 cc_rate:1;
  371. u32 bgi_rate:1;
  372. u32 recon_rate:1;
  373. u32 patrol_rate:1;
  374. u32 alarm_control:1;
  375. u32 cluster_supported:1;
  376. u32 bbu:1;
  377. u32 spanning_allowed:1;
  378. u32 dedicated_hotspares:1;
  379. u32 revertible_hotspares:1;
  380. u32 foreign_config_import:1;
  381. u32 self_diagnostic:1;
  382. u32 mixed_redundancy_arr:1;
  383. u32 global_hot_spares:1;
  384. u32 reserved:17;
  385. } __attribute__ ((packed)) adapter_operations;
  386. struct {
  387. u32 read_policy:1;
  388. u32 write_policy:1;
  389. u32 io_policy:1;
  390. u32 access_policy:1;
  391. u32 disk_cache_policy:1;
  392. u32 reserved:27;
  393. } __attribute__ ((packed)) ld_operations;
  394. struct {
  395. u8 min;
  396. u8 max;
  397. u8 reserved[2];
  398. } __attribute__ ((packed)) stripe_sz_ops;
  399. struct {
  400. u32 force_online:1;
  401. u32 force_offline:1;
  402. u32 force_rebuild:1;
  403. u32 reserved:29;
  404. } __attribute__ ((packed)) pd_operations;
  405. struct {
  406. u32 ctrl_supports_sas:1;
  407. u32 ctrl_supports_sata:1;
  408. u32 allow_mix_in_encl:1;
  409. u32 allow_mix_in_ld:1;
  410. u32 allow_sata_in_cluster:1;
  411. u32 reserved:27;
  412. } __attribute__ ((packed)) pd_mix_support;
  413. /*
  414. * Define ECC single-bit-error bucket information
  415. */
  416. u8 ecc_bucket_count;
  417. u8 reserved_2[11];
  418. /*
  419. * Include the controller properties (changeable items)
  420. */
  421. struct megasas_ctrl_prop properties;
  422. /*
  423. * Define FW pkg version (set in envt v'bles on OEM basis)
  424. */
  425. char package_version[0x60];
  426. u8 pad[0x800 - 0x6a0];
  427. } __attribute__ ((packed));
  428. /*
  429. * ===============================
  430. * MegaRAID SAS driver definitions
  431. * ===============================
  432. */
  433. #define MEGASAS_MAX_PD_CHANNELS 2
  434. #define MEGASAS_MAX_LD_CHANNELS 2
  435. #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
  436. MEGASAS_MAX_LD_CHANNELS)
  437. #define MEGASAS_MAX_DEV_PER_CHANNEL 128
  438. #define MEGASAS_DEFAULT_INIT_ID -1
  439. #define MEGASAS_MAX_LUN 8
  440. #define MEGASAS_MAX_LD 64
  441. /*
  442. * When SCSI mid-layer calls driver's reset routine, driver waits for
  443. * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
  444. * that the driver cannot _actually_ abort or reset pending commands. While
  445. * it is waiting for the commands to complete, it prints a diagnostic message
  446. * every MEGASAS_RESET_NOTICE_INTERVAL seconds
  447. */
  448. #define MEGASAS_RESET_WAIT_TIME 180
  449. #define MEGASAS_RESET_NOTICE_INTERVAL 5
  450. #define MEGASAS_IOCTL_CMD 0
  451. /*
  452. * FW reports the maximum of number of commands that it can accept (maximum
  453. * commands that can be outstanding) at any time. The driver must report a
  454. * lower number to the mid layer because it can issue a few internal commands
  455. * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
  456. * is shown below
  457. */
  458. #define MEGASAS_INT_CMDS 32
  459. /*
  460. * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
  461. * SGLs based on the size of dma_addr_t
  462. */
  463. #define IS_DMA64 (sizeof(dma_addr_t) == 8)
  464. #define MFI_OB_INTR_STATUS_MASK 0x00000002
  465. #define MFI_POLL_TIMEOUT_SECS 10
  466. struct megasas_register_set {
  467. u32 reserved_0[4]; /*0000h */
  468. u32 inbound_msg_0; /*0010h */
  469. u32 inbound_msg_1; /*0014h */
  470. u32 outbound_msg_0; /*0018h */
  471. u32 outbound_msg_1; /*001Ch */
  472. u32 inbound_doorbell; /*0020h */
  473. u32 inbound_intr_status; /*0024h */
  474. u32 inbound_intr_mask; /*0028h */
  475. u32 outbound_doorbell; /*002Ch */
  476. u32 outbound_intr_status; /*0030h */
  477. u32 outbound_intr_mask; /*0034h */
  478. u32 reserved_1[2]; /*0038h */
  479. u32 inbound_queue_port; /*0040h */
  480. u32 outbound_queue_port; /*0044h */
  481. u32 reserved_2; /*004Ch */
  482. u32 index_registers[1004]; /*0050h */
  483. } __attribute__ ((packed));
  484. struct megasas_sge32 {
  485. u32 phys_addr;
  486. u32 length;
  487. } __attribute__ ((packed));
  488. struct megasas_sge64 {
  489. u64 phys_addr;
  490. u32 length;
  491. } __attribute__ ((packed));
  492. union megasas_sgl {
  493. struct megasas_sge32 sge32[1];
  494. struct megasas_sge64 sge64[1];
  495. } __attribute__ ((packed));
  496. struct megasas_header {
  497. u8 cmd; /*00h */
  498. u8 sense_len; /*01h */
  499. u8 cmd_status; /*02h */
  500. u8 scsi_status; /*03h */
  501. u8 target_id; /*04h */
  502. u8 lun; /*05h */
  503. u8 cdb_len; /*06h */
  504. u8 sge_count; /*07h */
  505. u32 context; /*08h */
  506. u32 pad_0; /*0Ch */
  507. u16 flags; /*10h */
  508. u16 timeout; /*12h */
  509. u32 data_xferlen; /*14h */
  510. } __attribute__ ((packed));
  511. union megasas_sgl_frame {
  512. struct megasas_sge32 sge32[8];
  513. struct megasas_sge64 sge64[5];
  514. } __attribute__ ((packed));
  515. struct megasas_init_frame {
  516. u8 cmd; /*00h */
  517. u8 reserved_0; /*01h */
  518. u8 cmd_status; /*02h */
  519. u8 reserved_1; /*03h */
  520. u32 reserved_2; /*04h */
  521. u32 context; /*08h */
  522. u32 pad_0; /*0Ch */
  523. u16 flags; /*10h */
  524. u16 reserved_3; /*12h */
  525. u32 data_xfer_len; /*14h */
  526. u32 queue_info_new_phys_addr_lo; /*18h */
  527. u32 queue_info_new_phys_addr_hi; /*1Ch */
  528. u32 queue_info_old_phys_addr_lo; /*20h */
  529. u32 queue_info_old_phys_addr_hi; /*24h */
  530. u32 reserved_4[6]; /*28h */
  531. } __attribute__ ((packed));
  532. struct megasas_init_queue_info {
  533. u32 init_flags; /*00h */
  534. u32 reply_queue_entries; /*04h */
  535. u32 reply_queue_start_phys_addr_lo; /*08h */
  536. u32 reply_queue_start_phys_addr_hi; /*0Ch */
  537. u32 producer_index_phys_addr_lo; /*10h */
  538. u32 producer_index_phys_addr_hi; /*14h */
  539. u32 consumer_index_phys_addr_lo; /*18h */
  540. u32 consumer_index_phys_addr_hi; /*1Ch */
  541. } __attribute__ ((packed));
  542. struct megasas_io_frame {
  543. u8 cmd; /*00h */
  544. u8 sense_len; /*01h */
  545. u8 cmd_status; /*02h */
  546. u8 scsi_status; /*03h */
  547. u8 target_id; /*04h */
  548. u8 access_byte; /*05h */
  549. u8 reserved_0; /*06h */
  550. u8 sge_count; /*07h */
  551. u32 context; /*08h */
  552. u32 pad_0; /*0Ch */
  553. u16 flags; /*10h */
  554. u16 timeout; /*12h */
  555. u32 lba_count; /*14h */
  556. u32 sense_buf_phys_addr_lo; /*18h */
  557. u32 sense_buf_phys_addr_hi; /*1Ch */
  558. u32 start_lba_lo; /*20h */
  559. u32 start_lba_hi; /*24h */
  560. union megasas_sgl sgl; /*28h */
  561. } __attribute__ ((packed));
  562. struct megasas_pthru_frame {
  563. u8 cmd; /*00h */
  564. u8 sense_len; /*01h */
  565. u8 cmd_status; /*02h */
  566. u8 scsi_status; /*03h */
  567. u8 target_id; /*04h */
  568. u8 lun; /*05h */
  569. u8 cdb_len; /*06h */
  570. u8 sge_count; /*07h */
  571. u32 context; /*08h */
  572. u32 pad_0; /*0Ch */
  573. u16 flags; /*10h */
  574. u16 timeout; /*12h */
  575. u32 data_xfer_len; /*14h */
  576. u32 sense_buf_phys_addr_lo; /*18h */
  577. u32 sense_buf_phys_addr_hi; /*1Ch */
  578. u8 cdb[16]; /*20h */
  579. union megasas_sgl sgl; /*30h */
  580. } __attribute__ ((packed));
  581. struct megasas_dcmd_frame {
  582. u8 cmd; /*00h */
  583. u8 reserved_0; /*01h */
  584. u8 cmd_status; /*02h */
  585. u8 reserved_1[4]; /*03h */
  586. u8 sge_count; /*07h */
  587. u32 context; /*08h */
  588. u32 pad_0; /*0Ch */
  589. u16 flags; /*10h */
  590. u16 timeout; /*12h */
  591. u32 data_xfer_len; /*14h */
  592. u32 opcode; /*18h */
  593. union { /*1Ch */
  594. u8 b[12];
  595. u16 s[6];
  596. u32 w[3];
  597. } mbox;
  598. union megasas_sgl sgl; /*28h */
  599. } __attribute__ ((packed));
  600. struct megasas_abort_frame {
  601. u8 cmd; /*00h */
  602. u8 reserved_0; /*01h */
  603. u8 cmd_status; /*02h */
  604. u8 reserved_1; /*03h */
  605. u32 reserved_2; /*04h */
  606. u32 context; /*08h */
  607. u32 pad_0; /*0Ch */
  608. u16 flags; /*10h */
  609. u16 reserved_3; /*12h */
  610. u32 reserved_4; /*14h */
  611. u32 abort_context; /*18h */
  612. u32 pad_1; /*1Ch */
  613. u32 abort_mfi_phys_addr_lo; /*20h */
  614. u32 abort_mfi_phys_addr_hi; /*24h */
  615. u32 reserved_5[6]; /*28h */
  616. } __attribute__ ((packed));
  617. struct megasas_smp_frame {
  618. u8 cmd; /*00h */
  619. u8 reserved_1; /*01h */
  620. u8 cmd_status; /*02h */
  621. u8 connection_status; /*03h */
  622. u8 reserved_2[3]; /*04h */
  623. u8 sge_count; /*07h */
  624. u32 context; /*08h */
  625. u32 pad_0; /*0Ch */
  626. u16 flags; /*10h */
  627. u16 timeout; /*12h */
  628. u32 data_xfer_len; /*14h */
  629. u64 sas_addr; /*18h */
  630. union {
  631. struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
  632. struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
  633. } sgl;
  634. } __attribute__ ((packed));
  635. struct megasas_stp_frame {
  636. u8 cmd; /*00h */
  637. u8 reserved_1; /*01h */
  638. u8 cmd_status; /*02h */
  639. u8 reserved_2; /*03h */
  640. u8 target_id; /*04h */
  641. u8 reserved_3[2]; /*05h */
  642. u8 sge_count; /*07h */
  643. u32 context; /*08h */
  644. u32 pad_0; /*0Ch */
  645. u16 flags; /*10h */
  646. u16 timeout; /*12h */
  647. u32 data_xfer_len; /*14h */
  648. u16 fis[10]; /*18h */
  649. u32 stp_flags;
  650. union {
  651. struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
  652. struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
  653. } sgl;
  654. } __attribute__ ((packed));
  655. union megasas_frame {
  656. struct megasas_header hdr;
  657. struct megasas_init_frame init;
  658. struct megasas_io_frame io;
  659. struct megasas_pthru_frame pthru;
  660. struct megasas_dcmd_frame dcmd;
  661. struct megasas_abort_frame abort;
  662. struct megasas_smp_frame smp;
  663. struct megasas_stp_frame stp;
  664. u8 raw_bytes[64];
  665. };
  666. struct megasas_cmd;
  667. union megasas_evt_class_locale {
  668. struct {
  669. u16 locale;
  670. u8 reserved;
  671. s8 class;
  672. } __attribute__ ((packed)) members;
  673. u32 word;
  674. } __attribute__ ((packed));
  675. struct megasas_evt_log_info {
  676. u32 newest_seq_num;
  677. u32 oldest_seq_num;
  678. u32 clear_seq_num;
  679. u32 shutdown_seq_num;
  680. u32 boot_seq_num;
  681. } __attribute__ ((packed));
  682. struct megasas_progress {
  683. u16 progress;
  684. u16 elapsed_seconds;
  685. } __attribute__ ((packed));
  686. struct megasas_evtarg_ld {
  687. u16 target_id;
  688. u8 ld_index;
  689. u8 reserved;
  690. } __attribute__ ((packed));
  691. struct megasas_evtarg_pd {
  692. u16 device_id;
  693. u8 encl_index;
  694. u8 slot_number;
  695. } __attribute__ ((packed));
  696. struct megasas_evt_detail {
  697. u32 seq_num;
  698. u32 time_stamp;
  699. u32 code;
  700. union megasas_evt_class_locale cl;
  701. u8 arg_type;
  702. u8 reserved1[15];
  703. union {
  704. struct {
  705. struct megasas_evtarg_pd pd;
  706. u8 cdb_length;
  707. u8 sense_length;
  708. u8 reserved[2];
  709. u8 cdb[16];
  710. u8 sense[64];
  711. } __attribute__ ((packed)) cdbSense;
  712. struct megasas_evtarg_ld ld;
  713. struct {
  714. struct megasas_evtarg_ld ld;
  715. u64 count;
  716. } __attribute__ ((packed)) ld_count;
  717. struct {
  718. u64 lba;
  719. struct megasas_evtarg_ld ld;
  720. } __attribute__ ((packed)) ld_lba;
  721. struct {
  722. struct megasas_evtarg_ld ld;
  723. u32 prevOwner;
  724. u32 newOwner;
  725. } __attribute__ ((packed)) ld_owner;
  726. struct {
  727. u64 ld_lba;
  728. u64 pd_lba;
  729. struct megasas_evtarg_ld ld;
  730. struct megasas_evtarg_pd pd;
  731. } __attribute__ ((packed)) ld_lba_pd_lba;
  732. struct {
  733. struct megasas_evtarg_ld ld;
  734. struct megasas_progress prog;
  735. } __attribute__ ((packed)) ld_prog;
  736. struct {
  737. struct megasas_evtarg_ld ld;
  738. u32 prev_state;
  739. u32 new_state;
  740. } __attribute__ ((packed)) ld_state;
  741. struct {
  742. u64 strip;
  743. struct megasas_evtarg_ld ld;
  744. } __attribute__ ((packed)) ld_strip;
  745. struct megasas_evtarg_pd pd;
  746. struct {
  747. struct megasas_evtarg_pd pd;
  748. u32 err;
  749. } __attribute__ ((packed)) pd_err;
  750. struct {
  751. u64 lba;
  752. struct megasas_evtarg_pd pd;
  753. } __attribute__ ((packed)) pd_lba;
  754. struct {
  755. u64 lba;
  756. struct megasas_evtarg_pd pd;
  757. struct megasas_evtarg_ld ld;
  758. } __attribute__ ((packed)) pd_lba_ld;
  759. struct {
  760. struct megasas_evtarg_pd pd;
  761. struct megasas_progress prog;
  762. } __attribute__ ((packed)) pd_prog;
  763. struct {
  764. struct megasas_evtarg_pd pd;
  765. u32 prevState;
  766. u32 newState;
  767. } __attribute__ ((packed)) pd_state;
  768. struct {
  769. u16 vendorId;
  770. u16 deviceId;
  771. u16 subVendorId;
  772. u16 subDeviceId;
  773. } __attribute__ ((packed)) pci;
  774. u32 rate;
  775. char str[96];
  776. struct {
  777. u32 rtc;
  778. u32 elapsedSeconds;
  779. } __attribute__ ((packed)) time;
  780. struct {
  781. u32 ecar;
  782. u32 elog;
  783. char str[64];
  784. } __attribute__ ((packed)) ecc;
  785. u8 b[96];
  786. u16 s[48];
  787. u32 w[24];
  788. u64 d[12];
  789. } args;
  790. char description[128];
  791. } __attribute__ ((packed));
  792. struct megasas_instance {
  793. u32 *producer;
  794. dma_addr_t producer_h;
  795. u32 *consumer;
  796. dma_addr_t consumer_h;
  797. u32 *reply_queue;
  798. dma_addr_t reply_queue_h;
  799. unsigned long base_addr;
  800. struct megasas_register_set __iomem *reg_set;
  801. s8 init_id;
  802. u8 reserved[3];
  803. u16 max_num_sge;
  804. u16 max_fw_cmds;
  805. u32 max_sectors_per_req;
  806. struct megasas_cmd **cmd_list;
  807. struct list_head cmd_pool;
  808. spinlock_t cmd_pool_lock;
  809. struct dma_pool *frame_dma_pool;
  810. struct dma_pool *sense_dma_pool;
  811. struct megasas_evt_detail *evt_detail;
  812. dma_addr_t evt_detail_h;
  813. struct megasas_cmd *aen_cmd;
  814. struct semaphore aen_mutex;
  815. struct semaphore ioctl_sem;
  816. struct Scsi_Host *host;
  817. wait_queue_head_t int_cmd_wait_q;
  818. wait_queue_head_t abort_cmd_wait_q;
  819. struct pci_dev *pdev;
  820. u32 unique_id;
  821. u32 fw_outstanding;
  822. u32 hw_crit_error;
  823. spinlock_t instance_lock;
  824. };
  825. #define MEGASAS_IS_LOGICAL(scp) \
  826. (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
  827. #define MEGASAS_DEV_INDEX(inst, scp) \
  828. ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
  829. scp->device->id
  830. struct megasas_cmd {
  831. union megasas_frame *frame;
  832. dma_addr_t frame_phys_addr;
  833. u8 *sense;
  834. dma_addr_t sense_phys_addr;
  835. u32 index;
  836. u8 sync_cmd;
  837. u8 cmd_status;
  838. u16 abort_aen;
  839. struct list_head list;
  840. struct scsi_cmnd *scmd;
  841. struct megasas_instance *instance;
  842. u32 frame_count;
  843. };
  844. #define MAX_MGMT_ADAPTERS 1024
  845. #define MAX_IOCTL_SGE 16
  846. struct megasas_iocpacket {
  847. u16 host_no;
  848. u16 __pad1;
  849. u32 sgl_off;
  850. u32 sge_count;
  851. u32 sense_off;
  852. u32 sense_len;
  853. union {
  854. u8 raw[128];
  855. struct megasas_header hdr;
  856. } frame;
  857. struct iovec sgl[MAX_IOCTL_SGE];
  858. } __attribute__ ((packed));
  859. struct megasas_aen {
  860. u16 host_no;
  861. u16 __pad1;
  862. u32 seq_num;
  863. u32 class_locale_word;
  864. } __attribute__ ((packed));
  865. #ifdef CONFIG_COMPAT
  866. struct compat_megasas_iocpacket {
  867. u16 host_no;
  868. u16 __pad1;
  869. u32 sgl_off;
  870. u32 sge_count;
  871. u32 sense_off;
  872. u32 sense_len;
  873. union {
  874. u8 raw[128];
  875. struct megasas_header hdr;
  876. } frame;
  877. struct compat_iovec sgl[MAX_IOCTL_SGE];
  878. } __attribute__ ((packed));
  879. #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct compat_megasas_iocpacket)
  880. #else
  881. #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
  882. #endif
  883. #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
  884. struct megasas_mgmt_info {
  885. u16 count;
  886. struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
  887. int max_index;
  888. };
  889. #endif /*LSI_MEGARAID_SAS_H */