mthca_main.c 32 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224
  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_PCI_MSI
  52. static int msi_x = 0;
  53. module_param(msi_x, int, 0444);
  54. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  55. static int msi = 0;
  56. module_param(msi, int, 0444);
  57. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  58. #else /* CONFIG_PCI_MSI */
  59. #define msi_x (0)
  60. #define msi (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static const char mthca_version[] __devinitdata =
  63. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  64. DRV_VERSION " (" DRV_RELDATE ")\n";
  65. static struct mthca_profile default_profile = {
  66. .num_qp = 1 << 16,
  67. .rdb_per_qp = 4,
  68. .num_cq = 1 << 16,
  69. .num_mcg = 1 << 13,
  70. .num_mpt = 1 << 17,
  71. .num_mtt = 1 << 20,
  72. .num_udav = 1 << 15, /* Tavor only */
  73. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  74. .uarc_size = 1 << 18, /* Arbel only */
  75. };
  76. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  77. {
  78. int cap;
  79. u16 val;
  80. /* First try to max out Read Byte Count */
  81. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  82. if (cap) {
  83. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  84. mthca_err(mdev, "Couldn't read PCI-X command register, "
  85. "aborting.\n");
  86. return -ENODEV;
  87. }
  88. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  89. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  90. mthca_err(mdev, "Couldn't write PCI-X command register, "
  91. "aborting.\n");
  92. return -ENODEV;
  93. }
  94. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  95. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  96. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  97. if (cap) {
  98. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  99. mthca_err(mdev, "Couldn't read PCI Express device control "
  100. "register, aborting.\n");
  101. return -ENODEV;
  102. }
  103. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  104. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  105. mthca_err(mdev, "Couldn't write PCI Express device control "
  106. "register, aborting.\n");
  107. return -ENODEV;
  108. }
  109. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  110. mthca_info(mdev, "No PCI Express capability, "
  111. "not setting Max Read Request Size.\n");
  112. return 0;
  113. }
  114. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  115. {
  116. int err;
  117. u8 status;
  118. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  119. if (err) {
  120. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  121. return err;
  122. }
  123. if (status) {
  124. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  125. "aborting.\n", status);
  126. return -EINVAL;
  127. }
  128. if (dev_lim->min_page_sz > PAGE_SIZE) {
  129. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  130. "kernel PAGE_SIZE of %ld, aborting.\n",
  131. dev_lim->min_page_sz, PAGE_SIZE);
  132. return -ENODEV;
  133. }
  134. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  135. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  136. "aborting.\n",
  137. dev_lim->num_ports, MTHCA_MAX_PORTS);
  138. return -ENODEV;
  139. }
  140. mdev->limits.num_ports = dev_lim->num_ports;
  141. mdev->limits.vl_cap = dev_lim->max_vl;
  142. mdev->limits.mtu_cap = dev_lim->max_mtu;
  143. mdev->limits.gid_table_len = dev_lim->max_gids;
  144. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  145. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  146. mdev->limits.max_sg = dev_lim->max_sg;
  147. mdev->limits.max_wqes = dev_lim->max_qp_sz;
  148. mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
  149. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  150. mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
  151. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  152. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  153. mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
  154. /*
  155. * Subtract 1 from the limit because we need to allocate a
  156. * spare CQE so the HCA HW can tell the difference between an
  157. * empty CQ and a full CQ.
  158. */
  159. mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
  160. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  161. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  162. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  163. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  164. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  165. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  166. mdev->limits.port_width_cap = dev_lim->max_port_width;
  167. mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
  168. mdev->limits.flags = dev_lim->flags;
  169. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  170. May be doable since hardware supports it for SRQ.
  171. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  172. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  173. supported by driver. */
  174. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  175. IB_DEVICE_PORT_ACTIVE_EVENT |
  176. IB_DEVICE_SYS_IMAGE_GUID |
  177. IB_DEVICE_RC_RNR_NAK_GEN;
  178. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  179. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  180. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  181. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  182. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  183. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  184. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  185. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  186. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  187. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  188. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  189. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  190. return 0;
  191. }
  192. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  193. {
  194. u8 status;
  195. int err;
  196. struct mthca_dev_lim dev_lim;
  197. struct mthca_profile profile;
  198. struct mthca_init_hca_param init_hca;
  199. err = mthca_SYS_EN(mdev, &status);
  200. if (err) {
  201. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  202. return err;
  203. }
  204. if (status) {
  205. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  206. "aborting.\n", status);
  207. return -EINVAL;
  208. }
  209. err = mthca_QUERY_FW(mdev, &status);
  210. if (err) {
  211. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  212. goto err_disable;
  213. }
  214. if (status) {
  215. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  216. "aborting.\n", status);
  217. err = -EINVAL;
  218. goto err_disable;
  219. }
  220. err = mthca_QUERY_DDR(mdev, &status);
  221. if (err) {
  222. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  223. goto err_disable;
  224. }
  225. if (status) {
  226. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  227. "aborting.\n", status);
  228. err = -EINVAL;
  229. goto err_disable;
  230. }
  231. err = mthca_dev_lim(mdev, &dev_lim);
  232. if (err) {
  233. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  234. goto err_disable;
  235. }
  236. profile = default_profile;
  237. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  238. profile.uarc_size = 0;
  239. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  240. profile.num_srq = dev_lim.max_srqs;
  241. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  242. if (err < 0)
  243. goto err_disable;
  244. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  245. if (err) {
  246. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  247. goto err_disable;
  248. }
  249. if (status) {
  250. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  251. "aborting.\n", status);
  252. err = -EINVAL;
  253. goto err_disable;
  254. }
  255. return 0;
  256. err_disable:
  257. mthca_SYS_DIS(mdev, &status);
  258. return err;
  259. }
  260. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  261. {
  262. u8 status;
  263. int err;
  264. /* FIXME: use HCA-attached memory for FW if present */
  265. mdev->fw.arbel.fw_icm =
  266. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  267. GFP_HIGHUSER | __GFP_NOWARN);
  268. if (!mdev->fw.arbel.fw_icm) {
  269. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  270. return -ENOMEM;
  271. }
  272. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  273. if (err) {
  274. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  275. goto err_free;
  276. }
  277. if (status) {
  278. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  279. err = -EINVAL;
  280. goto err_free;
  281. }
  282. err = mthca_RUN_FW(mdev, &status);
  283. if (err) {
  284. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  285. goto err_unmap_fa;
  286. }
  287. if (status) {
  288. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  289. err = -EINVAL;
  290. goto err_unmap_fa;
  291. }
  292. return 0;
  293. err_unmap_fa:
  294. mthca_UNMAP_FA(mdev, &status);
  295. err_free:
  296. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  297. return err;
  298. }
  299. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  300. struct mthca_dev_lim *dev_lim,
  301. struct mthca_init_hca_param *init_hca,
  302. u64 icm_size)
  303. {
  304. u64 aux_pages;
  305. u8 status;
  306. int err;
  307. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  308. if (err) {
  309. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  310. return err;
  311. }
  312. if (status) {
  313. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  314. "aborting.\n", status);
  315. return -EINVAL;
  316. }
  317. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  318. (unsigned long long) icm_size >> 10,
  319. (unsigned long long) aux_pages << 2);
  320. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  321. GFP_HIGHUSER | __GFP_NOWARN);
  322. if (!mdev->fw.arbel.aux_icm) {
  323. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  324. return -ENOMEM;
  325. }
  326. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  327. if (err) {
  328. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  329. goto err_free_aux;
  330. }
  331. if (status) {
  332. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  333. err = -EINVAL;
  334. goto err_free_aux;
  335. }
  336. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  337. if (err) {
  338. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  339. goto err_unmap_aux;
  340. }
  341. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  342. MTHCA_MTT_SEG_SIZE,
  343. mdev->limits.num_mtt_segs,
  344. mdev->limits.reserved_mtts, 1);
  345. if (!mdev->mr_table.mtt_table) {
  346. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  347. err = -ENOMEM;
  348. goto err_unmap_eq;
  349. }
  350. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  351. dev_lim->mpt_entry_sz,
  352. mdev->limits.num_mpts,
  353. mdev->limits.reserved_mrws, 1);
  354. if (!mdev->mr_table.mpt_table) {
  355. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  356. err = -ENOMEM;
  357. goto err_unmap_mtt;
  358. }
  359. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  360. dev_lim->qpc_entry_sz,
  361. mdev->limits.num_qps,
  362. mdev->limits.reserved_qps, 0);
  363. if (!mdev->qp_table.qp_table) {
  364. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  365. err = -ENOMEM;
  366. goto err_unmap_mpt;
  367. }
  368. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  369. dev_lim->eqpc_entry_sz,
  370. mdev->limits.num_qps,
  371. mdev->limits.reserved_qps, 0);
  372. if (!mdev->qp_table.eqp_table) {
  373. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  374. err = -ENOMEM;
  375. goto err_unmap_qp;
  376. }
  377. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  378. MTHCA_RDB_ENTRY_SIZE,
  379. mdev->limits.num_qps <<
  380. mdev->qp_table.rdb_shift,
  381. 0, 0);
  382. if (!mdev->qp_table.rdb_table) {
  383. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  384. err = -ENOMEM;
  385. goto err_unmap_eqp;
  386. }
  387. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  388. dev_lim->cqc_entry_sz,
  389. mdev->limits.num_cqs,
  390. mdev->limits.reserved_cqs, 0);
  391. if (!mdev->cq_table.table) {
  392. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  393. err = -ENOMEM;
  394. goto err_unmap_rdb;
  395. }
  396. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  397. mdev->srq_table.table =
  398. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  399. dev_lim->srq_entry_sz,
  400. mdev->limits.num_srqs,
  401. mdev->limits.reserved_srqs, 0);
  402. if (!mdev->srq_table.table) {
  403. mthca_err(mdev, "Failed to map SRQ context memory, "
  404. "aborting.\n");
  405. err = -ENOMEM;
  406. goto err_unmap_cq;
  407. }
  408. }
  409. /*
  410. * It's not strictly required, but for simplicity just map the
  411. * whole multicast group table now. The table isn't very big
  412. * and it's a lot easier than trying to track ref counts.
  413. */
  414. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  415. MTHCA_MGM_ENTRY_SIZE,
  416. mdev->limits.num_mgms +
  417. mdev->limits.num_amgms,
  418. mdev->limits.num_mgms +
  419. mdev->limits.num_amgms,
  420. 0);
  421. if (!mdev->mcg_table.table) {
  422. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  423. err = -ENOMEM;
  424. goto err_unmap_srq;
  425. }
  426. return 0;
  427. err_unmap_srq:
  428. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  429. mthca_free_icm_table(mdev, mdev->srq_table.table);
  430. err_unmap_cq:
  431. mthca_free_icm_table(mdev, mdev->cq_table.table);
  432. err_unmap_rdb:
  433. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  434. err_unmap_eqp:
  435. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  436. err_unmap_qp:
  437. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  438. err_unmap_mpt:
  439. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  440. err_unmap_mtt:
  441. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  442. err_unmap_eq:
  443. mthca_unmap_eq_icm(mdev);
  444. err_unmap_aux:
  445. mthca_UNMAP_ICM_AUX(mdev, &status);
  446. err_free_aux:
  447. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  448. return err;
  449. }
  450. static void mthca_free_icms(struct mthca_dev *mdev)
  451. {
  452. u8 status;
  453. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  454. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  455. mthca_free_icm_table(mdev, mdev->srq_table.table);
  456. mthca_free_icm_table(mdev, mdev->cq_table.table);
  457. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  458. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  459. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  460. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  461. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  462. mthca_unmap_eq_icm(mdev);
  463. mthca_UNMAP_ICM_AUX(mdev, &status);
  464. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  465. }
  466. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  467. {
  468. struct mthca_dev_lim dev_lim;
  469. struct mthca_profile profile;
  470. struct mthca_init_hca_param init_hca;
  471. u64 icm_size;
  472. u8 status;
  473. int err;
  474. err = mthca_QUERY_FW(mdev, &status);
  475. if (err) {
  476. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  477. return err;
  478. }
  479. if (status) {
  480. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  481. "aborting.\n", status);
  482. return -EINVAL;
  483. }
  484. err = mthca_ENABLE_LAM(mdev, &status);
  485. if (err) {
  486. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  487. return err;
  488. }
  489. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  490. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  491. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  492. } else if (status) {
  493. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  494. "aborting.\n", status);
  495. return -EINVAL;
  496. }
  497. err = mthca_load_fw(mdev);
  498. if (err) {
  499. mthca_err(mdev, "Failed to start FW, aborting.\n");
  500. goto err_disable;
  501. }
  502. err = mthca_dev_lim(mdev, &dev_lim);
  503. if (err) {
  504. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  505. goto err_stop_fw;
  506. }
  507. profile = default_profile;
  508. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  509. profile.num_udav = 0;
  510. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  511. profile.num_srq = dev_lim.max_srqs;
  512. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  513. if ((int) icm_size < 0) {
  514. err = icm_size;
  515. goto err_stop_fw;
  516. }
  517. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  518. if (err)
  519. goto err_stop_fw;
  520. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  521. if (err) {
  522. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  523. goto err_free_icm;
  524. }
  525. if (status) {
  526. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  527. "aborting.\n", status);
  528. err = -EINVAL;
  529. goto err_free_icm;
  530. }
  531. return 0;
  532. err_free_icm:
  533. mthca_free_icms(mdev);
  534. err_stop_fw:
  535. mthca_UNMAP_FA(mdev, &status);
  536. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  537. err_disable:
  538. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  539. mthca_DISABLE_LAM(mdev, &status);
  540. return err;
  541. }
  542. static void mthca_close_hca(struct mthca_dev *mdev)
  543. {
  544. u8 status;
  545. mthca_CLOSE_HCA(mdev, 0, &status);
  546. if (mthca_is_memfree(mdev)) {
  547. mthca_free_icms(mdev);
  548. mthca_UNMAP_FA(mdev, &status);
  549. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  550. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  551. mthca_DISABLE_LAM(mdev, &status);
  552. } else
  553. mthca_SYS_DIS(mdev, &status);
  554. }
  555. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  556. {
  557. u8 status;
  558. int err;
  559. struct mthca_adapter adapter;
  560. if (mthca_is_memfree(mdev))
  561. err = mthca_init_arbel(mdev);
  562. else
  563. err = mthca_init_tavor(mdev);
  564. if (err)
  565. return err;
  566. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  567. if (err) {
  568. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  569. goto err_close;
  570. }
  571. if (status) {
  572. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  573. "aborting.\n", status);
  574. err = -EINVAL;
  575. goto err_close;
  576. }
  577. mdev->eq_table.inta_pin = adapter.inta_pin;
  578. mdev->rev_id = adapter.revision_id;
  579. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  580. return 0;
  581. err_close:
  582. mthca_close_hca(mdev);
  583. return err;
  584. }
  585. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  586. {
  587. int err;
  588. u8 status;
  589. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  590. err = mthca_init_uar_table(dev);
  591. if (err) {
  592. mthca_err(dev, "Failed to initialize "
  593. "user access region table, aborting.\n");
  594. return err;
  595. }
  596. err = mthca_uar_alloc(dev, &dev->driver_uar);
  597. if (err) {
  598. mthca_err(dev, "Failed to allocate driver access region, "
  599. "aborting.\n");
  600. goto err_uar_table_free;
  601. }
  602. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  603. if (!dev->kar) {
  604. mthca_err(dev, "Couldn't map kernel access region, "
  605. "aborting.\n");
  606. err = -ENOMEM;
  607. goto err_uar_free;
  608. }
  609. err = mthca_init_pd_table(dev);
  610. if (err) {
  611. mthca_err(dev, "Failed to initialize "
  612. "protection domain table, aborting.\n");
  613. goto err_kar_unmap;
  614. }
  615. err = mthca_init_mr_table(dev);
  616. if (err) {
  617. mthca_err(dev, "Failed to initialize "
  618. "memory region table, aborting.\n");
  619. goto err_pd_table_free;
  620. }
  621. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  622. if (err) {
  623. mthca_err(dev, "Failed to create driver PD, "
  624. "aborting.\n");
  625. goto err_mr_table_free;
  626. }
  627. err = mthca_init_eq_table(dev);
  628. if (err) {
  629. mthca_err(dev, "Failed to initialize "
  630. "event queue table, aborting.\n");
  631. goto err_pd_free;
  632. }
  633. err = mthca_cmd_use_events(dev);
  634. if (err) {
  635. mthca_err(dev, "Failed to switch to event-driven "
  636. "firmware commands, aborting.\n");
  637. goto err_eq_table_free;
  638. }
  639. err = mthca_NOP(dev, &status);
  640. if (err || status) {
  641. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  642. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  643. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  644. dev->pdev->irq);
  645. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  646. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  647. else
  648. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  649. goto err_cmd_poll;
  650. }
  651. mthca_dbg(dev, "NOP command IRQ test passed\n");
  652. err = mthca_init_cq_table(dev);
  653. if (err) {
  654. mthca_err(dev, "Failed to initialize "
  655. "completion queue table, aborting.\n");
  656. goto err_cmd_poll;
  657. }
  658. err = mthca_init_srq_table(dev);
  659. if (err) {
  660. mthca_err(dev, "Failed to initialize "
  661. "shared receive queue table, aborting.\n");
  662. goto err_cq_table_free;
  663. }
  664. err = mthca_init_qp_table(dev);
  665. if (err) {
  666. mthca_err(dev, "Failed to initialize "
  667. "queue pair table, aborting.\n");
  668. goto err_srq_table_free;
  669. }
  670. err = mthca_init_av_table(dev);
  671. if (err) {
  672. mthca_err(dev, "Failed to initialize "
  673. "address vector table, aborting.\n");
  674. goto err_qp_table_free;
  675. }
  676. err = mthca_init_mcg_table(dev);
  677. if (err) {
  678. mthca_err(dev, "Failed to initialize "
  679. "multicast group table, aborting.\n");
  680. goto err_av_table_free;
  681. }
  682. return 0;
  683. err_av_table_free:
  684. mthca_cleanup_av_table(dev);
  685. err_qp_table_free:
  686. mthca_cleanup_qp_table(dev);
  687. err_srq_table_free:
  688. mthca_cleanup_srq_table(dev);
  689. err_cq_table_free:
  690. mthca_cleanup_cq_table(dev);
  691. err_cmd_poll:
  692. mthca_cmd_use_polling(dev);
  693. err_eq_table_free:
  694. mthca_cleanup_eq_table(dev);
  695. err_pd_free:
  696. mthca_pd_free(dev, &dev->driver_pd);
  697. err_mr_table_free:
  698. mthca_cleanup_mr_table(dev);
  699. err_pd_table_free:
  700. mthca_cleanup_pd_table(dev);
  701. err_kar_unmap:
  702. iounmap(dev->kar);
  703. err_uar_free:
  704. mthca_uar_free(dev, &dev->driver_uar);
  705. err_uar_table_free:
  706. mthca_cleanup_uar_table(dev);
  707. return err;
  708. }
  709. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  710. int ddr_hidden)
  711. {
  712. int err;
  713. /*
  714. * We can't just use pci_request_regions() because the MSI-X
  715. * table is right in the middle of the first BAR. If we did
  716. * pci_request_region and grab all of the first BAR, then
  717. * setting up MSI-X would fail, since the PCI core wants to do
  718. * request_mem_region on the MSI-X vector table.
  719. *
  720. * So just request what we need right now, and request any
  721. * other regions we need when setting up EQs.
  722. */
  723. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  724. MTHCA_HCR_SIZE, DRV_NAME))
  725. return -EBUSY;
  726. err = pci_request_region(pdev, 2, DRV_NAME);
  727. if (err)
  728. goto err_bar2_failed;
  729. if (!ddr_hidden) {
  730. err = pci_request_region(pdev, 4, DRV_NAME);
  731. if (err)
  732. goto err_bar4_failed;
  733. }
  734. return 0;
  735. err_bar4_failed:
  736. pci_release_region(pdev, 2);
  737. err_bar2_failed:
  738. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  739. MTHCA_HCR_SIZE);
  740. return err;
  741. }
  742. static void mthca_release_regions(struct pci_dev *pdev,
  743. int ddr_hidden)
  744. {
  745. if (!ddr_hidden)
  746. pci_release_region(pdev, 4);
  747. pci_release_region(pdev, 2);
  748. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  749. MTHCA_HCR_SIZE);
  750. }
  751. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  752. {
  753. struct msix_entry entries[3];
  754. int err;
  755. entries[0].entry = 0;
  756. entries[1].entry = 1;
  757. entries[2].entry = 2;
  758. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  759. if (err) {
  760. if (err > 0)
  761. mthca_info(mdev, "Only %d MSI-X vectors available, "
  762. "not using MSI-X\n", err);
  763. return err;
  764. }
  765. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  766. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  767. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  768. return 0;
  769. }
  770. /* Types of supported HCA */
  771. enum {
  772. TAVOR, /* MT23108 */
  773. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  774. ARBEL_NATIVE, /* MT25208 with extended features */
  775. SINAI /* MT25204 */
  776. };
  777. #define MTHCA_FW_VER(major, minor, subminor) \
  778. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  779. static struct {
  780. u64 latest_fw;
  781. int is_memfree;
  782. int is_pcie;
  783. } mthca_hca_table[] = {
  784. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 3, 3), .is_memfree = 0, .is_pcie = 0 },
  785. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 0), .is_memfree = 0, .is_pcie = 1 },
  786. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0), .is_memfree = 1, .is_pcie = 1 },
  787. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 1), .is_memfree = 1, .is_pcie = 1 }
  788. };
  789. static int __devinit mthca_init_one(struct pci_dev *pdev,
  790. const struct pci_device_id *id)
  791. {
  792. static int mthca_version_printed = 0;
  793. int ddr_hidden = 0;
  794. int err;
  795. struct mthca_dev *mdev;
  796. if (!mthca_version_printed) {
  797. printk(KERN_INFO "%s", mthca_version);
  798. ++mthca_version_printed;
  799. }
  800. printk(KERN_INFO PFX "Initializing %s\n",
  801. pci_name(pdev));
  802. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  803. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  804. pci_name(pdev), id->driver_data);
  805. return -ENODEV;
  806. }
  807. err = pci_enable_device(pdev);
  808. if (err) {
  809. dev_err(&pdev->dev, "Cannot enable PCI device, "
  810. "aborting.\n");
  811. return err;
  812. }
  813. /*
  814. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  815. * be present)
  816. */
  817. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  818. pci_resource_len(pdev, 0) != 1 << 20) {
  819. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  820. err = -ENODEV;
  821. goto err_disable_pdev;
  822. }
  823. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM) ||
  824. pci_resource_len(pdev, 2) != 1 << 23) {
  825. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  826. err = -ENODEV;
  827. goto err_disable_pdev;
  828. }
  829. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  830. ddr_hidden = 1;
  831. err = mthca_request_regions(pdev, ddr_hidden);
  832. if (err) {
  833. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  834. "aborting.\n");
  835. goto err_disable_pdev;
  836. }
  837. pci_set_master(pdev);
  838. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  839. if (err) {
  840. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  841. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  842. if (err) {
  843. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  844. goto err_free_res;
  845. }
  846. }
  847. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  848. if (err) {
  849. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  850. "consistent PCI DMA mask.\n");
  851. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  852. if (err) {
  853. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  854. "aborting.\n");
  855. goto err_free_res;
  856. }
  857. }
  858. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  859. if (!mdev) {
  860. dev_err(&pdev->dev, "Device struct alloc failed, "
  861. "aborting.\n");
  862. err = -ENOMEM;
  863. goto err_free_res;
  864. }
  865. mdev->pdev = pdev;
  866. if (ddr_hidden)
  867. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  868. if (mthca_hca_table[id->driver_data].is_memfree)
  869. mdev->mthca_flags |= MTHCA_FLAG_MEMFREE;
  870. if (mthca_hca_table[id->driver_data].is_pcie)
  871. mdev->mthca_flags |= MTHCA_FLAG_PCIE;
  872. /*
  873. * Now reset the HCA before we touch the PCI capabilities or
  874. * attempt a firmware command, since a boot ROM may have left
  875. * the HCA in an undefined state.
  876. */
  877. err = mthca_reset(mdev);
  878. if (err) {
  879. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  880. goto err_free_dev;
  881. }
  882. if (msi_x && !mthca_enable_msi_x(mdev))
  883. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  884. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  885. !pci_enable_msi(pdev))
  886. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  887. if (mthca_cmd_init(mdev)) {
  888. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  889. goto err_free_dev;
  890. }
  891. err = mthca_tune_pci(mdev);
  892. if (err)
  893. goto err_cmd;
  894. err = mthca_init_hca(mdev);
  895. if (err)
  896. goto err_cmd;
  897. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  898. mthca_warn(mdev, "HCA FW version %d.%d.%d is old (%d.%d.%d is current).\n",
  899. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  900. (int) (mdev->fw_ver & 0xffff),
  901. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  902. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  903. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  904. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  905. }
  906. err = mthca_setup_hca(mdev);
  907. if (err)
  908. goto err_close;
  909. err = mthca_register_device(mdev);
  910. if (err)
  911. goto err_cleanup;
  912. err = mthca_create_agents(mdev);
  913. if (err)
  914. goto err_unregister;
  915. pci_set_drvdata(pdev, mdev);
  916. return 0;
  917. err_unregister:
  918. mthca_unregister_device(mdev);
  919. err_cleanup:
  920. mthca_cleanup_mcg_table(mdev);
  921. mthca_cleanup_av_table(mdev);
  922. mthca_cleanup_qp_table(mdev);
  923. mthca_cleanup_srq_table(mdev);
  924. mthca_cleanup_cq_table(mdev);
  925. mthca_cmd_use_polling(mdev);
  926. mthca_cleanup_eq_table(mdev);
  927. mthca_pd_free(mdev, &mdev->driver_pd);
  928. mthca_cleanup_mr_table(mdev);
  929. mthca_cleanup_pd_table(mdev);
  930. mthca_cleanup_uar_table(mdev);
  931. err_close:
  932. mthca_close_hca(mdev);
  933. err_cmd:
  934. mthca_cmd_cleanup(mdev);
  935. err_free_dev:
  936. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  937. pci_disable_msix(pdev);
  938. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  939. pci_disable_msi(pdev);
  940. ib_dealloc_device(&mdev->ib_dev);
  941. err_free_res:
  942. mthca_release_regions(pdev, ddr_hidden);
  943. err_disable_pdev:
  944. pci_disable_device(pdev);
  945. pci_set_drvdata(pdev, NULL);
  946. return err;
  947. }
  948. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  949. {
  950. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  951. u8 status;
  952. int p;
  953. if (mdev) {
  954. mthca_free_agents(mdev);
  955. mthca_unregister_device(mdev);
  956. for (p = 1; p <= mdev->limits.num_ports; ++p)
  957. mthca_CLOSE_IB(mdev, p, &status);
  958. mthca_cleanup_mcg_table(mdev);
  959. mthca_cleanup_av_table(mdev);
  960. mthca_cleanup_qp_table(mdev);
  961. mthca_cleanup_srq_table(mdev);
  962. mthca_cleanup_cq_table(mdev);
  963. mthca_cmd_use_polling(mdev);
  964. mthca_cleanup_eq_table(mdev);
  965. mthca_pd_free(mdev, &mdev->driver_pd);
  966. mthca_cleanup_mr_table(mdev);
  967. mthca_cleanup_pd_table(mdev);
  968. iounmap(mdev->kar);
  969. mthca_uar_free(mdev, &mdev->driver_uar);
  970. mthca_cleanup_uar_table(mdev);
  971. mthca_close_hca(mdev);
  972. mthca_cmd_cleanup(mdev);
  973. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  974. pci_disable_msix(pdev);
  975. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  976. pci_disable_msi(pdev);
  977. ib_dealloc_device(&mdev->ib_dev);
  978. mthca_release_regions(pdev, mdev->mthca_flags &
  979. MTHCA_FLAG_DDR_HIDDEN);
  980. pci_disable_device(pdev);
  981. pci_set_drvdata(pdev, NULL);
  982. }
  983. }
  984. static struct pci_device_id mthca_pci_table[] = {
  985. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  986. .driver_data = TAVOR },
  987. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  988. .driver_data = TAVOR },
  989. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  990. .driver_data = ARBEL_COMPAT },
  991. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  992. .driver_data = ARBEL_COMPAT },
  993. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  994. .driver_data = ARBEL_NATIVE },
  995. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  996. .driver_data = ARBEL_NATIVE },
  997. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  998. .driver_data = SINAI },
  999. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  1000. .driver_data = SINAI },
  1001. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1002. .driver_data = SINAI },
  1003. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  1004. .driver_data = SINAI },
  1005. { 0, }
  1006. };
  1007. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  1008. static struct pci_driver mthca_driver = {
  1009. .name = DRV_NAME,
  1010. .id_table = mthca_pci_table,
  1011. .probe = mthca_init_one,
  1012. .remove = __devexit_p(mthca_remove_one)
  1013. };
  1014. static int __init mthca_init(void)
  1015. {
  1016. int ret;
  1017. ret = pci_register_driver(&mthca_driver);
  1018. return ret < 0 ? ret : 0;
  1019. }
  1020. static void __exit mthca_cleanup(void)
  1021. {
  1022. pci_unregister_driver(&mthca_driver);
  1023. }
  1024. module_init(mthca_init);
  1025. module_exit(mthca_cleanup);