tlclk.c 22 KB

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  1. /*
  2. * Telecom Clock driver for Intel NetStructure(tm) MPCBL0010
  3. *
  4. * Copyright (C) 2005 Kontron Canada
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or (at
  11. * your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  16. * NON INFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. *
  23. * Send feedback to <sebastien.bouchard@ca.kontron.com> and the current
  24. * Maintainer <mark.gross@intel.com>
  25. *
  26. * Description : This is the TELECOM CLOCK module driver for the ATCA
  27. * MPCBL0010 ATCA computer.
  28. */
  29. #include <linux/config.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/sched.h>
  33. #include <linux/kernel.h> /* printk() */
  34. #include <linux/fs.h> /* everything... */
  35. #include <linux/errno.h> /* error codes */
  36. #include <linux/delay.h> /* udelay */
  37. #include <linux/slab.h>
  38. #include <linux/ioport.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/spinlock.h>
  41. #include <linux/timer.h>
  42. #include <linux/sysfs.h>
  43. #include <linux/device.h>
  44. #include <linux/miscdevice.h>
  45. #include <linux/platform_device.h>
  46. #include <asm/io.h> /* inb/outb */
  47. #include <asm/uaccess.h>
  48. MODULE_AUTHOR("Sebastien Bouchard <sebastien.bouchard@ca.kontron.com>");
  49. MODULE_LICENSE("GPL");
  50. /*Hardware Reset of the PLL */
  51. #define RESET_ON 0x00
  52. #define RESET_OFF 0x01
  53. /* MODE SELECT */
  54. #define NORMAL_MODE 0x00
  55. #define HOLDOVER_MODE 0x10
  56. #define FREERUN_MODE 0x20
  57. /* FILTER SELECT */
  58. #define FILTER_6HZ 0x04
  59. #define FILTER_12HZ 0x00
  60. /* SELECT REFERENCE FREQUENCY */
  61. #define REF_CLK1_8kHz 0x00
  62. #define REF_CLK2_19_44MHz 0x02
  63. /* Select primary or secondary redundant clock */
  64. #define PRIMARY_CLOCK 0x00
  65. #define SECONDARY_CLOCK 0x01
  66. /* CLOCK TRANSMISSION DEFINE */
  67. #define CLK_8kHz 0xff
  68. #define CLK_16_384MHz 0xfb
  69. #define CLK_1_544MHz 0x00
  70. #define CLK_2_048MHz 0x01
  71. #define CLK_4_096MHz 0x02
  72. #define CLK_6_312MHz 0x03
  73. #define CLK_8_192MHz 0x04
  74. #define CLK_19_440MHz 0x06
  75. #define CLK_8_592MHz 0x08
  76. #define CLK_11_184MHz 0x09
  77. #define CLK_34_368MHz 0x0b
  78. #define CLK_44_736MHz 0x0a
  79. /* RECEIVED REFERENCE */
  80. #define AMC_B1 0
  81. #define AMC_B2 1
  82. /* HARDWARE SWITCHING DEFINE */
  83. #define HW_ENABLE 0x80
  84. #define HW_DISABLE 0x00
  85. /* HARDWARE SWITCHING MODE DEFINE */
  86. #define PLL_HOLDOVER 0x40
  87. #define LOST_CLOCK 0x00
  88. /* ALARMS DEFINE */
  89. #define UNLOCK_MASK 0x10
  90. #define HOLDOVER_MASK 0x20
  91. #define SEC_LOST_MASK 0x40
  92. #define PRI_LOST_MASK 0x80
  93. /* INTERRUPT CAUSE DEFINE */
  94. #define PRI_LOS_01_MASK 0x01
  95. #define PRI_LOS_10_MASK 0x02
  96. #define SEC_LOS_01_MASK 0x04
  97. #define SEC_LOS_10_MASK 0x08
  98. #define HOLDOVER_01_MASK 0x10
  99. #define HOLDOVER_10_MASK 0x20
  100. #define UNLOCK_01_MASK 0x40
  101. #define UNLOCK_10_MASK 0x80
  102. struct tlclk_alarms {
  103. __u32 lost_clocks;
  104. __u32 lost_primary_clock;
  105. __u32 lost_secondary_clock;
  106. __u32 primary_clock_back;
  107. __u32 secondary_clock_back;
  108. __u32 switchover_primary;
  109. __u32 switchover_secondary;
  110. __u32 pll_holdover;
  111. __u32 pll_end_holdover;
  112. __u32 pll_lost_sync;
  113. __u32 pll_sync;
  114. };
  115. /* Telecom clock I/O register definition */
  116. #define TLCLK_BASE 0xa08
  117. #define TLCLK_REG0 TLCLK_BASE
  118. #define TLCLK_REG1 (TLCLK_BASE+1)
  119. #define TLCLK_REG2 (TLCLK_BASE+2)
  120. #define TLCLK_REG3 (TLCLK_BASE+3)
  121. #define TLCLK_REG4 (TLCLK_BASE+4)
  122. #define TLCLK_REG5 (TLCLK_BASE+5)
  123. #define TLCLK_REG6 (TLCLK_BASE+6)
  124. #define TLCLK_REG7 (TLCLK_BASE+7)
  125. #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)
  126. /* 0 = Dynamic allocation of the major device number */
  127. #define TLCLK_MAJOR 0
  128. /* sysfs interface definition:
  129. Upon loading the driver will create a sysfs directory under
  130. /sys/devices/platform/telco_clock.
  131. This directory exports the following interfaces. There operation is
  132. documented in the MCPBL0010 TPS under the Telecom Clock API section, 11.4.
  133. alarms :
  134. current_ref :
  135. enable_clk3a_output :
  136. enable_clk3b_output :
  137. enable_clka0_output :
  138. enable_clka1_output :
  139. enable_clkb0_output :
  140. enable_clkb1_output :
  141. filter_select :
  142. hardware_switching :
  143. hardware_switching_mode :
  144. interrupt_switch :
  145. mode_select :
  146. refalign :
  147. reset :
  148. select_amcb1_transmit_clock :
  149. select_amcb2_transmit_clock :
  150. select_redundant_clock :
  151. select_ref_frequency :
  152. test_mode :
  153. All sysfs interfaces are integers in hex format, i.e echo 99 > refalign
  154. has the same effect as echo 0x99 > refalign.
  155. */
  156. static unsigned int telclk_interrupt;
  157. static int int_events; /* Event that generate a interrupt */
  158. static int got_event; /* if events processing have been done */
  159. static void switchover_timeout(unsigned long data);
  160. static struct timer_list switchover_timer =
  161. TIMER_INITIALIZER(switchover_timeout , 0, 0);
  162. static struct tlclk_alarms *alarm_events;
  163. static DEFINE_SPINLOCK(event_lock);
  164. static int tlclk_major = TLCLK_MAJOR;
  165. static irqreturn_t tlclk_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  166. static DECLARE_WAIT_QUEUE_HEAD(wq);
  167. static int tlclk_open(struct inode *inode, struct file *filp)
  168. {
  169. int result;
  170. /* Make sure there is no interrupt pending while
  171. * initialising interrupt handler */
  172. inb(TLCLK_REG6);
  173. /* This device is wired through the FPGA IO space of the ATCA blade
  174. * we can't share this IRQ */
  175. result = request_irq(telclk_interrupt, &tlclk_interrupt,
  176. SA_INTERRUPT, "telco_clock", tlclk_interrupt);
  177. if (result == -EBUSY) {
  178. printk(KERN_ERR "tlclk: Interrupt can't be reserved.\n");
  179. return -EBUSY;
  180. }
  181. inb(TLCLK_REG6); /* Clear interrupt events */
  182. return 0;
  183. }
  184. static int tlclk_release(struct inode *inode, struct file *filp)
  185. {
  186. free_irq(telclk_interrupt, tlclk_interrupt);
  187. return 0;
  188. }
  189. ssize_t tlclk_read(struct file *filp, char __user *buf, size_t count,
  190. loff_t *f_pos)
  191. {
  192. if (count < sizeof(struct tlclk_alarms))
  193. return -EIO;
  194. wait_event_interruptible(wq, got_event);
  195. if (copy_to_user(buf, alarm_events, sizeof(struct tlclk_alarms)))
  196. return -EFAULT;
  197. memset(alarm_events, 0, sizeof(struct tlclk_alarms));
  198. got_event = 0;
  199. return sizeof(struct tlclk_alarms);
  200. }
  201. ssize_t tlclk_write(struct file *filp, const char __user *buf, size_t count,
  202. loff_t *f_pos)
  203. {
  204. return 0;
  205. }
  206. static struct file_operations tlclk_fops = {
  207. .read = tlclk_read,
  208. .write = tlclk_write,
  209. .open = tlclk_open,
  210. .release = tlclk_release,
  211. };
  212. static struct miscdevice tlclk_miscdev = {
  213. .minor = MISC_DYNAMIC_MINOR,
  214. .name = "telco_clock",
  215. .fops = &tlclk_fops,
  216. };
  217. static ssize_t show_current_ref(struct device *d,
  218. struct device_attribute *attr, char *buf)
  219. {
  220. unsigned long ret_val;
  221. unsigned long flags;
  222. spin_lock_irqsave(&event_lock, flags);
  223. ret_val = ((inb(TLCLK_REG1) & 0x08) >> 3);
  224. spin_unlock_irqrestore(&event_lock, flags);
  225. return sprintf(buf, "0x%lX\n", ret_val);
  226. }
  227. static DEVICE_ATTR(current_ref, S_IRUGO, show_current_ref, NULL);
  228. static ssize_t show_interrupt_switch(struct device *d,
  229. struct device_attribute *attr, char *buf)
  230. {
  231. unsigned long ret_val;
  232. unsigned long flags;
  233. spin_lock_irqsave(&event_lock, flags);
  234. ret_val = inb(TLCLK_REG6);
  235. spin_unlock_irqrestore(&event_lock, flags);
  236. return sprintf(buf, "0x%lX\n", ret_val);
  237. }
  238. static DEVICE_ATTR(interrupt_switch, S_IRUGO,
  239. show_interrupt_switch, NULL);
  240. static ssize_t show_alarms(struct device *d,
  241. struct device_attribute *attr, char *buf)
  242. {
  243. unsigned long ret_val;
  244. unsigned long flags;
  245. spin_lock_irqsave(&event_lock, flags);
  246. ret_val = (inb(TLCLK_REG2) & 0xf0);
  247. spin_unlock_irqrestore(&event_lock, flags);
  248. return sprintf(buf, "0x%lX\n", ret_val);
  249. }
  250. static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
  251. static ssize_t store_enable_clk3b_output(struct device *d,
  252. struct device_attribute *attr, const char *buf, size_t count)
  253. {
  254. unsigned long tmp;
  255. unsigned char val;
  256. unsigned long flags;
  257. sscanf(buf, "%lX", &tmp);
  258. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  259. val = (unsigned char)tmp;
  260. spin_lock_irqsave(&event_lock, flags);
  261. SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7);
  262. spin_unlock_irqrestore(&event_lock, flags);
  263. return strnlen(buf, count);
  264. }
  265. static DEVICE_ATTR(enable_clk3b_output, S_IWUGO, NULL,
  266. store_enable_clk3b_output);
  267. static ssize_t store_enable_clk3a_output(struct device *d,
  268. struct device_attribute *attr, const char *buf, size_t count)
  269. {
  270. unsigned long flags;
  271. unsigned long tmp;
  272. unsigned char val;
  273. sscanf(buf, "%lX", &tmp);
  274. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  275. val = (unsigned char)tmp;
  276. spin_lock_irqsave(&event_lock, flags);
  277. SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6);
  278. spin_unlock_irqrestore(&event_lock, flags);
  279. return strnlen(buf, count);
  280. }
  281. static DEVICE_ATTR(enable_clk3a_output, S_IWUGO, NULL,
  282. store_enable_clk3a_output);
  283. static ssize_t store_enable_clkb1_output(struct device *d,
  284. struct device_attribute *attr, const char *buf, size_t count)
  285. {
  286. unsigned long flags;
  287. unsigned long tmp;
  288. unsigned char val;
  289. sscanf(buf, "%lX", &tmp);
  290. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  291. val = (unsigned char)tmp;
  292. spin_lock_irqsave(&event_lock, flags);
  293. SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3);
  294. spin_unlock_irqrestore(&event_lock, flags);
  295. return strnlen(buf, count);
  296. }
  297. static DEVICE_ATTR(enable_clkb1_output, S_IWUGO, NULL,
  298. store_enable_clkb1_output);
  299. static ssize_t store_enable_clka1_output(struct device *d,
  300. struct device_attribute *attr, const char *buf, size_t count)
  301. {
  302. unsigned long flags;
  303. unsigned long tmp;
  304. unsigned char val;
  305. sscanf(buf, "%lX", &tmp);
  306. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  307. val = (unsigned char)tmp;
  308. spin_lock_irqsave(&event_lock, flags);
  309. SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2);
  310. spin_unlock_irqrestore(&event_lock, flags);
  311. return strnlen(buf, count);
  312. }
  313. static DEVICE_ATTR(enable_clka1_output, S_IWUGO, NULL,
  314. store_enable_clka1_output);
  315. static ssize_t store_enable_clkb0_output(struct device *d,
  316. struct device_attribute *attr, const char *buf, size_t count)
  317. {
  318. unsigned long flags;
  319. unsigned long tmp;
  320. unsigned char val;
  321. sscanf(buf, "%lX", &tmp);
  322. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  323. val = (unsigned char)tmp;
  324. spin_lock_irqsave(&event_lock, flags);
  325. SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1);
  326. spin_unlock_irqrestore(&event_lock, flags);
  327. return strnlen(buf, count);
  328. }
  329. static DEVICE_ATTR(enable_clkb0_output, S_IWUGO, NULL,
  330. store_enable_clkb0_output);
  331. static ssize_t store_enable_clka0_output(struct device *d,
  332. struct device_attribute *attr, const char *buf, size_t count)
  333. {
  334. unsigned long flags;
  335. unsigned long tmp;
  336. unsigned char val;
  337. sscanf(buf, "%lX", &tmp);
  338. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  339. val = (unsigned char)tmp;
  340. spin_lock_irqsave(&event_lock, flags);
  341. SET_PORT_BITS(TLCLK_REG2, 0xfe, val);
  342. spin_unlock_irqrestore(&event_lock, flags);
  343. return strnlen(buf, count);
  344. }
  345. static DEVICE_ATTR(enable_clka0_output, S_IWUGO, NULL,
  346. store_enable_clka0_output);
  347. static ssize_t store_test_mode(struct device *d,
  348. struct device_attribute *attr, const char *buf, size_t count)
  349. {
  350. unsigned long flags;
  351. unsigned long tmp;
  352. unsigned char val;
  353. sscanf(buf, "%lX", &tmp);
  354. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  355. val = (unsigned char)tmp;
  356. spin_lock_irqsave(&event_lock, flags);
  357. SET_PORT_BITS(TLCLK_REG4, 0xfd, 2);
  358. spin_unlock_irqrestore(&event_lock, flags);
  359. return strnlen(buf, count);
  360. }
  361. static DEVICE_ATTR(test_mode, S_IWUGO, NULL, store_test_mode);
  362. static ssize_t store_select_amcb2_transmit_clock(struct device *d,
  363. struct device_attribute *attr, const char *buf, size_t count)
  364. {
  365. unsigned long flags;
  366. unsigned long tmp;
  367. unsigned char val;
  368. sscanf(buf, "%lX", &tmp);
  369. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  370. val = (unsigned char)tmp;
  371. spin_lock_irqsave(&event_lock, flags);
  372. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  373. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);
  374. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  375. } else if (val >= CLK_8_592MHz) {
  376. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);
  377. switch (val) {
  378. case CLK_8_592MHz:
  379. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  380. break;
  381. case CLK_11_184MHz:
  382. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  383. break;
  384. case CLK_34_368MHz:
  385. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  386. break;
  387. case CLK_44_736MHz:
  388. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  389. break;
  390. }
  391. } else
  392. SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);
  393. spin_unlock_irqrestore(&event_lock, flags);
  394. return strnlen(buf, count);
  395. }
  396. static DEVICE_ATTR(select_amcb2_transmit_clock, S_IWUGO, NULL,
  397. store_select_amcb2_transmit_clock);
  398. static ssize_t store_select_amcb1_transmit_clock(struct device *d,
  399. struct device_attribute *attr, const char *buf, size_t count)
  400. {
  401. unsigned long tmp;
  402. unsigned char val;
  403. unsigned long flags;
  404. sscanf(buf, "%lX", &tmp);
  405. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  406. val = (unsigned char)tmp;
  407. spin_lock_irqsave(&event_lock, flags);
  408. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  409. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);
  410. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  411. } else if (val >= CLK_8_592MHz) {
  412. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);
  413. switch (val) {
  414. case CLK_8_592MHz:
  415. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  416. break;
  417. case CLK_11_184MHz:
  418. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  419. break;
  420. case CLK_34_368MHz:
  421. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  422. break;
  423. case CLK_44_736MHz:
  424. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  425. break;
  426. }
  427. } else
  428. SET_PORT_BITS(TLCLK_REG3, 0xf8, val);
  429. spin_unlock_irqrestore(&event_lock, flags);
  430. return strnlen(buf, count);
  431. }
  432. static DEVICE_ATTR(select_amcb1_transmit_clock, S_IWUGO, NULL,
  433. store_select_amcb1_transmit_clock);
  434. static ssize_t store_select_redundant_clock(struct device *d,
  435. struct device_attribute *attr, const char *buf, size_t count)
  436. {
  437. unsigned long tmp;
  438. unsigned char val;
  439. unsigned long flags;
  440. sscanf(buf, "%lX", &tmp);
  441. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  442. val = (unsigned char)tmp;
  443. spin_lock_irqsave(&event_lock, flags);
  444. SET_PORT_BITS(TLCLK_REG1, 0xfe, val);
  445. spin_unlock_irqrestore(&event_lock, flags);
  446. return strnlen(buf, count);
  447. }
  448. static DEVICE_ATTR(select_redundant_clock, S_IWUGO, NULL,
  449. store_select_redundant_clock);
  450. static ssize_t store_select_ref_frequency(struct device *d,
  451. struct device_attribute *attr, const char *buf, size_t count)
  452. {
  453. unsigned long tmp;
  454. unsigned char val;
  455. unsigned long flags;
  456. sscanf(buf, "%lX", &tmp);
  457. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  458. val = (unsigned char)tmp;
  459. spin_lock_irqsave(&event_lock, flags);
  460. SET_PORT_BITS(TLCLK_REG1, 0xfd, val);
  461. spin_unlock_irqrestore(&event_lock, flags);
  462. return strnlen(buf, count);
  463. }
  464. static DEVICE_ATTR(select_ref_frequency, S_IWUGO, NULL,
  465. store_select_ref_frequency);
  466. static ssize_t store_filter_select(struct device *d,
  467. struct device_attribute *attr, const char *buf, size_t count)
  468. {
  469. unsigned long tmp;
  470. unsigned char val;
  471. unsigned long flags;
  472. sscanf(buf, "%lX", &tmp);
  473. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  474. val = (unsigned char)tmp;
  475. spin_lock_irqsave(&event_lock, flags);
  476. SET_PORT_BITS(TLCLK_REG0, 0xfb, val);
  477. spin_unlock_irqrestore(&event_lock, flags);
  478. return strnlen(buf, count);
  479. }
  480. static DEVICE_ATTR(filter_select, S_IWUGO, NULL, store_filter_select);
  481. static ssize_t store_hardware_switching_mode(struct device *d,
  482. struct device_attribute *attr, const char *buf, size_t count)
  483. {
  484. unsigned long tmp;
  485. unsigned char val;
  486. unsigned long flags;
  487. sscanf(buf, "%lX", &tmp);
  488. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  489. val = (unsigned char)tmp;
  490. spin_lock_irqsave(&event_lock, flags);
  491. SET_PORT_BITS(TLCLK_REG0, 0xbf, val);
  492. spin_unlock_irqrestore(&event_lock, flags);
  493. return strnlen(buf, count);
  494. }
  495. static DEVICE_ATTR(hardware_switching_mode, S_IWUGO, NULL,
  496. store_hardware_switching_mode);
  497. static ssize_t store_hardware_switching(struct device *d,
  498. struct device_attribute *attr, const char *buf, size_t count)
  499. {
  500. unsigned long tmp;
  501. unsigned char val;
  502. unsigned long flags;
  503. sscanf(buf, "%lX", &tmp);
  504. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  505. val = (unsigned char)tmp;
  506. spin_lock_irqsave(&event_lock, flags);
  507. SET_PORT_BITS(TLCLK_REG0, 0x7f, val);
  508. spin_unlock_irqrestore(&event_lock, flags);
  509. return strnlen(buf, count);
  510. }
  511. static DEVICE_ATTR(hardware_switching, S_IWUGO, NULL,
  512. store_hardware_switching);
  513. static ssize_t store_refalign (struct device *d,
  514. struct device_attribute *attr, const char *buf, size_t count)
  515. {
  516. unsigned long tmp;
  517. unsigned long flags;
  518. sscanf(buf, "%lX", &tmp);
  519. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  520. spin_lock_irqsave(&event_lock, flags);
  521. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  522. udelay(2);
  523. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08);
  524. udelay(2);
  525. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  526. spin_unlock_irqrestore(&event_lock, flags);
  527. return strnlen(buf, count);
  528. }
  529. static DEVICE_ATTR(refalign, S_IWUGO, NULL, store_refalign);
  530. static ssize_t store_mode_select (struct device *d,
  531. struct device_attribute *attr, const char *buf, size_t count)
  532. {
  533. unsigned long tmp;
  534. unsigned char val;
  535. unsigned long flags;
  536. sscanf(buf, "%lX", &tmp);
  537. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  538. val = (unsigned char)tmp;
  539. spin_lock_irqsave(&event_lock, flags);
  540. SET_PORT_BITS(TLCLK_REG0, 0xcf, val);
  541. spin_unlock_irqrestore(&event_lock, flags);
  542. return strnlen(buf, count);
  543. }
  544. static DEVICE_ATTR(mode_select, S_IWUGO, NULL, store_mode_select);
  545. static ssize_t store_reset (struct device *d,
  546. struct device_attribute *attr, const char *buf, size_t count)
  547. {
  548. unsigned long tmp;
  549. unsigned char val;
  550. unsigned long flags;
  551. sscanf(buf, "%lX", &tmp);
  552. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  553. val = (unsigned char)tmp;
  554. spin_lock_irqsave(&event_lock, flags);
  555. SET_PORT_BITS(TLCLK_REG4, 0xfd, val);
  556. spin_unlock_irqrestore(&event_lock, flags);
  557. return strnlen(buf, count);
  558. }
  559. static DEVICE_ATTR(reset, S_IWUGO, NULL, store_reset);
  560. static struct attribute *tlclk_sysfs_entries[] = {
  561. &dev_attr_current_ref.attr,
  562. &dev_attr_interrupt_switch.attr,
  563. &dev_attr_alarms.attr,
  564. &dev_attr_enable_clk3a_output.attr,
  565. &dev_attr_enable_clk3b_output.attr,
  566. &dev_attr_enable_clkb1_output.attr,
  567. &dev_attr_enable_clka1_output.attr,
  568. &dev_attr_enable_clkb0_output.attr,
  569. &dev_attr_enable_clka0_output.attr,
  570. &dev_attr_test_mode.attr,
  571. &dev_attr_select_amcb1_transmit_clock.attr,
  572. &dev_attr_select_amcb2_transmit_clock.attr,
  573. &dev_attr_select_redundant_clock.attr,
  574. &dev_attr_select_ref_frequency.attr,
  575. &dev_attr_filter_select.attr,
  576. &dev_attr_hardware_switching_mode.attr,
  577. &dev_attr_hardware_switching.attr,
  578. &dev_attr_refalign.attr,
  579. &dev_attr_mode_select.attr,
  580. &dev_attr_reset.attr,
  581. NULL
  582. };
  583. static struct attribute_group tlclk_attribute_group = {
  584. .name = NULL, /* put in device directory */
  585. .attrs = tlclk_sysfs_entries,
  586. };
  587. static struct platform_device *tlclk_device;
  588. static int __init tlclk_init(void)
  589. {
  590. int ret;
  591. ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops);
  592. if (ret < 0) {
  593. printk(KERN_ERR "tlclk: can't get major %d.\n", tlclk_major);
  594. return ret;
  595. }
  596. alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL);
  597. if (!alarm_events)
  598. goto out1;
  599. /* Read telecom clock IRQ number (Set by BIOS) */
  600. if (!request_region(TLCLK_BASE, 8, "telco_clock")) {
  601. printk(KERN_ERR "tlclk: request_region 0x%X failed.\n",
  602. TLCLK_BASE);
  603. ret = -EBUSY;
  604. goto out2;
  605. }
  606. telclk_interrupt = (inb(TLCLK_REG7) & 0x0f);
  607. if (0x0F == telclk_interrupt ) { /* not MCPBL0010 ? */
  608. printk(KERN_ERR "telclk_interrup = 0x%x non-mcpbl0010 hw.\n",
  609. telclk_interrupt);
  610. ret = -ENXIO;
  611. goto out3;
  612. }
  613. init_timer(&switchover_timer);
  614. ret = misc_register(&tlclk_miscdev);
  615. if (ret < 0) {
  616. printk(KERN_ERR "tlclk: misc_register returns %d.\n", ret);
  617. ret = -EBUSY;
  618. goto out3;
  619. }
  620. tlclk_device = platform_device_register_simple("telco_clock",
  621. -1, NULL, 0);
  622. if (!tlclk_device) {
  623. printk(KERN_ERR "tlclk: platform_device_register failed.\n");
  624. ret = -EBUSY;
  625. goto out4;
  626. }
  627. ret = sysfs_create_group(&tlclk_device->dev.kobj,
  628. &tlclk_attribute_group);
  629. if (ret) {
  630. printk(KERN_ERR "tlclk: failed to create sysfs device attributes.\n");
  631. sysfs_remove_group(&tlclk_device->dev.kobj,
  632. &tlclk_attribute_group);
  633. goto out5;
  634. }
  635. return 0;
  636. out5:
  637. platform_device_unregister(tlclk_device);
  638. out4:
  639. misc_deregister(&tlclk_miscdev);
  640. out3:
  641. release_region(TLCLK_BASE, 8);
  642. out2:
  643. kfree(alarm_events);
  644. out1:
  645. unregister_chrdev(tlclk_major, "telco_clock");
  646. return ret;
  647. }
  648. static void __exit tlclk_cleanup(void)
  649. {
  650. sysfs_remove_group(&tlclk_device->dev.kobj, &tlclk_attribute_group);
  651. platform_device_unregister(tlclk_device);
  652. misc_deregister(&tlclk_miscdev);
  653. unregister_chrdev(tlclk_major, "telco_clock");
  654. release_region(TLCLK_BASE, 8);
  655. del_timer_sync(&switchover_timer);
  656. kfree(alarm_events);
  657. }
  658. static void switchover_timeout(unsigned long data)
  659. {
  660. if ((data & 1)) {
  661. if ((inb(TLCLK_REG1) & 0x08) != (data & 0x08))
  662. alarm_events->switchover_primary++;
  663. } else {
  664. if ((inb(TLCLK_REG1) & 0x08) != (data & 0x08))
  665. alarm_events->switchover_secondary++;
  666. }
  667. /* Alarm processing is done, wake up read task */
  668. del_timer(&switchover_timer);
  669. got_event = 1;
  670. wake_up(&wq);
  671. }
  672. static irqreturn_t tlclk_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  673. {
  674. unsigned long flags;
  675. spin_lock_irqsave(&event_lock, flags);
  676. /* Read and clear interrupt events */
  677. int_events = inb(TLCLK_REG6);
  678. /* Primary_Los changed from 0 to 1 ? */
  679. if (int_events & PRI_LOS_01_MASK) {
  680. if (inb(TLCLK_REG2) & SEC_LOST_MASK)
  681. alarm_events->lost_clocks++;
  682. else
  683. alarm_events->lost_primary_clock++;
  684. }
  685. /* Primary_Los changed from 1 to 0 ? */
  686. if (int_events & PRI_LOS_10_MASK) {
  687. alarm_events->primary_clock_back++;
  688. SET_PORT_BITS(TLCLK_REG1, 0xFE, 1);
  689. }
  690. /* Secondary_Los changed from 0 to 1 ? */
  691. if (int_events & SEC_LOS_01_MASK) {
  692. if (inb(TLCLK_REG2) & PRI_LOST_MASK)
  693. alarm_events->lost_clocks++;
  694. else
  695. alarm_events->lost_secondary_clock++;
  696. }
  697. /* Secondary_Los changed from 1 to 0 ? */
  698. if (int_events & SEC_LOS_10_MASK) {
  699. alarm_events->secondary_clock_back++;
  700. SET_PORT_BITS(TLCLK_REG1, 0xFE, 0);
  701. }
  702. if (int_events & HOLDOVER_10_MASK)
  703. alarm_events->pll_end_holdover++;
  704. if (int_events & UNLOCK_01_MASK)
  705. alarm_events->pll_lost_sync++;
  706. if (int_events & UNLOCK_10_MASK)
  707. alarm_events->pll_sync++;
  708. /* Holdover changed from 0 to 1 ? */
  709. if (int_events & HOLDOVER_01_MASK) {
  710. alarm_events->pll_holdover++;
  711. /* TIMEOUT in ~10ms */
  712. switchover_timer.expires = jiffies + msecs_to_jiffies(10);
  713. switchover_timer.data = inb(TLCLK_REG1);
  714. add_timer(&switchover_timer);
  715. } else {
  716. got_event = 1;
  717. wake_up(&wq);
  718. }
  719. spin_unlock_irqrestore(&event_lock, flags);
  720. return IRQ_HANDLED;
  721. }
  722. module_init(tlclk_init);
  723. module_exit(tlclk_cleanup);