head_44x.S 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782
  1. /*
  2. * arch/ppc/kernel/head_44x.S
  3. *
  4. * Kernel execution entry point code.
  5. *
  6. * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
  7. * Initial PowerPC version.
  8. * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
  9. * Rewritten for PReP
  10. * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
  11. * Low-level exception handers, MMU support, and rewrite.
  12. * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  13. * PowerPC 8xx modifications.
  14. * Copyright (c) 1998-1999 TiVo, Inc.
  15. * PowerPC 403GCX modifications.
  16. * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  17. * PowerPC 403GCX/405GP modifications.
  18. * Copyright 2000 MontaVista Software Inc.
  19. * PPC405 modifications
  20. * PowerPC 403GCX/405GP modifications.
  21. * Author: MontaVista Software, Inc.
  22. * frank_rowand@mvista.com or source@mvista.com
  23. * debbie_chu@mvista.com
  24. * Copyright 2002-2005 MontaVista Software, Inc.
  25. * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  26. *
  27. * This program is free software; you can redistribute it and/or modify it
  28. * under the terms of the GNU General Public License as published by the
  29. * Free Software Foundation; either version 2 of the License, or (at your
  30. * option) any later version.
  31. */
  32. #include <linux/config.h>
  33. #include <asm/processor.h>
  34. #include <asm/page.h>
  35. #include <asm/mmu.h>
  36. #include <asm/pgtable.h>
  37. #include <asm/ibm4xx.h>
  38. #include <asm/ibm44x.h>
  39. #include <asm/cputable.h>
  40. #include <asm/thread_info.h>
  41. #include <asm/ppc_asm.h>
  42. #include <asm/asm-offsets.h>
  43. #include "head_booke.h"
  44. /* As with the other PowerPC ports, it is expected that when code
  45. * execution begins here, the following registers contain valid, yet
  46. * optional, information:
  47. *
  48. * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  49. * r4 - Starting address of the init RAM disk
  50. * r5 - Ending address of the init RAM disk
  51. * r6 - Start of kernel command line string (e.g. "mem=128")
  52. * r7 - End of kernel command line string
  53. *
  54. */
  55. .text
  56. _GLOBAL(_stext)
  57. _GLOBAL(_start)
  58. /*
  59. * Reserve a word at a fixed location to store the address
  60. * of abatron_pteptrs
  61. */
  62. nop
  63. /*
  64. * Save parameters we are passed
  65. */
  66. mr r31,r3
  67. mr r30,r4
  68. mr r29,r5
  69. mr r28,r6
  70. mr r27,r7
  71. li r24,0 /* CPU number */
  72. /*
  73. * Set up the initial MMU state
  74. *
  75. * We are still executing code at the virtual address
  76. * mappings set by the firmware for the base of RAM.
  77. *
  78. * We first invalidate all TLB entries but the one
  79. * we are running from. We then load the KERNELBASE
  80. * mappings so we can begin to use kernel addresses
  81. * natively and so the interrupt vector locations are
  82. * permanently pinned (necessary since Book E
  83. * implementations always have translation enabled).
  84. *
  85. * TODO: Use the known TLB entry we are running from to
  86. * determine which physical region we are located
  87. * in. This can be used to determine where in RAM
  88. * (on a shared CPU system) or PCI memory space
  89. * (on a DRAMless system) we are located.
  90. * For now, we assume a perfect world which means
  91. * we are located at the base of DRAM (physical 0).
  92. */
  93. /*
  94. * Search TLB for entry that we are currently using.
  95. * Invalidate all entries but the one we are using.
  96. */
  97. /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
  98. mfspr r3,SPRN_PID /* Get PID */
  99. mfmsr r4 /* Get MSR */
  100. andi. r4,r4,MSR_IS@l /* TS=1? */
  101. beq wmmucr /* If not, leave STS=0 */
  102. oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */
  103. wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
  104. sync
  105. bl invstr /* Find our address */
  106. invstr: mflr r5 /* Make it accessible */
  107. tlbsx r23,0,r5 /* Find entry we are in */
  108. li r4,0 /* Start at TLB entry 0 */
  109. li r3,0 /* Set PAGEID inval value */
  110. 1: cmpw r23,r4 /* Is this our entry? */
  111. beq skpinv /* If so, skip the inval */
  112. tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
  113. skpinv: addi r4,r4,1 /* Increment */
  114. cmpwi r4,64 /* Are we done? */
  115. bne 1b /* If not, repeat */
  116. isync /* If so, context change */
  117. /*
  118. * Configure and load pinned entry into TLB slot 63.
  119. */
  120. lis r3,KERNELBASE@h /* Load the kernel virtual address */
  121. ori r3,r3,KERNELBASE@l
  122. /* Kernel is at the base of RAM */
  123. li r4, 0 /* Load the kernel physical address */
  124. /* Load the kernel PID = 0 */
  125. li r0,0
  126. mtspr SPRN_PID,r0
  127. sync
  128. /* Initialize MMUCR */
  129. li r5,0
  130. mtspr SPRN_MMUCR,r5
  131. sync
  132. /* pageid fields */
  133. clrrwi r3,r3,10 /* Mask off the effective page number */
  134. ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
  135. /* xlat fields */
  136. clrrwi r4,r4,10 /* Mask off the real page number */
  137. /* ERPN is 0 for first 4GB page */
  138. /* attrib fields */
  139. /* Added guarded bit to protect against speculative loads/stores */
  140. li r5,0
  141. ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
  142. li r0,63 /* TLB slot 63 */
  143. tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
  144. tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
  145. tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
  146. /* Force context change */
  147. mfmsr r0
  148. mtspr SPRN_SRR1, r0
  149. lis r0,3f@h
  150. ori r0,r0,3f@l
  151. mtspr SPRN_SRR0,r0
  152. sync
  153. rfi
  154. /* If necessary, invalidate original entry we used */
  155. 3: cmpwi r23,63
  156. beq 4f
  157. li r6,0
  158. tlbwe r6,r23,PPC44x_TLB_PAGEID
  159. isync
  160. 4:
  161. #ifdef CONFIG_SERIAL_TEXT_DEBUG
  162. /*
  163. * Add temporary UART mapping for early debug.
  164. * We can map UART registers wherever we want as long as they don't
  165. * interfere with other system mappings (e.g. with pinned entries).
  166. * For an example of how we handle this - see ocotea.h. --ebs
  167. */
  168. /* pageid fields */
  169. lis r3,UART0_IO_BASE@h
  170. ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_4K
  171. /* xlat fields */
  172. lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */
  173. #ifndef CONFIG_440EP
  174. ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */
  175. #endif
  176. /* attrib fields */
  177. li r5,0
  178. ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G)
  179. li r0,0 /* TLB slot 0 */
  180. tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
  181. tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
  182. tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
  183. /* Force context change */
  184. isync
  185. #endif /* CONFIG_SERIAL_TEXT_DEBUG */
  186. /* Establish the interrupt vector offsets */
  187. SET_IVOR(0, CriticalInput);
  188. SET_IVOR(1, MachineCheck);
  189. SET_IVOR(2, DataStorage);
  190. SET_IVOR(3, InstructionStorage);
  191. SET_IVOR(4, ExternalInput);
  192. SET_IVOR(5, Alignment);
  193. SET_IVOR(6, Program);
  194. SET_IVOR(7, FloatingPointUnavailable);
  195. SET_IVOR(8, SystemCall);
  196. SET_IVOR(9, AuxillaryProcessorUnavailable);
  197. SET_IVOR(10, Decrementer);
  198. SET_IVOR(11, FixedIntervalTimer);
  199. SET_IVOR(12, WatchdogTimer);
  200. SET_IVOR(13, DataTLBError);
  201. SET_IVOR(14, InstructionTLBError);
  202. SET_IVOR(15, Debug);
  203. /* Establish the interrupt vector base */
  204. lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
  205. mtspr SPRN_IVPR,r4
  206. #ifdef CONFIG_440EP
  207. /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */
  208. mfspr r2,SPRN_CCR0
  209. lis r3,0xffef
  210. ori r3,r3,0xffff
  211. and r2,r2,r3
  212. mtspr SPRN_CCR0,r2
  213. isync
  214. #endif
  215. /*
  216. * This is where the main kernel code starts.
  217. */
  218. /* ptr to current */
  219. lis r2,init_task@h
  220. ori r2,r2,init_task@l
  221. /* ptr to current thread */
  222. addi r4,r2,THREAD /* init task's THREAD */
  223. mtspr SPRN_SPRG3,r4
  224. /* stack */
  225. lis r1,init_thread_union@h
  226. ori r1,r1,init_thread_union@l
  227. li r0,0
  228. stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
  229. bl early_init
  230. /*
  231. * Decide what sort of machine this is and initialize the MMU.
  232. */
  233. mr r3,r31
  234. mr r4,r30
  235. mr r5,r29
  236. mr r6,r28
  237. mr r7,r27
  238. bl machine_init
  239. bl MMU_init
  240. /* Setup PTE pointers for the Abatron bdiGDB */
  241. lis r6, swapper_pg_dir@h
  242. ori r6, r6, swapper_pg_dir@l
  243. lis r5, abatron_pteptrs@h
  244. ori r5, r5, abatron_pteptrs@l
  245. lis r4, KERNELBASE@h
  246. ori r4, r4, KERNELBASE@l
  247. stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
  248. stw r6, 0(r5)
  249. /* Let's move on */
  250. lis r4,start_kernel@h
  251. ori r4,r4,start_kernel@l
  252. lis r3,MSR_KERNEL@h
  253. ori r3,r3,MSR_KERNEL@l
  254. mtspr SPRN_SRR0,r4
  255. mtspr SPRN_SRR1,r3
  256. rfi /* change context and jump to start_kernel */
  257. /*
  258. * Interrupt vector entry code
  259. *
  260. * The Book E MMUs are always on so we don't need to handle
  261. * interrupts in real mode as with previous PPC processors. In
  262. * this case we handle interrupts in the kernel virtual address
  263. * space.
  264. *
  265. * Interrupt vectors are dynamically placed relative to the
  266. * interrupt prefix as determined by the address of interrupt_base.
  267. * The interrupt vectors offsets are programmed using the labels
  268. * for each interrupt vector entry.
  269. *
  270. * Interrupt vectors must be aligned on a 16 byte boundary.
  271. * We align on a 32 byte cache line boundary for good measure.
  272. */
  273. interrupt_base:
  274. /* Critical Input Interrupt */
  275. CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
  276. /* Machine Check Interrupt */
  277. #ifdef CONFIG_440A
  278. MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
  279. #else
  280. CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
  281. #endif
  282. /* Data Storage Interrupt */
  283. START_EXCEPTION(DataStorage)
  284. mtspr SPRN_SPRG0, r10 /* Save some working registers */
  285. mtspr SPRN_SPRG1, r11
  286. mtspr SPRN_SPRG4W, r12
  287. mtspr SPRN_SPRG5W, r13
  288. mfcr r11
  289. mtspr SPRN_SPRG7W, r11
  290. /*
  291. * Check if it was a store fault, if not then bail
  292. * because a user tried to access a kernel or
  293. * read-protected page. Otherwise, get the
  294. * offending address and handle it.
  295. */
  296. mfspr r10, SPRN_ESR
  297. andis. r10, r10, ESR_ST@h
  298. beq 2f
  299. mfspr r10, SPRN_DEAR /* Get faulting address */
  300. /* If we are faulting a kernel address, we have to use the
  301. * kernel page tables.
  302. */
  303. lis r11, TASK_SIZE@h
  304. cmplw r10, r11
  305. blt+ 3f
  306. lis r11, swapper_pg_dir@h
  307. ori r11, r11, swapper_pg_dir@l
  308. mfspr r12,SPRN_MMUCR
  309. rlwinm r12,r12,0,0,23 /* Clear TID */
  310. b 4f
  311. /* Get the PGD for the current thread */
  312. 3:
  313. mfspr r11,SPRN_SPRG3
  314. lwz r11,PGDIR(r11)
  315. /* Load PID into MMUCR TID */
  316. mfspr r12,SPRN_MMUCR /* Get MMUCR */
  317. mfspr r13,SPRN_PID /* Get PID */
  318. rlwimi r12,r13,0,24,31 /* Set TID */
  319. 4:
  320. mtspr SPRN_MMUCR,r12
  321. rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
  322. lwzx r11, r12, r11 /* Get pgd/pmd entry */
  323. rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
  324. beq 2f /* Bail if no table */
  325. rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
  326. lwz r11, 4(r12) /* Get pte entry */
  327. andi. r13, r11, _PAGE_RW /* Is it writeable? */
  328. beq 2f /* Bail if not */
  329. /* Update 'changed'.
  330. */
  331. ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
  332. stw r11, 4(r12) /* Update Linux page table */
  333. li r13, PPC44x_TLB_SR@l /* Set SR */
  334. rlwimi r13, r11, 29, 29, 29 /* SX = _PAGE_HWEXEC */
  335. rlwimi r13, r11, 0, 30, 30 /* SW = _PAGE_RW */
  336. rlwimi r13, r11, 29, 28, 28 /* UR = _PAGE_USER */
  337. rlwimi r12, r11, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
  338. rlwimi r12, r11, 29, 30, 30 /* (_PAGE_USER>>3)->r12 */
  339. and r12, r12, r11 /* HWEXEC/RW & USER */
  340. rlwimi r13, r12, 0, 26, 26 /* UX = HWEXEC & USER */
  341. rlwimi r13, r12, 3, 27, 27 /* UW = RW & USER */
  342. rlwimi r11,r13,0,26,31 /* Insert static perms */
  343. rlwinm r11,r11,0,20,15 /* Clear U0-U3 */
  344. /* find the TLB index that caused the fault. It has to be here. */
  345. tlbsx r10, 0, r10
  346. tlbwe r11, r10, PPC44x_TLB_ATTRIB /* Write ATTRIB */
  347. /* Done...restore registers and get out of here.
  348. */
  349. mfspr r11, SPRN_SPRG7R
  350. mtcr r11
  351. mfspr r13, SPRN_SPRG5R
  352. mfspr r12, SPRN_SPRG4R
  353. mfspr r11, SPRN_SPRG1
  354. mfspr r10, SPRN_SPRG0
  355. rfi /* Force context change */
  356. 2:
  357. /*
  358. * The bailout. Restore registers to pre-exception conditions
  359. * and call the heavyweights to help us out.
  360. */
  361. mfspr r11, SPRN_SPRG7R
  362. mtcr r11
  363. mfspr r13, SPRN_SPRG5R
  364. mfspr r12, SPRN_SPRG4R
  365. mfspr r11, SPRN_SPRG1
  366. mfspr r10, SPRN_SPRG0
  367. b data_access
  368. /* Instruction Storage Interrupt */
  369. INSTRUCTION_STORAGE_EXCEPTION
  370. /* External Input Interrupt */
  371. EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
  372. /* Alignment Interrupt */
  373. ALIGNMENT_EXCEPTION
  374. /* Program Interrupt */
  375. PROGRAM_EXCEPTION
  376. /* Floating Point Unavailable Interrupt */
  377. #ifdef CONFIG_PPC_FPU
  378. FP_UNAVAILABLE_EXCEPTION
  379. #else
  380. EXCEPTION(0x2010, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
  381. #endif
  382. /* System Call Interrupt */
  383. START_EXCEPTION(SystemCall)
  384. NORMAL_EXCEPTION_PROLOG
  385. EXC_XFER_EE_LITE(0x0c00, DoSyscall)
  386. /* Auxillary Processor Unavailable Interrupt */
  387. EXCEPTION(0x2020, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
  388. /* Decrementer Interrupt */
  389. DECREMENTER_EXCEPTION
  390. /* Fixed Internal Timer Interrupt */
  391. /* TODO: Add FIT support */
  392. EXCEPTION(0x1010, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
  393. /* Watchdog Timer Interrupt */
  394. /* TODO: Add watchdog support */
  395. #ifdef CONFIG_BOOKE_WDT
  396. CRITICAL_EXCEPTION(0x1020, WatchdogTimer, WatchdogException)
  397. #else
  398. CRITICAL_EXCEPTION(0x1020, WatchdogTimer, unknown_exception)
  399. #endif
  400. /* Data TLB Error Interrupt */
  401. START_EXCEPTION(DataTLBError)
  402. mtspr SPRN_SPRG0, r10 /* Save some working registers */
  403. mtspr SPRN_SPRG1, r11
  404. mtspr SPRN_SPRG4W, r12
  405. mtspr SPRN_SPRG5W, r13
  406. mfcr r11
  407. mtspr SPRN_SPRG7W, r11
  408. mfspr r10, SPRN_DEAR /* Get faulting address */
  409. /* If we are faulting a kernel address, we have to use the
  410. * kernel page tables.
  411. */
  412. lis r11, TASK_SIZE@h
  413. cmplw r10, r11
  414. blt+ 3f
  415. lis r11, swapper_pg_dir@h
  416. ori r11, r11, swapper_pg_dir@l
  417. mfspr r12,SPRN_MMUCR
  418. rlwinm r12,r12,0,0,23 /* Clear TID */
  419. b 4f
  420. /* Get the PGD for the current thread */
  421. 3:
  422. mfspr r11,SPRN_SPRG3
  423. lwz r11,PGDIR(r11)
  424. /* Load PID into MMUCR TID */
  425. mfspr r12,SPRN_MMUCR
  426. mfspr r13,SPRN_PID /* Get PID */
  427. rlwimi r12,r13,0,24,31 /* Set TID */
  428. 4:
  429. mtspr SPRN_MMUCR,r12
  430. rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
  431. lwzx r11, r12, r11 /* Get pgd/pmd entry */
  432. rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
  433. beq 2f /* Bail if no table */
  434. rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
  435. lwz r11, 4(r12) /* Get pte entry */
  436. andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
  437. beq 2f /* Bail if not present */
  438. ori r11, r11, _PAGE_ACCESSED
  439. stw r11, 4(r12)
  440. /* Jump to common tlb load */
  441. b finish_tlb_load
  442. 2:
  443. /* The bailout. Restore registers to pre-exception conditions
  444. * and call the heavyweights to help us out.
  445. */
  446. mfspr r11, SPRN_SPRG7R
  447. mtcr r11
  448. mfspr r13, SPRN_SPRG5R
  449. mfspr r12, SPRN_SPRG4R
  450. mfspr r11, SPRN_SPRG1
  451. mfspr r10, SPRN_SPRG0
  452. b data_access
  453. /* Instruction TLB Error Interrupt */
  454. /*
  455. * Nearly the same as above, except we get our
  456. * information from different registers and bailout
  457. * to a different point.
  458. */
  459. START_EXCEPTION(InstructionTLBError)
  460. mtspr SPRN_SPRG0, r10 /* Save some working registers */
  461. mtspr SPRN_SPRG1, r11
  462. mtspr SPRN_SPRG4W, r12
  463. mtspr SPRN_SPRG5W, r13
  464. mfcr r11
  465. mtspr SPRN_SPRG7W, r11
  466. mfspr r10, SPRN_SRR0 /* Get faulting address */
  467. /* If we are faulting a kernel address, we have to use the
  468. * kernel page tables.
  469. */
  470. lis r11, TASK_SIZE@h
  471. cmplw r10, r11
  472. blt+ 3f
  473. lis r11, swapper_pg_dir@h
  474. ori r11, r11, swapper_pg_dir@l
  475. mfspr r12,SPRN_MMUCR
  476. rlwinm r12,r12,0,0,23 /* Clear TID */
  477. b 4f
  478. /* Get the PGD for the current thread */
  479. 3:
  480. mfspr r11,SPRN_SPRG3
  481. lwz r11,PGDIR(r11)
  482. /* Load PID into MMUCR TID */
  483. mfspr r12,SPRN_MMUCR
  484. mfspr r13,SPRN_PID /* Get PID */
  485. rlwimi r12,r13,0,24,31 /* Set TID */
  486. 4:
  487. mtspr SPRN_MMUCR,r12
  488. rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
  489. lwzx r11, r12, r11 /* Get pgd/pmd entry */
  490. rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
  491. beq 2f /* Bail if no table */
  492. rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
  493. lwz r11, 4(r12) /* Get pte entry */
  494. andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
  495. beq 2f /* Bail if not present */
  496. ori r11, r11, _PAGE_ACCESSED
  497. stw r11, 4(r12)
  498. /* Jump to common TLB load point */
  499. b finish_tlb_load
  500. 2:
  501. /* The bailout. Restore registers to pre-exception conditions
  502. * and call the heavyweights to help us out.
  503. */
  504. mfspr r11, SPRN_SPRG7R
  505. mtcr r11
  506. mfspr r13, SPRN_SPRG5R
  507. mfspr r12, SPRN_SPRG4R
  508. mfspr r11, SPRN_SPRG1
  509. mfspr r10, SPRN_SPRG0
  510. b InstructionStorage
  511. /* Debug Interrupt */
  512. DEBUG_EXCEPTION
  513. /*
  514. * Local functions
  515. */
  516. /*
  517. * Data TLB exceptions will bail out to this point
  518. * if they can't resolve the lightweight TLB fault.
  519. */
  520. data_access:
  521. NORMAL_EXCEPTION_PROLOG
  522. mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
  523. stw r5,_ESR(r11)
  524. mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
  525. EXC_XFER_EE_LITE(0x0300, handle_page_fault)
  526. /*
  527. * Both the instruction and data TLB miss get to this
  528. * point to load the TLB.
  529. * r10 - EA of fault
  530. * r11 - available to use
  531. * r12 - Pointer to the 64-bit PTE
  532. * r13 - available to use
  533. * MMUCR - loaded with proper value when we get here
  534. * Upon exit, we reload everything and RFI.
  535. */
  536. finish_tlb_load:
  537. /*
  538. * We set execute, because we don't have the granularity to
  539. * properly set this at the page level (Linux problem).
  540. * If shared is set, we cause a zero PID->TID load.
  541. * Many of these bits are software only. Bits we don't set
  542. * here we (properly should) assume have the appropriate value.
  543. */
  544. /* Load the next available TLB index */
  545. lis r13, tlb_44x_index@ha
  546. lwz r13, tlb_44x_index@l(r13)
  547. /* Load the TLB high watermark */
  548. lis r11, tlb_44x_hwater@ha
  549. lwz r11, tlb_44x_hwater@l(r11)
  550. /* Increment, rollover, and store TLB index */
  551. addi r13, r13, 1
  552. cmpw 0, r13, r11 /* reserve entries */
  553. ble 7f
  554. li r13, 0
  555. 7:
  556. /* Store the next available TLB index */
  557. lis r11, tlb_44x_index@ha
  558. stw r13, tlb_44x_index@l(r11)
  559. lwz r11, 0(r12) /* Get MS word of PTE */
  560. lwz r12, 4(r12) /* Get LS word of PTE */
  561. rlwimi r11, r12, 0, 0 , 19 /* Insert RPN */
  562. tlbwe r11, r13, PPC44x_TLB_XLAT /* Write XLAT */
  563. /*
  564. * Create PAGEID. This is the faulting address,
  565. * page size, and valid flag.
  566. */
  567. li r11, PPC44x_TLB_VALID | PPC44x_TLB_4K
  568. rlwimi r10, r11, 0, 20, 31 /* Insert valid and page size */
  569. tlbwe r10, r13, PPC44x_TLB_PAGEID /* Write PAGEID */
  570. li r10, PPC44x_TLB_SR@l /* Set SR */
  571. rlwimi r10, r12, 0, 30, 30 /* Set SW = _PAGE_RW */
  572. rlwimi r10, r12, 29, 29, 29 /* SX = _PAGE_HWEXEC */
  573. rlwimi r10, r12, 29, 28, 28 /* UR = _PAGE_USER */
  574. rlwimi r11, r12, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
  575. and r11, r12, r11 /* HWEXEC & USER */
  576. rlwimi r10, r11, 0, 26, 26 /* UX = HWEXEC & USER */
  577. rlwimi r12, r10, 0, 26, 31 /* Insert static perms */
  578. rlwinm r12, r12, 0, 20, 15 /* Clear U0-U3 */
  579. tlbwe r12, r13, PPC44x_TLB_ATTRIB /* Write ATTRIB */
  580. /* Done...restore registers and get out of here.
  581. */
  582. mfspr r11, SPRN_SPRG7R
  583. mtcr r11
  584. mfspr r13, SPRN_SPRG5R
  585. mfspr r12, SPRN_SPRG4R
  586. mfspr r11, SPRN_SPRG1
  587. mfspr r10, SPRN_SPRG0
  588. rfi /* Force context change */
  589. /*
  590. * Global functions
  591. */
  592. /*
  593. * extern void giveup_altivec(struct task_struct *prev)
  594. *
  595. * The 44x core does not have an AltiVec unit.
  596. */
  597. _GLOBAL(giveup_altivec)
  598. blr
  599. /*
  600. * extern void giveup_fpu(struct task_struct *prev)
  601. *
  602. * The 44x core does not have an FPU.
  603. */
  604. #ifndef CONFIG_PPC_FPU
  605. _GLOBAL(giveup_fpu)
  606. blr
  607. #endif
  608. /*
  609. * extern void abort(void)
  610. *
  611. * At present, this routine just applies a system reset.
  612. */
  613. _GLOBAL(abort)
  614. mfspr r13,SPRN_DBCR0
  615. oris r13,r13,DBCR0_RST_SYSTEM@h
  616. mtspr SPRN_DBCR0,r13
  617. _GLOBAL(set_context)
  618. #ifdef CONFIG_BDI_SWITCH
  619. /* Context switch the PTE pointer for the Abatron BDI2000.
  620. * The PGDIR is the second parameter.
  621. */
  622. lis r5, abatron_pteptrs@h
  623. ori r5, r5, abatron_pteptrs@l
  624. stw r4, 0x4(r5)
  625. #endif
  626. mtspr SPRN_PID,r3
  627. isync /* Force context change */
  628. blr
  629. /*
  630. * We put a few things here that have to be page-aligned. This stuff
  631. * goes at the beginning of the data segment, which is page-aligned.
  632. */
  633. .data
  634. .align 12
  635. .globl sdata
  636. sdata:
  637. .globl empty_zero_page
  638. empty_zero_page:
  639. .space 4096
  640. /*
  641. * To support >32-bit physical addresses, we use an 8KB pgdir.
  642. */
  643. .globl swapper_pg_dir
  644. swapper_pg_dir:
  645. .space 8192
  646. /* Reserved 4k for the critical exception stack & 4k for the machine
  647. * check stack per CPU for kernel mode exceptions */
  648. .section .bss
  649. .align 12
  650. exception_stack_bottom:
  651. .space BOOKE_EXCEPTION_STACK_SIZE
  652. .globl exception_stack_top
  653. exception_stack_top:
  654. /*
  655. * This space gets a copy of optional info passed to us by the bootstrap
  656. * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
  657. */
  658. .globl cmd_line
  659. cmd_line:
  660. .space 512
  661. /*
  662. * Room for two PTE pointers, usually the kernel and current user pointers
  663. * to their respective root page table.
  664. */
  665. abatron_pteptrs:
  666. .space 8