iwl-agn.c 90 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. /* allow CTS-to-self if possible. this is relevant only for
  101. * 5000, but will not damage 4965 */
  102. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  103. ret = iwl_check_rxon_cmd(priv);
  104. if (ret) {
  105. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  106. return -EINVAL;
  107. }
  108. /* If we don't need to send a full RXON, we can use
  109. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  110. * and other flags for the current radio configuration. */
  111. if (!iwl_full_rxon_required(priv)) {
  112. ret = iwl_send_rxon_assoc(priv);
  113. if (ret) {
  114. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  115. return ret;
  116. }
  117. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  118. return 0;
  119. }
  120. /* station table will be cleared */
  121. priv->assoc_station_added = 0;
  122. /* If we are currently associated and the new config requires
  123. * an RXON_ASSOC and the new config wants the associated mask enabled,
  124. * we must clear the associated from the active configuration
  125. * before we apply the new config */
  126. if (iwl_is_associated(priv) && new_assoc) {
  127. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  128. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  129. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  130. sizeof(struct iwl_rxon_cmd),
  131. &priv->active_rxon);
  132. /* If the mask clearing failed then we set
  133. * active_rxon back to what it was previously */
  134. if (ret) {
  135. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  136. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  137. return ret;
  138. }
  139. }
  140. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  141. "* with%s RXON_FILTER_ASSOC_MSK\n"
  142. "* channel = %d\n"
  143. "* bssid = %pM\n",
  144. (new_assoc ? "" : "out"),
  145. le16_to_cpu(priv->staging_rxon.channel),
  146. priv->staging_rxon.bssid_addr);
  147. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  148. /* Apply the new configuration
  149. * RXON unassoc clears the station table in uCode, send it before
  150. * we add the bcast station. If assoc bit is set, we will send RXON
  151. * after having added the bcast and bssid station.
  152. */
  153. if (!new_assoc) {
  154. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  155. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  156. if (ret) {
  157. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  158. return ret;
  159. }
  160. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  161. }
  162. iwl_clear_stations_table(priv);
  163. priv->start_calib = 0;
  164. /* Add the broadcast address so we can send broadcast frames */
  165. if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
  166. IWL_INVALID_STATION) {
  167. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  168. return -EIO;
  169. }
  170. /* If we have set the ASSOC_MSK and we are in BSS mode then
  171. * add the IWL_AP_ID to the station rate table */
  172. if (new_assoc) {
  173. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  174. ret = iwl_rxon_add_station(priv,
  175. priv->active_rxon.bssid_addr, 1);
  176. if (ret == IWL_INVALID_STATION) {
  177. IWL_ERR(priv,
  178. "Error adding AP address for TX.\n");
  179. return -EIO;
  180. }
  181. priv->assoc_station_added = 1;
  182. if (priv->default_wep_key &&
  183. iwl_send_static_wepkey_cmd(priv, 0))
  184. IWL_ERR(priv,
  185. "Could not send WEP static key.\n");
  186. }
  187. /* Apply the new configuration
  188. * RXON assoc doesn't clear the station table in uCode,
  189. */
  190. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  191. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  192. if (ret) {
  193. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  194. return ret;
  195. }
  196. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  197. }
  198. iwl_init_sensitivity(priv);
  199. /* If we issue a new RXON command which required a tune then we must
  200. * send a new TXPOWER command or we won't be able to Tx any frames */
  201. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  202. if (ret) {
  203. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  204. return ret;
  205. }
  206. return 0;
  207. }
  208. void iwl_update_chain_flags(struct iwl_priv *priv)
  209. {
  210. if (priv->cfg->ops->hcmd->set_rxon_chain)
  211. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  212. iwlcore_commit_rxon(priv);
  213. }
  214. static void iwl_clear_free_frames(struct iwl_priv *priv)
  215. {
  216. struct list_head *element;
  217. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  218. priv->frames_count);
  219. while (!list_empty(&priv->free_frames)) {
  220. element = priv->free_frames.next;
  221. list_del(element);
  222. kfree(list_entry(element, struct iwl_frame, list));
  223. priv->frames_count--;
  224. }
  225. if (priv->frames_count) {
  226. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  227. priv->frames_count);
  228. priv->frames_count = 0;
  229. }
  230. }
  231. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  232. {
  233. struct iwl_frame *frame;
  234. struct list_head *element;
  235. if (list_empty(&priv->free_frames)) {
  236. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  237. if (!frame) {
  238. IWL_ERR(priv, "Could not allocate frame!\n");
  239. return NULL;
  240. }
  241. priv->frames_count++;
  242. return frame;
  243. }
  244. element = priv->free_frames.next;
  245. list_del(element);
  246. return list_entry(element, struct iwl_frame, list);
  247. }
  248. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  249. {
  250. memset(frame, 0, sizeof(*frame));
  251. list_add(&frame->list, &priv->free_frames);
  252. }
  253. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  254. struct ieee80211_hdr *hdr,
  255. int left)
  256. {
  257. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  258. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  259. (priv->iw_mode != NL80211_IFTYPE_AP)))
  260. return 0;
  261. if (priv->ibss_beacon->len > left)
  262. return 0;
  263. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  264. return priv->ibss_beacon->len;
  265. }
  266. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  267. struct iwl_frame *frame, u8 rate)
  268. {
  269. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  270. unsigned int frame_size;
  271. tx_beacon_cmd = &frame->u.beacon;
  272. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  273. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  274. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  275. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  276. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  277. BUG_ON(frame_size > MAX_MPDU_SIZE);
  278. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  279. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  280. tx_beacon_cmd->tx.rate_n_flags =
  281. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  282. else
  283. tx_beacon_cmd->tx.rate_n_flags =
  284. iwl_hw_set_rate_n_flags(rate, 0);
  285. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  286. TX_CMD_FLG_TSF_MSK |
  287. TX_CMD_FLG_STA_RATE_MSK;
  288. return sizeof(*tx_beacon_cmd) + frame_size;
  289. }
  290. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  291. {
  292. struct iwl_frame *frame;
  293. unsigned int frame_size;
  294. int rc;
  295. u8 rate;
  296. frame = iwl_get_free_frame(priv);
  297. if (!frame) {
  298. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  299. "command.\n");
  300. return -ENOMEM;
  301. }
  302. rate = iwl_rate_get_lowest_plcp(priv);
  303. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  304. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  305. &frame->u.cmd[0]);
  306. iwl_free_frame(priv, frame);
  307. return rc;
  308. }
  309. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  310. {
  311. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  312. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  313. if (sizeof(dma_addr_t) > sizeof(u32))
  314. addr |=
  315. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  316. return addr;
  317. }
  318. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  319. {
  320. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  321. return le16_to_cpu(tb->hi_n_len) >> 4;
  322. }
  323. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  324. dma_addr_t addr, u16 len)
  325. {
  326. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  327. u16 hi_n_len = len << 4;
  328. put_unaligned_le32(addr, &tb->lo);
  329. if (sizeof(dma_addr_t) > sizeof(u32))
  330. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  331. tb->hi_n_len = cpu_to_le16(hi_n_len);
  332. tfd->num_tbs = idx + 1;
  333. }
  334. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  335. {
  336. return tfd->num_tbs & 0x1f;
  337. }
  338. /**
  339. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  340. * @priv - driver private data
  341. * @txq - tx queue
  342. *
  343. * Does NOT advance any TFD circular buffer read/write indexes
  344. * Does NOT free the TFD itself (which is within circular buffer)
  345. */
  346. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  347. {
  348. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  349. struct iwl_tfd *tfd;
  350. struct pci_dev *dev = priv->pci_dev;
  351. int index = txq->q.read_ptr;
  352. int i;
  353. int num_tbs;
  354. tfd = &tfd_tmp[index];
  355. /* Sanity check on number of chunks */
  356. num_tbs = iwl_tfd_get_num_tbs(tfd);
  357. if (num_tbs >= IWL_NUM_OF_TBS) {
  358. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  359. /* @todo issue fatal error, it is quite serious situation */
  360. return;
  361. }
  362. /* Unmap tx_cmd */
  363. if (num_tbs)
  364. pci_unmap_single(dev,
  365. pci_unmap_addr(&txq->meta[index], mapping),
  366. pci_unmap_len(&txq->meta[index], len),
  367. PCI_DMA_BIDIRECTIONAL);
  368. /* Unmap chunks, if any. */
  369. for (i = 1; i < num_tbs; i++) {
  370. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  371. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  372. if (txq->txb) {
  373. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  374. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  375. }
  376. }
  377. }
  378. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  379. struct iwl_tx_queue *txq,
  380. dma_addr_t addr, u16 len,
  381. u8 reset, u8 pad)
  382. {
  383. struct iwl_queue *q;
  384. struct iwl_tfd *tfd, *tfd_tmp;
  385. u32 num_tbs;
  386. q = &txq->q;
  387. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  388. tfd = &tfd_tmp[q->write_ptr];
  389. if (reset)
  390. memset(tfd, 0, sizeof(*tfd));
  391. num_tbs = iwl_tfd_get_num_tbs(tfd);
  392. /* Each TFD can point to a maximum 20 Tx buffers */
  393. if (num_tbs >= IWL_NUM_OF_TBS) {
  394. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  395. IWL_NUM_OF_TBS);
  396. return -EINVAL;
  397. }
  398. BUG_ON(addr & ~DMA_BIT_MASK(36));
  399. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  400. IWL_ERR(priv, "Unaligned address = %llx\n",
  401. (unsigned long long)addr);
  402. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  403. return 0;
  404. }
  405. /*
  406. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  407. * given Tx queue, and enable the DMA channel used for that queue.
  408. *
  409. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  410. * channels supported in hardware.
  411. */
  412. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  413. struct iwl_tx_queue *txq)
  414. {
  415. int txq_id = txq->q.id;
  416. /* Circular buffer (TFD queue in DRAM) physical base address */
  417. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  418. txq->q.dma_addr >> 8);
  419. return 0;
  420. }
  421. /******************************************************************************
  422. *
  423. * Generic RX handler implementations
  424. *
  425. ******************************************************************************/
  426. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  427. struct iwl_rx_mem_buffer *rxb)
  428. {
  429. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  430. struct iwl_alive_resp *palive;
  431. struct delayed_work *pwork;
  432. palive = &pkt->u.alive_frame;
  433. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  434. "0x%01X 0x%01X\n",
  435. palive->is_valid, palive->ver_type,
  436. palive->ver_subtype);
  437. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  438. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  439. memcpy(&priv->card_alive_init,
  440. &pkt->u.alive_frame,
  441. sizeof(struct iwl_init_alive_resp));
  442. pwork = &priv->init_alive_start;
  443. } else {
  444. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  445. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  446. sizeof(struct iwl_alive_resp));
  447. pwork = &priv->alive_start;
  448. }
  449. /* We delay the ALIVE response by 5ms to
  450. * give the HW RF Kill time to activate... */
  451. if (palive->is_valid == UCODE_VALID_OK)
  452. queue_delayed_work(priv->workqueue, pwork,
  453. msecs_to_jiffies(5));
  454. else
  455. IWL_WARN(priv, "uCode did not respond OK.\n");
  456. }
  457. static void iwl_bg_beacon_update(struct work_struct *work)
  458. {
  459. struct iwl_priv *priv =
  460. container_of(work, struct iwl_priv, beacon_update);
  461. struct sk_buff *beacon;
  462. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  463. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  464. if (!beacon) {
  465. IWL_ERR(priv, "update beacon failed\n");
  466. return;
  467. }
  468. mutex_lock(&priv->mutex);
  469. /* new beacon skb is allocated every time; dispose previous.*/
  470. if (priv->ibss_beacon)
  471. dev_kfree_skb(priv->ibss_beacon);
  472. priv->ibss_beacon = beacon;
  473. mutex_unlock(&priv->mutex);
  474. iwl_send_beacon_cmd(priv);
  475. }
  476. /**
  477. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  478. *
  479. * This callback is provided in order to send a statistics request.
  480. *
  481. * This timer function is continually reset to execute within
  482. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  483. * was received. We need to ensure we receive the statistics in order
  484. * to update the temperature used for calibrating the TXPOWER.
  485. */
  486. static void iwl_bg_statistics_periodic(unsigned long data)
  487. {
  488. struct iwl_priv *priv = (struct iwl_priv *)data;
  489. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  490. return;
  491. /* dont send host command if rf-kill is on */
  492. if (!iwl_is_ready_rf(priv))
  493. return;
  494. iwl_send_statistics_request(priv, CMD_ASYNC);
  495. }
  496. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  497. struct iwl_rx_mem_buffer *rxb)
  498. {
  499. #ifdef CONFIG_IWLWIFI_DEBUG
  500. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  501. struct iwl4965_beacon_notif *beacon =
  502. (struct iwl4965_beacon_notif *)pkt->u.raw;
  503. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  504. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  505. "tsf %d %d rate %d\n",
  506. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  507. beacon->beacon_notify_hdr.failure_frame,
  508. le32_to_cpu(beacon->ibss_mgr_status),
  509. le32_to_cpu(beacon->high_tsf),
  510. le32_to_cpu(beacon->low_tsf), rate);
  511. #endif
  512. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  513. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  514. queue_work(priv->workqueue, &priv->beacon_update);
  515. }
  516. /* Handle notification from uCode that card's power state is changing
  517. * due to software, hardware, or critical temperature RFKILL */
  518. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  519. struct iwl_rx_mem_buffer *rxb)
  520. {
  521. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  522. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  523. unsigned long status = priv->status;
  524. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  525. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  526. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  527. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  528. RF_CARD_DISABLED)) {
  529. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  530. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  531. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  532. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  533. if (!(flags & RXON_CARD_DISABLED)) {
  534. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  535. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  536. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  537. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  538. }
  539. if (flags & RF_CARD_DISABLED)
  540. iwl_tt_enter_ct_kill(priv);
  541. }
  542. if (!(flags & RF_CARD_DISABLED))
  543. iwl_tt_exit_ct_kill(priv);
  544. if (flags & HW_CARD_DISABLED)
  545. set_bit(STATUS_RF_KILL_HW, &priv->status);
  546. else
  547. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  548. if (!(flags & RXON_CARD_DISABLED))
  549. iwl_scan_cancel(priv);
  550. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  551. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  552. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  553. test_bit(STATUS_RF_KILL_HW, &priv->status));
  554. else
  555. wake_up_interruptible(&priv->wait_command_queue);
  556. }
  557. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  558. {
  559. if (src == IWL_PWR_SRC_VAUX) {
  560. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  561. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  562. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  563. ~APMG_PS_CTRL_MSK_PWR_SRC);
  564. } else {
  565. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  566. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  567. ~APMG_PS_CTRL_MSK_PWR_SRC);
  568. }
  569. return 0;
  570. }
  571. /**
  572. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  573. *
  574. * Setup the RX handlers for each of the reply types sent from the uCode
  575. * to the host.
  576. *
  577. * This function chains into the hardware specific files for them to setup
  578. * any hardware specific handlers as well.
  579. */
  580. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  581. {
  582. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  583. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  584. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  585. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  586. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  587. iwl_rx_pm_debug_statistics_notif;
  588. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  589. /*
  590. * The same handler is used for both the REPLY to a discrete
  591. * statistics request from the host as well as for the periodic
  592. * statistics notifications (after received beacons) from the uCode.
  593. */
  594. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  595. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  596. iwl_setup_spectrum_handlers(priv);
  597. iwl_setup_rx_scan_handlers(priv);
  598. /* status change handler */
  599. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  600. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  601. iwl_rx_missed_beacon_notif;
  602. /* Rx handlers */
  603. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  604. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  605. /* block ack */
  606. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  607. /* Set up hardware specific Rx handlers */
  608. priv->cfg->ops->lib->rx_handler_setup(priv);
  609. }
  610. /**
  611. * iwl_rx_handle - Main entry function for receiving responses from uCode
  612. *
  613. * Uses the priv->rx_handlers callback function array to invoke
  614. * the appropriate handlers, including command responses,
  615. * frame-received notifications, and other notifications.
  616. */
  617. void iwl_rx_handle(struct iwl_priv *priv)
  618. {
  619. struct iwl_rx_mem_buffer *rxb;
  620. struct iwl_rx_packet *pkt;
  621. struct iwl_rx_queue *rxq = &priv->rxq;
  622. u32 r, i;
  623. int reclaim;
  624. unsigned long flags;
  625. u8 fill_rx = 0;
  626. u32 count = 8;
  627. int total_empty;
  628. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  629. * buffer that the driver may process (last buffer filled by ucode). */
  630. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  631. i = rxq->read;
  632. /* Rx interrupt, but nothing sent from uCode */
  633. if (i == r)
  634. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  635. /* calculate total frames need to be restock after handling RX */
  636. total_empty = r - priv->rxq.write_actual;
  637. if (total_empty < 0)
  638. total_empty += RX_QUEUE_SIZE;
  639. if (total_empty > (RX_QUEUE_SIZE / 2))
  640. fill_rx = 1;
  641. while (i != r) {
  642. rxb = rxq->queue[i];
  643. /* If an RXB doesn't have a Rx queue slot associated with it,
  644. * then a bug has been introduced in the queue refilling
  645. * routines -- catch it here */
  646. BUG_ON(rxb == NULL);
  647. rxq->queue[i] = NULL;
  648. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  649. priv->hw_params.rx_buf_size + 256,
  650. PCI_DMA_FROMDEVICE);
  651. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  652. /* Reclaim a command buffer only if this packet is a response
  653. * to a (driver-originated) command.
  654. * If the packet (e.g. Rx frame) originated from uCode,
  655. * there is no command buffer to reclaim.
  656. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  657. * but apparently a few don't get set; catch them here. */
  658. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  659. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  660. (pkt->hdr.cmd != REPLY_RX) &&
  661. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  662. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  663. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  664. (pkt->hdr.cmd != REPLY_TX);
  665. /* Based on type of command response or notification,
  666. * handle those that need handling via function in
  667. * rx_handlers table. See iwl_setup_rx_handlers() */
  668. if (priv->rx_handlers[pkt->hdr.cmd]) {
  669. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  670. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  671. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  672. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  673. } else {
  674. /* No handling needed */
  675. IWL_DEBUG_RX(priv,
  676. "r %d i %d No handler needed for %s, 0x%02x\n",
  677. r, i, get_cmd_string(pkt->hdr.cmd),
  678. pkt->hdr.cmd);
  679. }
  680. if (reclaim) {
  681. /* Invoke any callbacks, transfer the skb to caller, and
  682. * fire off the (possibly) blocking iwl_send_cmd()
  683. * as we reclaim the driver command queue */
  684. if (rxb && rxb->skb)
  685. iwl_tx_cmd_complete(priv, rxb);
  686. else
  687. IWL_WARN(priv, "Claim null rxb?\n");
  688. }
  689. /* For now we just don't re-use anything. We can tweak this
  690. * later to try and re-use notification packets and SKBs that
  691. * fail to Rx correctly */
  692. if (rxb->skb != NULL) {
  693. priv->alloc_rxb_skb--;
  694. dev_kfree_skb_any(rxb->skb);
  695. rxb->skb = NULL;
  696. }
  697. spin_lock_irqsave(&rxq->lock, flags);
  698. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  699. spin_unlock_irqrestore(&rxq->lock, flags);
  700. i = (i + 1) & RX_QUEUE_MASK;
  701. /* If there are a lot of unused frames,
  702. * restock the Rx queue so ucode wont assert. */
  703. if (fill_rx) {
  704. count++;
  705. if (count >= 8) {
  706. priv->rxq.read = i;
  707. iwl_rx_replenish_now(priv);
  708. count = 0;
  709. }
  710. }
  711. }
  712. /* Backtrack one entry */
  713. priv->rxq.read = i;
  714. if (fill_rx)
  715. iwl_rx_replenish_now(priv);
  716. else
  717. iwl_rx_queue_restock(priv);
  718. }
  719. /* call this function to flush any scheduled tasklet */
  720. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  721. {
  722. /* wait to make sure we flush pending tasklet*/
  723. synchronize_irq(priv->pci_dev->irq);
  724. tasklet_kill(&priv->irq_tasklet);
  725. }
  726. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  727. {
  728. u32 inta, handled = 0;
  729. u32 inta_fh;
  730. unsigned long flags;
  731. #ifdef CONFIG_IWLWIFI_DEBUG
  732. u32 inta_mask;
  733. #endif
  734. spin_lock_irqsave(&priv->lock, flags);
  735. /* Ack/clear/reset pending uCode interrupts.
  736. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  737. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  738. inta = iwl_read32(priv, CSR_INT);
  739. iwl_write32(priv, CSR_INT, inta);
  740. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  741. * Any new interrupts that happen after this, either while we're
  742. * in this tasklet, or later, will show up in next ISR/tasklet. */
  743. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  744. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  745. #ifdef CONFIG_IWLWIFI_DEBUG
  746. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  747. /* just for debug */
  748. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  749. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  750. inta, inta_mask, inta_fh);
  751. }
  752. #endif
  753. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  754. * atomic, make sure that inta covers all the interrupts that
  755. * we've discovered, even if FH interrupt came in just after
  756. * reading CSR_INT. */
  757. if (inta_fh & CSR49_FH_INT_RX_MASK)
  758. inta |= CSR_INT_BIT_FH_RX;
  759. if (inta_fh & CSR49_FH_INT_TX_MASK)
  760. inta |= CSR_INT_BIT_FH_TX;
  761. /* Now service all interrupt bits discovered above. */
  762. if (inta & CSR_INT_BIT_HW_ERR) {
  763. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  764. /* Tell the device to stop sending interrupts */
  765. iwl_disable_interrupts(priv);
  766. priv->isr_stats.hw++;
  767. iwl_irq_handle_error(priv);
  768. handled |= CSR_INT_BIT_HW_ERR;
  769. spin_unlock_irqrestore(&priv->lock, flags);
  770. return;
  771. }
  772. #ifdef CONFIG_IWLWIFI_DEBUG
  773. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  774. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  775. if (inta & CSR_INT_BIT_SCD) {
  776. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  777. "the frame/frames.\n");
  778. priv->isr_stats.sch++;
  779. }
  780. /* Alive notification via Rx interrupt will do the real work */
  781. if (inta & CSR_INT_BIT_ALIVE) {
  782. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  783. priv->isr_stats.alive++;
  784. }
  785. }
  786. #endif
  787. /* Safely ignore these bits for debug checks below */
  788. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  789. /* HW RF KILL switch toggled */
  790. if (inta & CSR_INT_BIT_RF_KILL) {
  791. int hw_rf_kill = 0;
  792. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  793. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  794. hw_rf_kill = 1;
  795. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  796. hw_rf_kill ? "disable radio" : "enable radio");
  797. priv->isr_stats.rfkill++;
  798. /* driver only loads ucode once setting the interface up.
  799. * the driver allows loading the ucode even if the radio
  800. * is killed. Hence update the killswitch state here. The
  801. * rfkill handler will care about restarting if needed.
  802. */
  803. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  804. if (hw_rf_kill)
  805. set_bit(STATUS_RF_KILL_HW, &priv->status);
  806. else
  807. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  808. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  809. }
  810. handled |= CSR_INT_BIT_RF_KILL;
  811. }
  812. /* Chip got too hot and stopped itself */
  813. if (inta & CSR_INT_BIT_CT_KILL) {
  814. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  815. priv->isr_stats.ctkill++;
  816. handled |= CSR_INT_BIT_CT_KILL;
  817. }
  818. /* Error detected by uCode */
  819. if (inta & CSR_INT_BIT_SW_ERR) {
  820. IWL_ERR(priv, "Microcode SW error detected. "
  821. " Restarting 0x%X.\n", inta);
  822. priv->isr_stats.sw++;
  823. priv->isr_stats.sw_err = inta;
  824. iwl_irq_handle_error(priv);
  825. handled |= CSR_INT_BIT_SW_ERR;
  826. }
  827. /* uCode wakes up after power-down sleep */
  828. if (inta & CSR_INT_BIT_WAKEUP) {
  829. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  830. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  831. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  832. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  833. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  834. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  835. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  836. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  837. priv->isr_stats.wakeup++;
  838. handled |= CSR_INT_BIT_WAKEUP;
  839. }
  840. /* All uCode command responses, including Tx command responses,
  841. * Rx "responses" (frame-received notification), and other
  842. * notifications from uCode come through here*/
  843. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  844. iwl_rx_handle(priv);
  845. priv->isr_stats.rx++;
  846. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  847. }
  848. if (inta & CSR_INT_BIT_FH_TX) {
  849. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  850. priv->isr_stats.tx++;
  851. handled |= CSR_INT_BIT_FH_TX;
  852. /* FH finished to write, send event */
  853. priv->ucode_write_complete = 1;
  854. wake_up_interruptible(&priv->wait_command_queue);
  855. }
  856. if (inta & ~handled) {
  857. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  858. priv->isr_stats.unhandled++;
  859. }
  860. if (inta & ~(priv->inta_mask)) {
  861. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  862. inta & ~priv->inta_mask);
  863. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  864. }
  865. /* Re-enable all interrupts */
  866. /* only Re-enable if diabled by irq */
  867. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  868. iwl_enable_interrupts(priv);
  869. #ifdef CONFIG_IWLWIFI_DEBUG
  870. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  871. inta = iwl_read32(priv, CSR_INT);
  872. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  873. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  874. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  875. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  876. }
  877. #endif
  878. spin_unlock_irqrestore(&priv->lock, flags);
  879. }
  880. /* tasklet for iwlagn interrupt */
  881. static void iwl_irq_tasklet(struct iwl_priv *priv)
  882. {
  883. u32 inta = 0;
  884. u32 handled = 0;
  885. unsigned long flags;
  886. #ifdef CONFIG_IWLWIFI_DEBUG
  887. u32 inta_mask;
  888. #endif
  889. spin_lock_irqsave(&priv->lock, flags);
  890. /* Ack/clear/reset pending uCode interrupts.
  891. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  892. */
  893. iwl_write32(priv, CSR_INT, priv->inta);
  894. inta = priv->inta;
  895. #ifdef CONFIG_IWLWIFI_DEBUG
  896. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  897. /* just for debug */
  898. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  899. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  900. inta, inta_mask);
  901. }
  902. #endif
  903. /* saved interrupt in inta variable now we can reset priv->inta */
  904. priv->inta = 0;
  905. /* Now service all interrupt bits discovered above. */
  906. if (inta & CSR_INT_BIT_HW_ERR) {
  907. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  908. /* Tell the device to stop sending interrupts */
  909. iwl_disable_interrupts(priv);
  910. priv->isr_stats.hw++;
  911. iwl_irq_handle_error(priv);
  912. handled |= CSR_INT_BIT_HW_ERR;
  913. spin_unlock_irqrestore(&priv->lock, flags);
  914. return;
  915. }
  916. #ifdef CONFIG_IWLWIFI_DEBUG
  917. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  918. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  919. if (inta & CSR_INT_BIT_SCD) {
  920. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  921. "the frame/frames.\n");
  922. priv->isr_stats.sch++;
  923. }
  924. /* Alive notification via Rx interrupt will do the real work */
  925. if (inta & CSR_INT_BIT_ALIVE) {
  926. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  927. priv->isr_stats.alive++;
  928. }
  929. }
  930. #endif
  931. /* Safely ignore these bits for debug checks below */
  932. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  933. /* HW RF KILL switch toggled */
  934. if (inta & CSR_INT_BIT_RF_KILL) {
  935. int hw_rf_kill = 0;
  936. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  937. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  938. hw_rf_kill = 1;
  939. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  940. hw_rf_kill ? "disable radio" : "enable radio");
  941. priv->isr_stats.rfkill++;
  942. /* driver only loads ucode once setting the interface up.
  943. * the driver allows loading the ucode even if the radio
  944. * is killed. Hence update the killswitch state here. The
  945. * rfkill handler will care about restarting if needed.
  946. */
  947. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  948. if (hw_rf_kill)
  949. set_bit(STATUS_RF_KILL_HW, &priv->status);
  950. else
  951. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  952. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  953. }
  954. handled |= CSR_INT_BIT_RF_KILL;
  955. }
  956. /* Chip got too hot and stopped itself */
  957. if (inta & CSR_INT_BIT_CT_KILL) {
  958. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  959. priv->isr_stats.ctkill++;
  960. handled |= CSR_INT_BIT_CT_KILL;
  961. }
  962. /* Error detected by uCode */
  963. if (inta & CSR_INT_BIT_SW_ERR) {
  964. IWL_ERR(priv, "Microcode SW error detected. "
  965. " Restarting 0x%X.\n", inta);
  966. priv->isr_stats.sw++;
  967. priv->isr_stats.sw_err = inta;
  968. iwl_irq_handle_error(priv);
  969. handled |= CSR_INT_BIT_SW_ERR;
  970. }
  971. /* uCode wakes up after power-down sleep */
  972. if (inta & CSR_INT_BIT_WAKEUP) {
  973. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  974. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  975. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  976. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  977. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  978. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  979. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  980. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  981. priv->isr_stats.wakeup++;
  982. handled |= CSR_INT_BIT_WAKEUP;
  983. }
  984. /* All uCode command responses, including Tx command responses,
  985. * Rx "responses" (frame-received notification), and other
  986. * notifications from uCode come through here*/
  987. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  988. CSR_INT_BIT_RX_PERIODIC)) {
  989. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  990. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  991. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  992. iwl_write32(priv, CSR_FH_INT_STATUS,
  993. CSR49_FH_INT_RX_MASK);
  994. }
  995. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  996. handled |= CSR_INT_BIT_RX_PERIODIC;
  997. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  998. }
  999. /* Sending RX interrupt require many steps to be done in the
  1000. * the device:
  1001. * 1- write interrupt to current index in ICT table.
  1002. * 2- dma RX frame.
  1003. * 3- update RX shared data to indicate last write index.
  1004. * 4- send interrupt.
  1005. * This could lead to RX race, driver could receive RX interrupt
  1006. * but the shared data changes does not reflect this.
  1007. * this could lead to RX race, RX periodic will solve this race
  1008. */
  1009. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1010. CSR_INT_PERIODIC_DIS);
  1011. iwl_rx_handle(priv);
  1012. /* Only set RX periodic if real RX is received. */
  1013. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1014. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1015. CSR_INT_PERIODIC_ENA);
  1016. priv->isr_stats.rx++;
  1017. }
  1018. if (inta & CSR_INT_BIT_FH_TX) {
  1019. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1020. IWL_DEBUG_ISR(priv, "Tx interrupt\n");
  1021. priv->isr_stats.tx++;
  1022. handled |= CSR_INT_BIT_FH_TX;
  1023. /* FH finished to write, send event */
  1024. priv->ucode_write_complete = 1;
  1025. wake_up_interruptible(&priv->wait_command_queue);
  1026. }
  1027. if (inta & ~handled) {
  1028. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1029. priv->isr_stats.unhandled++;
  1030. }
  1031. if (inta & ~(priv->inta_mask)) {
  1032. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1033. inta & ~priv->inta_mask);
  1034. }
  1035. /* Re-enable all interrupts */
  1036. /* only Re-enable if diabled by irq */
  1037. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1038. iwl_enable_interrupts(priv);
  1039. spin_unlock_irqrestore(&priv->lock, flags);
  1040. }
  1041. /******************************************************************************
  1042. *
  1043. * uCode download functions
  1044. *
  1045. ******************************************************************************/
  1046. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1047. {
  1048. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1049. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1050. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1051. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1052. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1053. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1054. }
  1055. static void iwl_nic_start(struct iwl_priv *priv)
  1056. {
  1057. /* Remove all resets to allow NIC to operate */
  1058. iwl_write32(priv, CSR_RESET, 0);
  1059. }
  1060. /**
  1061. * iwl_read_ucode - Read uCode images from disk file.
  1062. *
  1063. * Copy into buffers for card to fetch via bus-mastering
  1064. */
  1065. static int iwl_read_ucode(struct iwl_priv *priv)
  1066. {
  1067. struct iwl_ucode_header *ucode;
  1068. int ret = -EINVAL, index;
  1069. const struct firmware *ucode_raw;
  1070. const char *name_pre = priv->cfg->fw_name_pre;
  1071. const unsigned int api_max = priv->cfg->ucode_api_max;
  1072. const unsigned int api_min = priv->cfg->ucode_api_min;
  1073. char buf[25];
  1074. u8 *src;
  1075. size_t len;
  1076. u32 api_ver, build;
  1077. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1078. u16 eeprom_ver;
  1079. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1080. * request_firmware() is synchronous, file is in memory on return. */
  1081. for (index = api_max; index >= api_min; index--) {
  1082. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1083. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1084. if (ret < 0) {
  1085. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1086. buf, ret);
  1087. if (ret == -ENOENT)
  1088. continue;
  1089. else
  1090. goto error;
  1091. } else {
  1092. if (index < api_max)
  1093. IWL_ERR(priv, "Loaded firmware %s, "
  1094. "which is deprecated. "
  1095. "Please use API v%u instead.\n",
  1096. buf, api_max);
  1097. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1098. buf, ucode_raw->size);
  1099. break;
  1100. }
  1101. }
  1102. if (ret < 0)
  1103. goto error;
  1104. /* Make sure that we got at least the v1 header! */
  1105. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1106. IWL_ERR(priv, "File size way too small!\n");
  1107. ret = -EINVAL;
  1108. goto err_release;
  1109. }
  1110. /* Data from ucode file: header followed by uCode images */
  1111. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1112. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1113. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1114. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1115. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1116. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1117. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1118. init_data_size =
  1119. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1120. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1121. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1122. /* api_ver should match the api version forming part of the
  1123. * firmware filename ... but we don't check for that and only rely
  1124. * on the API version read from firmware header from here on forward */
  1125. if (api_ver < api_min || api_ver > api_max) {
  1126. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1127. "Driver supports v%u, firmware is v%u.\n",
  1128. api_max, api_ver);
  1129. priv->ucode_ver = 0;
  1130. ret = -EINVAL;
  1131. goto err_release;
  1132. }
  1133. if (api_ver != api_max)
  1134. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1135. "got v%u. New firmware can be obtained "
  1136. "from http://www.intellinuxwireless.org.\n",
  1137. api_max, api_ver);
  1138. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1139. IWL_UCODE_MAJOR(priv->ucode_ver),
  1140. IWL_UCODE_MINOR(priv->ucode_ver),
  1141. IWL_UCODE_API(priv->ucode_ver),
  1142. IWL_UCODE_SERIAL(priv->ucode_ver));
  1143. if (build)
  1144. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1145. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1146. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1147. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1148. ? "OTP" : "EEPROM", eeprom_ver);
  1149. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1150. priv->ucode_ver);
  1151. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1152. inst_size);
  1153. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1154. data_size);
  1155. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1156. init_size);
  1157. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1158. init_data_size);
  1159. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1160. boot_size);
  1161. /* Verify size of file vs. image size info in file's header */
  1162. if (ucode_raw->size !=
  1163. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1164. inst_size + data_size + init_size +
  1165. init_data_size + boot_size) {
  1166. IWL_DEBUG_INFO(priv,
  1167. "uCode file size %d does not match expected size\n",
  1168. (int)ucode_raw->size);
  1169. ret = -EINVAL;
  1170. goto err_release;
  1171. }
  1172. /* Verify that uCode images will fit in card's SRAM */
  1173. if (inst_size > priv->hw_params.max_inst_size) {
  1174. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1175. inst_size);
  1176. ret = -EINVAL;
  1177. goto err_release;
  1178. }
  1179. if (data_size > priv->hw_params.max_data_size) {
  1180. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1181. data_size);
  1182. ret = -EINVAL;
  1183. goto err_release;
  1184. }
  1185. if (init_size > priv->hw_params.max_inst_size) {
  1186. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1187. init_size);
  1188. ret = -EINVAL;
  1189. goto err_release;
  1190. }
  1191. if (init_data_size > priv->hw_params.max_data_size) {
  1192. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1193. init_data_size);
  1194. ret = -EINVAL;
  1195. goto err_release;
  1196. }
  1197. if (boot_size > priv->hw_params.max_bsm_size) {
  1198. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1199. boot_size);
  1200. ret = -EINVAL;
  1201. goto err_release;
  1202. }
  1203. /* Allocate ucode buffers for card's bus-master loading ... */
  1204. /* Runtime instructions and 2 copies of data:
  1205. * 1) unmodified from disk
  1206. * 2) backup cache for save/restore during power-downs */
  1207. priv->ucode_code.len = inst_size;
  1208. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1209. priv->ucode_data.len = data_size;
  1210. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1211. priv->ucode_data_backup.len = data_size;
  1212. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1213. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1214. !priv->ucode_data_backup.v_addr)
  1215. goto err_pci_alloc;
  1216. /* Initialization instructions and data */
  1217. if (init_size && init_data_size) {
  1218. priv->ucode_init.len = init_size;
  1219. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1220. priv->ucode_init_data.len = init_data_size;
  1221. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1222. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1223. goto err_pci_alloc;
  1224. }
  1225. /* Bootstrap (instructions only, no data) */
  1226. if (boot_size) {
  1227. priv->ucode_boot.len = boot_size;
  1228. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1229. if (!priv->ucode_boot.v_addr)
  1230. goto err_pci_alloc;
  1231. }
  1232. /* Copy images into buffers for card's bus-master reads ... */
  1233. /* Runtime instructions (first block of data in file) */
  1234. len = inst_size;
  1235. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1236. memcpy(priv->ucode_code.v_addr, src, len);
  1237. src += len;
  1238. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1239. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1240. /* Runtime data (2nd block)
  1241. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1242. len = data_size;
  1243. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1244. memcpy(priv->ucode_data.v_addr, src, len);
  1245. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1246. src += len;
  1247. /* Initialization instructions (3rd block) */
  1248. if (init_size) {
  1249. len = init_size;
  1250. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1251. len);
  1252. memcpy(priv->ucode_init.v_addr, src, len);
  1253. src += len;
  1254. }
  1255. /* Initialization data (4th block) */
  1256. if (init_data_size) {
  1257. len = init_data_size;
  1258. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1259. len);
  1260. memcpy(priv->ucode_init_data.v_addr, src, len);
  1261. src += len;
  1262. }
  1263. /* Bootstrap instructions (5th block) */
  1264. len = boot_size;
  1265. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1266. memcpy(priv->ucode_boot.v_addr, src, len);
  1267. /* We have our copies now, allow OS release its copies */
  1268. release_firmware(ucode_raw);
  1269. return 0;
  1270. err_pci_alloc:
  1271. IWL_ERR(priv, "failed to allocate pci memory\n");
  1272. ret = -ENOMEM;
  1273. iwl_dealloc_ucode_pci(priv);
  1274. err_release:
  1275. release_firmware(ucode_raw);
  1276. error:
  1277. return ret;
  1278. }
  1279. #ifdef CONFIG_IWLWIFI_DEBUG
  1280. static const char *desc_lookup_text[] = {
  1281. "OK",
  1282. "FAIL",
  1283. "BAD_PARAM",
  1284. "BAD_CHECKSUM",
  1285. "NMI_INTERRUPT_WDG",
  1286. "SYSASSERT",
  1287. "FATAL_ERROR",
  1288. "BAD_COMMAND",
  1289. "HW_ERROR_TUNE_LOCK",
  1290. "HW_ERROR_TEMPERATURE",
  1291. "ILLEGAL_CHAN_FREQ",
  1292. "VCC_NOT_STABLE",
  1293. "FH_ERROR",
  1294. "NMI_INTERRUPT_HOST",
  1295. "NMI_INTERRUPT_ACTION_PT",
  1296. "NMI_INTERRUPT_UNKNOWN",
  1297. "UCODE_VERSION_MISMATCH",
  1298. "HW_ERROR_ABS_LOCK",
  1299. "HW_ERROR_CAL_LOCK_FAIL",
  1300. "NMI_INTERRUPT_INST_ACTION_PT",
  1301. "NMI_INTERRUPT_DATA_ACTION_PT",
  1302. "NMI_TRM_HW_ER",
  1303. "NMI_INTERRUPT_TRM",
  1304. "NMI_INTERRUPT_BREAK_POINT"
  1305. "DEBUG_0",
  1306. "DEBUG_1",
  1307. "DEBUG_2",
  1308. "DEBUG_3",
  1309. "UNKNOWN"
  1310. };
  1311. static const char *desc_lookup(int i)
  1312. {
  1313. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1314. if (i < 0 || i > max)
  1315. i = max;
  1316. return desc_lookup_text[i];
  1317. }
  1318. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1319. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1320. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1321. {
  1322. u32 data2, line;
  1323. u32 desc, time, count, base, data1;
  1324. u32 blink1, blink2, ilink1, ilink2;
  1325. if (priv->ucode_type == UCODE_INIT)
  1326. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1327. else
  1328. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1329. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1330. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1331. return;
  1332. }
  1333. count = iwl_read_targ_mem(priv, base);
  1334. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1335. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1336. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1337. priv->status, count);
  1338. }
  1339. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1340. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1341. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1342. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1343. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1344. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1345. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1346. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1347. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1348. IWL_ERR(priv, "Desc Time "
  1349. "data1 data2 line\n");
  1350. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1351. desc_lookup(desc), desc, time, data1, data2, line);
  1352. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1353. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1354. ilink1, ilink2);
  1355. }
  1356. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1357. /**
  1358. * iwl_print_event_log - Dump error event log to syslog
  1359. *
  1360. */
  1361. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1362. u32 num_events, u32 mode)
  1363. {
  1364. u32 i;
  1365. u32 base; /* SRAM byte address of event log header */
  1366. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1367. u32 ptr; /* SRAM byte address of log data */
  1368. u32 ev, time, data; /* event log data */
  1369. if (num_events == 0)
  1370. return;
  1371. if (priv->ucode_type == UCODE_INIT)
  1372. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1373. else
  1374. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1375. if (mode == 0)
  1376. event_size = 2 * sizeof(u32);
  1377. else
  1378. event_size = 3 * sizeof(u32);
  1379. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1380. /* "time" is actually "data" for mode 0 (no timestamp).
  1381. * place event id # at far right for easier visual parsing. */
  1382. for (i = 0; i < num_events; i++) {
  1383. ev = iwl_read_targ_mem(priv, ptr);
  1384. ptr += sizeof(u32);
  1385. time = iwl_read_targ_mem(priv, ptr);
  1386. ptr += sizeof(u32);
  1387. if (mode == 0) {
  1388. /* data, ev */
  1389. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1390. } else {
  1391. data = iwl_read_targ_mem(priv, ptr);
  1392. ptr += sizeof(u32);
  1393. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1394. time, data, ev);
  1395. }
  1396. }
  1397. }
  1398. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1399. {
  1400. u32 base; /* SRAM byte address of event log header */
  1401. u32 capacity; /* event log capacity in # entries */
  1402. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1403. u32 num_wraps; /* # times uCode wrapped to top of log */
  1404. u32 next_entry; /* index of next entry to be written by uCode */
  1405. u32 size; /* # entries that we'll print */
  1406. if (priv->ucode_type == UCODE_INIT)
  1407. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1408. else
  1409. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1410. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1411. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1412. return;
  1413. }
  1414. /* event log header */
  1415. capacity = iwl_read_targ_mem(priv, base);
  1416. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1417. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1418. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1419. size = num_wraps ? capacity : next_entry;
  1420. /* bail out if nothing in log */
  1421. if (size == 0) {
  1422. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1423. return;
  1424. }
  1425. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1426. size, num_wraps);
  1427. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1428. * i.e the next one that uCode would fill. */
  1429. if (num_wraps)
  1430. iwl_print_event_log(priv, next_entry,
  1431. capacity - next_entry, mode);
  1432. /* (then/else) start at top of log */
  1433. iwl_print_event_log(priv, 0, next_entry, mode);
  1434. }
  1435. #endif
  1436. /**
  1437. * iwl_alive_start - called after REPLY_ALIVE notification received
  1438. * from protocol/runtime uCode (initialization uCode's
  1439. * Alive gets handled by iwl_init_alive_start()).
  1440. */
  1441. static void iwl_alive_start(struct iwl_priv *priv)
  1442. {
  1443. int ret = 0;
  1444. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1445. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1446. /* We had an error bringing up the hardware, so take it
  1447. * all the way back down so we can try again */
  1448. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1449. goto restart;
  1450. }
  1451. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1452. * This is a paranoid check, because we would not have gotten the
  1453. * "runtime" alive if code weren't properly loaded. */
  1454. if (iwl_verify_ucode(priv)) {
  1455. /* Runtime instruction load was bad;
  1456. * take it all the way back down so we can try again */
  1457. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1458. goto restart;
  1459. }
  1460. iwl_clear_stations_table(priv);
  1461. ret = priv->cfg->ops->lib->alive_notify(priv);
  1462. if (ret) {
  1463. IWL_WARN(priv,
  1464. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1465. goto restart;
  1466. }
  1467. /* After the ALIVE response, we can send host commands to the uCode */
  1468. set_bit(STATUS_ALIVE, &priv->status);
  1469. if (iwl_is_rfkill(priv))
  1470. return;
  1471. ieee80211_wake_queues(priv->hw);
  1472. priv->active_rate = priv->rates_mask;
  1473. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1474. if (iwl_is_associated(priv)) {
  1475. struct iwl_rxon_cmd *active_rxon =
  1476. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1477. /* apply any changes in staging */
  1478. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1479. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1480. } else {
  1481. /* Initialize our rx_config data */
  1482. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1483. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1484. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1485. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1486. }
  1487. /* Configure Bluetooth device coexistence support */
  1488. iwl_send_bt_config(priv);
  1489. iwl_reset_run_time_calib(priv);
  1490. /* Configure the adapter for unassociated operation */
  1491. iwlcore_commit_rxon(priv);
  1492. /* At this point, the NIC is initialized and operational */
  1493. iwl_rf_kill_ct_config(priv);
  1494. iwl_leds_register(priv);
  1495. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1496. set_bit(STATUS_READY, &priv->status);
  1497. wake_up_interruptible(&priv->wait_command_queue);
  1498. iwl_power_update_mode(priv, true);
  1499. /* reassociate for ADHOC mode */
  1500. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1501. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1502. priv->vif);
  1503. if (beacon)
  1504. iwl_mac_beacon_update(priv->hw, beacon);
  1505. }
  1506. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1507. iwl_set_mode(priv, priv->iw_mode);
  1508. return;
  1509. restart:
  1510. queue_work(priv->workqueue, &priv->restart);
  1511. }
  1512. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1513. static void __iwl_down(struct iwl_priv *priv)
  1514. {
  1515. unsigned long flags;
  1516. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1517. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1518. if (!exit_pending)
  1519. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1520. iwl_leds_unregister(priv);
  1521. iwl_clear_stations_table(priv);
  1522. /* Unblock any waiting calls */
  1523. wake_up_interruptible_all(&priv->wait_command_queue);
  1524. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1525. * exiting the module */
  1526. if (!exit_pending)
  1527. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1528. /* stop and reset the on-board processor */
  1529. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1530. /* tell the device to stop sending interrupts */
  1531. spin_lock_irqsave(&priv->lock, flags);
  1532. iwl_disable_interrupts(priv);
  1533. spin_unlock_irqrestore(&priv->lock, flags);
  1534. iwl_synchronize_irq(priv);
  1535. if (priv->mac80211_registered)
  1536. ieee80211_stop_queues(priv->hw);
  1537. /* If we have not previously called iwl_init() then
  1538. * clear all bits but the RF Kill bit and return */
  1539. if (!iwl_is_init(priv)) {
  1540. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1541. STATUS_RF_KILL_HW |
  1542. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1543. STATUS_GEO_CONFIGURED |
  1544. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1545. STATUS_EXIT_PENDING;
  1546. goto exit;
  1547. }
  1548. /* ...otherwise clear out all the status bits but the RF Kill
  1549. * bit and continue taking the NIC down. */
  1550. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1551. STATUS_RF_KILL_HW |
  1552. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1553. STATUS_GEO_CONFIGURED |
  1554. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1555. STATUS_FW_ERROR |
  1556. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1557. STATUS_EXIT_PENDING;
  1558. /* device going down, Stop using ICT table */
  1559. iwl_disable_ict(priv);
  1560. spin_lock_irqsave(&priv->lock, flags);
  1561. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1562. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1563. spin_unlock_irqrestore(&priv->lock, flags);
  1564. iwl_txq_ctx_stop(priv);
  1565. iwl_rxq_stop(priv);
  1566. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1567. APMG_CLK_VAL_DMA_CLK_RQT);
  1568. udelay(5);
  1569. /* FIXME: apm_ops.suspend(priv) */
  1570. if (exit_pending)
  1571. priv->cfg->ops->lib->apm_ops.stop(priv);
  1572. else
  1573. priv->cfg->ops->lib->apm_ops.reset(priv);
  1574. exit:
  1575. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1576. if (priv->ibss_beacon)
  1577. dev_kfree_skb(priv->ibss_beacon);
  1578. priv->ibss_beacon = NULL;
  1579. /* clear out any free frames */
  1580. iwl_clear_free_frames(priv);
  1581. }
  1582. static void iwl_down(struct iwl_priv *priv)
  1583. {
  1584. mutex_lock(&priv->mutex);
  1585. __iwl_down(priv);
  1586. mutex_unlock(&priv->mutex);
  1587. iwl_cancel_deferred_work(priv);
  1588. }
  1589. #define HW_READY_TIMEOUT (50)
  1590. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1591. {
  1592. int ret = 0;
  1593. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1594. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1595. /* See if we got it */
  1596. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1597. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1598. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1599. HW_READY_TIMEOUT);
  1600. if (ret != -ETIMEDOUT)
  1601. priv->hw_ready = true;
  1602. else
  1603. priv->hw_ready = false;
  1604. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1605. (priv->hw_ready == 1) ? "ready" : "not ready");
  1606. return ret;
  1607. }
  1608. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1609. {
  1610. int ret = 0;
  1611. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1612. ret = iwl_set_hw_ready(priv);
  1613. if (priv->hw_ready)
  1614. return ret;
  1615. /* If HW is not ready, prepare the conditions to check again */
  1616. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1617. CSR_HW_IF_CONFIG_REG_PREPARE);
  1618. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1619. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1620. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1621. /* HW should be ready by now, check again. */
  1622. if (ret != -ETIMEDOUT)
  1623. iwl_set_hw_ready(priv);
  1624. return ret;
  1625. }
  1626. #define MAX_HW_RESTARTS 5
  1627. static int __iwl_up(struct iwl_priv *priv)
  1628. {
  1629. int i;
  1630. int ret;
  1631. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1632. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1633. return -EIO;
  1634. }
  1635. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1636. IWL_ERR(priv, "ucode not available for device bringup\n");
  1637. return -EIO;
  1638. }
  1639. iwl_prepare_card_hw(priv);
  1640. if (!priv->hw_ready) {
  1641. IWL_WARN(priv, "Exit HW not ready\n");
  1642. return -EIO;
  1643. }
  1644. /* If platform's RF_KILL switch is NOT set to KILL */
  1645. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1646. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1647. else
  1648. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1649. if (iwl_is_rfkill(priv)) {
  1650. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1651. iwl_enable_interrupts(priv);
  1652. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1653. return 0;
  1654. }
  1655. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1656. ret = iwl_hw_nic_init(priv);
  1657. if (ret) {
  1658. IWL_ERR(priv, "Unable to init nic\n");
  1659. return ret;
  1660. }
  1661. /* make sure rfkill handshake bits are cleared */
  1662. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1663. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1664. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1665. /* clear (again), then enable host interrupts */
  1666. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1667. iwl_enable_interrupts(priv);
  1668. /* really make sure rfkill handshake bits are cleared */
  1669. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1670. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1671. /* Copy original ucode data image from disk into backup cache.
  1672. * This will be used to initialize the on-board processor's
  1673. * data SRAM for a clean start when the runtime program first loads. */
  1674. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1675. priv->ucode_data.len);
  1676. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1677. iwl_clear_stations_table(priv);
  1678. /* load bootstrap state machine,
  1679. * load bootstrap program into processor's memory,
  1680. * prepare to load the "initialize" uCode */
  1681. ret = priv->cfg->ops->lib->load_ucode(priv);
  1682. if (ret) {
  1683. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1684. ret);
  1685. continue;
  1686. }
  1687. /* start card; "initialize" will load runtime ucode */
  1688. iwl_nic_start(priv);
  1689. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1690. return 0;
  1691. }
  1692. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1693. __iwl_down(priv);
  1694. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1695. /* tried to restart and config the device for as long as our
  1696. * patience could withstand */
  1697. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1698. return -EIO;
  1699. }
  1700. /*****************************************************************************
  1701. *
  1702. * Workqueue callbacks
  1703. *
  1704. *****************************************************************************/
  1705. static void iwl_bg_init_alive_start(struct work_struct *data)
  1706. {
  1707. struct iwl_priv *priv =
  1708. container_of(data, struct iwl_priv, init_alive_start.work);
  1709. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1710. return;
  1711. mutex_lock(&priv->mutex);
  1712. priv->cfg->ops->lib->init_alive_start(priv);
  1713. mutex_unlock(&priv->mutex);
  1714. }
  1715. static void iwl_bg_alive_start(struct work_struct *data)
  1716. {
  1717. struct iwl_priv *priv =
  1718. container_of(data, struct iwl_priv, alive_start.work);
  1719. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1720. return;
  1721. /* enable dram interrupt */
  1722. iwl_reset_ict(priv);
  1723. mutex_lock(&priv->mutex);
  1724. iwl_alive_start(priv);
  1725. mutex_unlock(&priv->mutex);
  1726. }
  1727. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1728. {
  1729. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1730. run_time_calib_work);
  1731. mutex_lock(&priv->mutex);
  1732. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1733. test_bit(STATUS_SCANNING, &priv->status)) {
  1734. mutex_unlock(&priv->mutex);
  1735. return;
  1736. }
  1737. if (priv->start_calib) {
  1738. iwl_chain_noise_calibration(priv, &priv->statistics);
  1739. iwl_sensitivity_calibration(priv, &priv->statistics);
  1740. }
  1741. mutex_unlock(&priv->mutex);
  1742. return;
  1743. }
  1744. static void iwl_bg_up(struct work_struct *data)
  1745. {
  1746. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1747. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1748. return;
  1749. mutex_lock(&priv->mutex);
  1750. __iwl_up(priv);
  1751. mutex_unlock(&priv->mutex);
  1752. }
  1753. static void iwl_bg_restart(struct work_struct *data)
  1754. {
  1755. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1756. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1757. return;
  1758. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1759. mutex_lock(&priv->mutex);
  1760. priv->vif = NULL;
  1761. priv->is_open = 0;
  1762. mutex_unlock(&priv->mutex);
  1763. iwl_down(priv);
  1764. ieee80211_restart_hw(priv->hw);
  1765. } else {
  1766. iwl_down(priv);
  1767. queue_work(priv->workqueue, &priv->up);
  1768. }
  1769. }
  1770. static void iwl_bg_rx_replenish(struct work_struct *data)
  1771. {
  1772. struct iwl_priv *priv =
  1773. container_of(data, struct iwl_priv, rx_replenish);
  1774. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1775. return;
  1776. mutex_lock(&priv->mutex);
  1777. iwl_rx_replenish(priv);
  1778. mutex_unlock(&priv->mutex);
  1779. }
  1780. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1781. void iwl_post_associate(struct iwl_priv *priv)
  1782. {
  1783. struct ieee80211_conf *conf = NULL;
  1784. int ret = 0;
  1785. unsigned long flags;
  1786. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1787. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1788. return;
  1789. }
  1790. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1791. priv->assoc_id, priv->active_rxon.bssid_addr);
  1792. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1793. return;
  1794. if (!priv->vif || !priv->is_open)
  1795. return;
  1796. iwl_scan_cancel_timeout(priv, 200);
  1797. conf = ieee80211_get_hw_conf(priv->hw);
  1798. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1799. iwlcore_commit_rxon(priv);
  1800. iwl_setup_rxon_timing(priv);
  1801. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1802. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1803. if (ret)
  1804. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1805. "Attempting to continue.\n");
  1806. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1807. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1808. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1809. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1810. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1811. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1812. priv->assoc_id, priv->beacon_int);
  1813. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1814. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1815. else
  1816. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1817. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1818. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1819. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1820. else
  1821. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1822. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1823. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1824. }
  1825. iwlcore_commit_rxon(priv);
  1826. switch (priv->iw_mode) {
  1827. case NL80211_IFTYPE_STATION:
  1828. break;
  1829. case NL80211_IFTYPE_ADHOC:
  1830. /* assume default assoc id */
  1831. priv->assoc_id = 1;
  1832. iwl_rxon_add_station(priv, priv->bssid, 0);
  1833. iwl_send_beacon_cmd(priv);
  1834. break;
  1835. default:
  1836. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1837. __func__, priv->iw_mode);
  1838. break;
  1839. }
  1840. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1841. priv->assoc_station_added = 1;
  1842. spin_lock_irqsave(&priv->lock, flags);
  1843. iwl_activate_qos(priv, 0);
  1844. spin_unlock_irqrestore(&priv->lock, flags);
  1845. /* the chain noise calibration will enabled PM upon completion
  1846. * If chain noise has already been run, then we need to enable
  1847. * power management here */
  1848. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1849. iwl_power_update_mode(priv, false);
  1850. /* Enable Rx differential gain and sensitivity calibrations */
  1851. iwl_chain_noise_reset(priv);
  1852. priv->start_calib = 1;
  1853. }
  1854. /*****************************************************************************
  1855. *
  1856. * mac80211 entry point functions
  1857. *
  1858. *****************************************************************************/
  1859. #define UCODE_READY_TIMEOUT (4 * HZ)
  1860. static int iwl_mac_start(struct ieee80211_hw *hw)
  1861. {
  1862. struct iwl_priv *priv = hw->priv;
  1863. int ret;
  1864. IWL_DEBUG_MAC80211(priv, "enter\n");
  1865. /* we should be verifying the device is ready to be opened */
  1866. mutex_lock(&priv->mutex);
  1867. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1868. * ucode filename and max sizes are card-specific. */
  1869. if (!priv->ucode_code.len) {
  1870. ret = iwl_read_ucode(priv);
  1871. if (ret) {
  1872. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1873. mutex_unlock(&priv->mutex);
  1874. return ret;
  1875. }
  1876. }
  1877. ret = __iwl_up(priv);
  1878. mutex_unlock(&priv->mutex);
  1879. if (ret)
  1880. return ret;
  1881. if (iwl_is_rfkill(priv))
  1882. goto out;
  1883. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1884. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1885. * mac80211 will not be run successfully. */
  1886. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1887. test_bit(STATUS_READY, &priv->status),
  1888. UCODE_READY_TIMEOUT);
  1889. if (!ret) {
  1890. if (!test_bit(STATUS_READY, &priv->status)) {
  1891. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1892. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1893. return -ETIMEDOUT;
  1894. }
  1895. }
  1896. out:
  1897. priv->is_open = 1;
  1898. IWL_DEBUG_MAC80211(priv, "leave\n");
  1899. return 0;
  1900. }
  1901. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1902. {
  1903. struct iwl_priv *priv = hw->priv;
  1904. IWL_DEBUG_MAC80211(priv, "enter\n");
  1905. if (!priv->is_open)
  1906. return;
  1907. priv->is_open = 0;
  1908. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  1909. /* stop mac, cancel any scan request and clear
  1910. * RXON_FILTER_ASSOC_MSK BIT
  1911. */
  1912. mutex_lock(&priv->mutex);
  1913. iwl_scan_cancel_timeout(priv, 100);
  1914. mutex_unlock(&priv->mutex);
  1915. }
  1916. iwl_down(priv);
  1917. flush_workqueue(priv->workqueue);
  1918. /* enable interrupts again in order to receive rfkill changes */
  1919. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1920. iwl_enable_interrupts(priv);
  1921. IWL_DEBUG_MAC80211(priv, "leave\n");
  1922. }
  1923. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1924. {
  1925. struct iwl_priv *priv = hw->priv;
  1926. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1927. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1928. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1929. if (iwl_tx_skb(priv, skb))
  1930. dev_kfree_skb_any(skb);
  1931. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1932. return NETDEV_TX_OK;
  1933. }
  1934. void iwl_config_ap(struct iwl_priv *priv)
  1935. {
  1936. int ret = 0;
  1937. unsigned long flags;
  1938. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1939. return;
  1940. /* The following should be done only at AP bring up */
  1941. if (!iwl_is_associated(priv)) {
  1942. /* RXON - unassoc (to set timing command) */
  1943. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1944. iwlcore_commit_rxon(priv);
  1945. /* RXON Timing */
  1946. iwl_setup_rxon_timing(priv);
  1947. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1948. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1949. if (ret)
  1950. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1951. "Attempting to continue.\n");
  1952. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1953. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1954. /* FIXME: what should be the assoc_id for AP? */
  1955. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1956. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1957. priv->staging_rxon.flags |=
  1958. RXON_FLG_SHORT_PREAMBLE_MSK;
  1959. else
  1960. priv->staging_rxon.flags &=
  1961. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1962. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1963. if (priv->assoc_capability &
  1964. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1965. priv->staging_rxon.flags |=
  1966. RXON_FLG_SHORT_SLOT_MSK;
  1967. else
  1968. priv->staging_rxon.flags &=
  1969. ~RXON_FLG_SHORT_SLOT_MSK;
  1970. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1971. priv->staging_rxon.flags &=
  1972. ~RXON_FLG_SHORT_SLOT_MSK;
  1973. }
  1974. /* restore RXON assoc */
  1975. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1976. iwlcore_commit_rxon(priv);
  1977. spin_lock_irqsave(&priv->lock, flags);
  1978. iwl_activate_qos(priv, 1);
  1979. spin_unlock_irqrestore(&priv->lock, flags);
  1980. iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
  1981. }
  1982. iwl_send_beacon_cmd(priv);
  1983. /* FIXME - we need to add code here to detect a totally new
  1984. * configuration, reset the AP, unassoc, rxon timing, assoc,
  1985. * clear sta table, add BCAST sta... */
  1986. }
  1987. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  1988. struct ieee80211_key_conf *keyconf, const u8 *addr,
  1989. u32 iv32, u16 *phase1key)
  1990. {
  1991. struct iwl_priv *priv = hw->priv;
  1992. IWL_DEBUG_MAC80211(priv, "enter\n");
  1993. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  1994. IWL_DEBUG_MAC80211(priv, "leave\n");
  1995. }
  1996. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1997. struct ieee80211_vif *vif,
  1998. struct ieee80211_sta *sta,
  1999. struct ieee80211_key_conf *key)
  2000. {
  2001. struct iwl_priv *priv = hw->priv;
  2002. const u8 *addr;
  2003. int ret;
  2004. u8 sta_id;
  2005. bool is_default_wep_key = false;
  2006. IWL_DEBUG_MAC80211(priv, "enter\n");
  2007. if (priv->cfg->mod_params->sw_crypto) {
  2008. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2009. return -EOPNOTSUPP;
  2010. }
  2011. addr = sta ? sta->addr : iwl_bcast_addr;
  2012. sta_id = iwl_find_station(priv, addr);
  2013. if (sta_id == IWL_INVALID_STATION) {
  2014. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2015. addr);
  2016. return -EINVAL;
  2017. }
  2018. mutex_lock(&priv->mutex);
  2019. iwl_scan_cancel_timeout(priv, 100);
  2020. mutex_unlock(&priv->mutex);
  2021. /* If we are getting WEP group key and we didn't receive any key mapping
  2022. * so far, we are in legacy wep mode (group key only), otherwise we are
  2023. * in 1X mode.
  2024. * In legacy wep mode, we use another host command to the uCode */
  2025. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2026. priv->iw_mode != NL80211_IFTYPE_AP) {
  2027. if (cmd == SET_KEY)
  2028. is_default_wep_key = !priv->key_mapping_key;
  2029. else
  2030. is_default_wep_key =
  2031. (key->hw_key_idx == HW_KEY_DEFAULT);
  2032. }
  2033. switch (cmd) {
  2034. case SET_KEY:
  2035. if (is_default_wep_key)
  2036. ret = iwl_set_default_wep_key(priv, key);
  2037. else
  2038. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2039. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2040. break;
  2041. case DISABLE_KEY:
  2042. if (is_default_wep_key)
  2043. ret = iwl_remove_default_wep_key(priv, key);
  2044. else
  2045. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2046. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2047. break;
  2048. default:
  2049. ret = -EINVAL;
  2050. }
  2051. IWL_DEBUG_MAC80211(priv, "leave\n");
  2052. return ret;
  2053. }
  2054. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2055. enum ieee80211_ampdu_mlme_action action,
  2056. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2057. {
  2058. struct iwl_priv *priv = hw->priv;
  2059. int ret;
  2060. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2061. sta->addr, tid);
  2062. if (!(priv->cfg->sku & IWL_SKU_N))
  2063. return -EACCES;
  2064. switch (action) {
  2065. case IEEE80211_AMPDU_RX_START:
  2066. IWL_DEBUG_HT(priv, "start Rx\n");
  2067. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2068. case IEEE80211_AMPDU_RX_STOP:
  2069. IWL_DEBUG_HT(priv, "stop Rx\n");
  2070. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2071. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2072. return 0;
  2073. else
  2074. return ret;
  2075. case IEEE80211_AMPDU_TX_START:
  2076. IWL_DEBUG_HT(priv, "start Tx\n");
  2077. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2078. case IEEE80211_AMPDU_TX_STOP:
  2079. IWL_DEBUG_HT(priv, "stop Tx\n");
  2080. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2081. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2082. return 0;
  2083. else
  2084. return ret;
  2085. default:
  2086. IWL_DEBUG_HT(priv, "unknown\n");
  2087. return -EINVAL;
  2088. break;
  2089. }
  2090. return 0;
  2091. }
  2092. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2093. struct ieee80211_low_level_stats *stats)
  2094. {
  2095. struct iwl_priv *priv = hw->priv;
  2096. priv = hw->priv;
  2097. IWL_DEBUG_MAC80211(priv, "enter\n");
  2098. IWL_DEBUG_MAC80211(priv, "leave\n");
  2099. return 0;
  2100. }
  2101. /*****************************************************************************
  2102. *
  2103. * sysfs attributes
  2104. *
  2105. *****************************************************************************/
  2106. #ifdef CONFIG_IWLWIFI_DEBUG
  2107. /*
  2108. * The following adds a new attribute to the sysfs representation
  2109. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2110. * used for controlling the debug level.
  2111. *
  2112. * See the level definitions in iwl for details.
  2113. *
  2114. * The debug_level being managed using sysfs below is a per device debug
  2115. * level that is used instead of the global debug level if it (the per
  2116. * device debug level) is set.
  2117. */
  2118. static ssize_t show_debug_level(struct device *d,
  2119. struct device_attribute *attr, char *buf)
  2120. {
  2121. struct iwl_priv *priv = dev_get_drvdata(d);
  2122. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2123. }
  2124. static ssize_t store_debug_level(struct device *d,
  2125. struct device_attribute *attr,
  2126. const char *buf, size_t count)
  2127. {
  2128. struct iwl_priv *priv = dev_get_drvdata(d);
  2129. unsigned long val;
  2130. int ret;
  2131. ret = strict_strtoul(buf, 0, &val);
  2132. if (ret)
  2133. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2134. else {
  2135. priv->debug_level = val;
  2136. if (iwl_alloc_traffic_mem(priv))
  2137. IWL_ERR(priv,
  2138. "Not enough memory to generate traffic log\n");
  2139. }
  2140. return strnlen(buf, count);
  2141. }
  2142. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2143. show_debug_level, store_debug_level);
  2144. #endif /* CONFIG_IWLWIFI_DEBUG */
  2145. static ssize_t show_temperature(struct device *d,
  2146. struct device_attribute *attr, char *buf)
  2147. {
  2148. struct iwl_priv *priv = dev_get_drvdata(d);
  2149. if (!iwl_is_alive(priv))
  2150. return -EAGAIN;
  2151. return sprintf(buf, "%d\n", priv->temperature);
  2152. }
  2153. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2154. static ssize_t show_tx_power(struct device *d,
  2155. struct device_attribute *attr, char *buf)
  2156. {
  2157. struct iwl_priv *priv = dev_get_drvdata(d);
  2158. if (!iwl_is_ready_rf(priv))
  2159. return sprintf(buf, "off\n");
  2160. else
  2161. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2162. }
  2163. static ssize_t store_tx_power(struct device *d,
  2164. struct device_attribute *attr,
  2165. const char *buf, size_t count)
  2166. {
  2167. struct iwl_priv *priv = dev_get_drvdata(d);
  2168. unsigned long val;
  2169. int ret;
  2170. ret = strict_strtoul(buf, 10, &val);
  2171. if (ret)
  2172. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2173. else {
  2174. ret = iwl_set_tx_power(priv, val, false);
  2175. if (ret)
  2176. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2177. ret);
  2178. else
  2179. ret = count;
  2180. }
  2181. return ret;
  2182. }
  2183. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2184. static ssize_t show_flags(struct device *d,
  2185. struct device_attribute *attr, char *buf)
  2186. {
  2187. struct iwl_priv *priv = dev_get_drvdata(d);
  2188. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2189. }
  2190. static ssize_t store_flags(struct device *d,
  2191. struct device_attribute *attr,
  2192. const char *buf, size_t count)
  2193. {
  2194. struct iwl_priv *priv = dev_get_drvdata(d);
  2195. unsigned long val;
  2196. u32 flags;
  2197. int ret = strict_strtoul(buf, 0, &val);
  2198. if (ret)
  2199. return ret;
  2200. flags = (u32)val;
  2201. mutex_lock(&priv->mutex);
  2202. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2203. /* Cancel any currently running scans... */
  2204. if (iwl_scan_cancel_timeout(priv, 100))
  2205. IWL_WARN(priv, "Could not cancel scan.\n");
  2206. else {
  2207. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2208. priv->staging_rxon.flags = cpu_to_le32(flags);
  2209. iwlcore_commit_rxon(priv);
  2210. }
  2211. }
  2212. mutex_unlock(&priv->mutex);
  2213. return count;
  2214. }
  2215. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2216. static ssize_t show_filter_flags(struct device *d,
  2217. struct device_attribute *attr, char *buf)
  2218. {
  2219. struct iwl_priv *priv = dev_get_drvdata(d);
  2220. return sprintf(buf, "0x%04X\n",
  2221. le32_to_cpu(priv->active_rxon.filter_flags));
  2222. }
  2223. static ssize_t store_filter_flags(struct device *d,
  2224. struct device_attribute *attr,
  2225. const char *buf, size_t count)
  2226. {
  2227. struct iwl_priv *priv = dev_get_drvdata(d);
  2228. unsigned long val;
  2229. u32 filter_flags;
  2230. int ret = strict_strtoul(buf, 0, &val);
  2231. if (ret)
  2232. return ret;
  2233. filter_flags = (u32)val;
  2234. mutex_lock(&priv->mutex);
  2235. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2236. /* Cancel any currently running scans... */
  2237. if (iwl_scan_cancel_timeout(priv, 100))
  2238. IWL_WARN(priv, "Could not cancel scan.\n");
  2239. else {
  2240. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2241. "0x%04X\n", filter_flags);
  2242. priv->staging_rxon.filter_flags =
  2243. cpu_to_le32(filter_flags);
  2244. iwlcore_commit_rxon(priv);
  2245. }
  2246. }
  2247. mutex_unlock(&priv->mutex);
  2248. return count;
  2249. }
  2250. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2251. store_filter_flags);
  2252. static ssize_t show_statistics(struct device *d,
  2253. struct device_attribute *attr, char *buf)
  2254. {
  2255. struct iwl_priv *priv = dev_get_drvdata(d);
  2256. u32 size = sizeof(struct iwl_notif_statistics);
  2257. u32 len = 0, ofs = 0;
  2258. u8 *data = (u8 *)&priv->statistics;
  2259. int rc = 0;
  2260. if (!iwl_is_alive(priv))
  2261. return -EAGAIN;
  2262. mutex_lock(&priv->mutex);
  2263. rc = iwl_send_statistics_request(priv, 0);
  2264. mutex_unlock(&priv->mutex);
  2265. if (rc) {
  2266. len = sprintf(buf,
  2267. "Error sending statistics request: 0x%08X\n", rc);
  2268. return len;
  2269. }
  2270. while (size && (PAGE_SIZE - len)) {
  2271. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2272. PAGE_SIZE - len, 1);
  2273. len = strlen(buf);
  2274. if (PAGE_SIZE - len)
  2275. buf[len++] = '\n';
  2276. ofs += 16;
  2277. size -= min(size, 16U);
  2278. }
  2279. return len;
  2280. }
  2281. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2282. /*****************************************************************************
  2283. *
  2284. * driver setup and teardown
  2285. *
  2286. *****************************************************************************/
  2287. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2288. {
  2289. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2290. init_waitqueue_head(&priv->wait_command_queue);
  2291. INIT_WORK(&priv->up, iwl_bg_up);
  2292. INIT_WORK(&priv->restart, iwl_bg_restart);
  2293. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2294. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2295. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2296. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2297. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2298. iwl_setup_scan_deferred_work(priv);
  2299. if (priv->cfg->ops->lib->setup_deferred_work)
  2300. priv->cfg->ops->lib->setup_deferred_work(priv);
  2301. init_timer(&priv->statistics_periodic);
  2302. priv->statistics_periodic.data = (unsigned long)priv;
  2303. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2304. if (!priv->cfg->use_isr_legacy)
  2305. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2306. iwl_irq_tasklet, (unsigned long)priv);
  2307. else
  2308. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2309. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2310. }
  2311. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2312. {
  2313. if (priv->cfg->ops->lib->cancel_deferred_work)
  2314. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2315. cancel_delayed_work_sync(&priv->init_alive_start);
  2316. cancel_delayed_work(&priv->scan_check);
  2317. cancel_delayed_work(&priv->alive_start);
  2318. cancel_work_sync(&priv->beacon_update);
  2319. del_timer_sync(&priv->statistics_periodic);
  2320. }
  2321. static struct attribute *iwl_sysfs_entries[] = {
  2322. &dev_attr_flags.attr,
  2323. &dev_attr_filter_flags.attr,
  2324. &dev_attr_statistics.attr,
  2325. &dev_attr_temperature.attr,
  2326. &dev_attr_tx_power.attr,
  2327. #ifdef CONFIG_IWLWIFI_DEBUG
  2328. &dev_attr_debug_level.attr,
  2329. #endif
  2330. NULL
  2331. };
  2332. static struct attribute_group iwl_attribute_group = {
  2333. .name = NULL, /* put in device directory */
  2334. .attrs = iwl_sysfs_entries,
  2335. };
  2336. static struct ieee80211_ops iwl_hw_ops = {
  2337. .tx = iwl_mac_tx,
  2338. .start = iwl_mac_start,
  2339. .stop = iwl_mac_stop,
  2340. .add_interface = iwl_mac_add_interface,
  2341. .remove_interface = iwl_mac_remove_interface,
  2342. .config = iwl_mac_config,
  2343. .configure_filter = iwl_configure_filter,
  2344. .set_key = iwl_mac_set_key,
  2345. .update_tkip_key = iwl_mac_update_tkip_key,
  2346. .get_stats = iwl_mac_get_stats,
  2347. .get_tx_stats = iwl_mac_get_tx_stats,
  2348. .conf_tx = iwl_mac_conf_tx,
  2349. .reset_tsf = iwl_mac_reset_tsf,
  2350. .bss_info_changed = iwl_bss_info_changed,
  2351. .ampdu_action = iwl_mac_ampdu_action,
  2352. .hw_scan = iwl_mac_hw_scan
  2353. };
  2354. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2355. {
  2356. int err = 0;
  2357. struct iwl_priv *priv;
  2358. struct ieee80211_hw *hw;
  2359. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2360. unsigned long flags;
  2361. u16 pci_cmd;
  2362. /************************
  2363. * 1. Allocating HW data
  2364. ************************/
  2365. /* Disabling hardware scan means that mac80211 will perform scans
  2366. * "the hard way", rather than using device's scan. */
  2367. if (cfg->mod_params->disable_hw_scan) {
  2368. if (iwl_debug_level & IWL_DL_INFO)
  2369. dev_printk(KERN_DEBUG, &(pdev->dev),
  2370. "Disabling hw_scan\n");
  2371. iwl_hw_ops.hw_scan = NULL;
  2372. }
  2373. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2374. if (!hw) {
  2375. err = -ENOMEM;
  2376. goto out;
  2377. }
  2378. priv = hw->priv;
  2379. /* At this point both hw and priv are allocated. */
  2380. SET_IEEE80211_DEV(hw, &pdev->dev);
  2381. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2382. priv->cfg = cfg;
  2383. priv->pci_dev = pdev;
  2384. priv->inta_mask = CSR_INI_SET_MASK;
  2385. #ifdef CONFIG_IWLWIFI_DEBUG
  2386. atomic_set(&priv->restrict_refcnt, 0);
  2387. #endif
  2388. if (iwl_alloc_traffic_mem(priv))
  2389. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2390. /**************************
  2391. * 2. Initializing PCI bus
  2392. **************************/
  2393. if (pci_enable_device(pdev)) {
  2394. err = -ENODEV;
  2395. goto out_ieee80211_free_hw;
  2396. }
  2397. pci_set_master(pdev);
  2398. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2399. if (!err)
  2400. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2401. if (err) {
  2402. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2403. if (!err)
  2404. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2405. /* both attempts failed: */
  2406. if (err) {
  2407. IWL_WARN(priv, "No suitable DMA available.\n");
  2408. goto out_pci_disable_device;
  2409. }
  2410. }
  2411. err = pci_request_regions(pdev, DRV_NAME);
  2412. if (err)
  2413. goto out_pci_disable_device;
  2414. pci_set_drvdata(pdev, priv);
  2415. /***********************
  2416. * 3. Read REV register
  2417. ***********************/
  2418. priv->hw_base = pci_iomap(pdev, 0, 0);
  2419. if (!priv->hw_base) {
  2420. err = -ENODEV;
  2421. goto out_pci_release_regions;
  2422. }
  2423. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2424. (unsigned long long) pci_resource_len(pdev, 0));
  2425. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2426. /* this spin lock will be used in apm_ops.init and EEPROM access
  2427. * we should init now
  2428. */
  2429. spin_lock_init(&priv->reg_lock);
  2430. iwl_hw_detect(priv);
  2431. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2432. priv->cfg->name, priv->hw_rev);
  2433. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2434. * PCI Tx retries from interfering with C3 CPU state */
  2435. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2436. iwl_prepare_card_hw(priv);
  2437. if (!priv->hw_ready) {
  2438. IWL_WARN(priv, "Failed, HW not ready\n");
  2439. goto out_iounmap;
  2440. }
  2441. /* amp init */
  2442. err = priv->cfg->ops->lib->apm_ops.init(priv);
  2443. if (err < 0) {
  2444. IWL_ERR(priv, "Failed to init APMG\n");
  2445. goto out_iounmap;
  2446. }
  2447. /*****************
  2448. * 4. Read EEPROM
  2449. *****************/
  2450. /* Read the EEPROM */
  2451. err = iwl_eeprom_init(priv);
  2452. if (err) {
  2453. IWL_ERR(priv, "Unable to init EEPROM\n");
  2454. goto out_iounmap;
  2455. }
  2456. err = iwl_eeprom_check_version(priv);
  2457. if (err)
  2458. goto out_free_eeprom;
  2459. /* extract MAC Address */
  2460. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2461. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2462. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2463. /************************
  2464. * 5. Setup HW constants
  2465. ************************/
  2466. if (iwl_set_hw_params(priv)) {
  2467. IWL_ERR(priv, "failed to set hw parameters\n");
  2468. goto out_free_eeprom;
  2469. }
  2470. /*******************
  2471. * 6. Setup priv
  2472. *******************/
  2473. err = iwl_init_drv(priv);
  2474. if (err)
  2475. goto out_free_eeprom;
  2476. /* At this point both hw and priv are initialized. */
  2477. /********************
  2478. * 7. Setup services
  2479. ********************/
  2480. spin_lock_irqsave(&priv->lock, flags);
  2481. iwl_disable_interrupts(priv);
  2482. spin_unlock_irqrestore(&priv->lock, flags);
  2483. pci_enable_msi(priv->pci_dev);
  2484. iwl_alloc_isr_ict(priv);
  2485. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2486. IRQF_SHARED, DRV_NAME, priv);
  2487. if (err) {
  2488. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2489. goto out_disable_msi;
  2490. }
  2491. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2492. if (err) {
  2493. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2494. goto out_free_irq;
  2495. }
  2496. iwl_setup_deferred_work(priv);
  2497. iwl_setup_rx_handlers(priv);
  2498. /**********************************
  2499. * 8. Setup and register mac80211
  2500. **********************************/
  2501. /* enable interrupts if needed: hw bug w/a */
  2502. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2503. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2504. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2505. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2506. }
  2507. iwl_enable_interrupts(priv);
  2508. err = iwl_setup_mac(priv);
  2509. if (err)
  2510. goto out_remove_sysfs;
  2511. err = iwl_dbgfs_register(priv, DRV_NAME);
  2512. if (err)
  2513. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2514. /* If platform's RF_KILL switch is NOT set to KILL */
  2515. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2516. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2517. else
  2518. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2519. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2520. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2521. iwl_power_initialize(priv);
  2522. iwl_tt_initialize(priv);
  2523. return 0;
  2524. out_remove_sysfs:
  2525. destroy_workqueue(priv->workqueue);
  2526. priv->workqueue = NULL;
  2527. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2528. out_free_irq:
  2529. free_irq(priv->pci_dev->irq, priv);
  2530. iwl_free_isr_ict(priv);
  2531. out_disable_msi:
  2532. pci_disable_msi(priv->pci_dev);
  2533. iwl_uninit_drv(priv);
  2534. out_free_eeprom:
  2535. iwl_eeprom_free(priv);
  2536. out_iounmap:
  2537. pci_iounmap(pdev, priv->hw_base);
  2538. out_pci_release_regions:
  2539. pci_set_drvdata(pdev, NULL);
  2540. pci_release_regions(pdev);
  2541. out_pci_disable_device:
  2542. pci_disable_device(pdev);
  2543. out_ieee80211_free_hw:
  2544. iwl_free_traffic_mem(priv);
  2545. ieee80211_free_hw(priv->hw);
  2546. out:
  2547. return err;
  2548. }
  2549. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2550. {
  2551. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2552. unsigned long flags;
  2553. if (!priv)
  2554. return;
  2555. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2556. iwl_dbgfs_unregister(priv);
  2557. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2558. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2559. * to be called and iwl_down since we are removing the device
  2560. * we need to set STATUS_EXIT_PENDING bit.
  2561. */
  2562. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2563. if (priv->mac80211_registered) {
  2564. ieee80211_unregister_hw(priv->hw);
  2565. priv->mac80211_registered = 0;
  2566. } else {
  2567. iwl_down(priv);
  2568. }
  2569. iwl_tt_exit(priv);
  2570. /* make sure we flush any pending irq or
  2571. * tasklet for the driver
  2572. */
  2573. spin_lock_irqsave(&priv->lock, flags);
  2574. iwl_disable_interrupts(priv);
  2575. spin_unlock_irqrestore(&priv->lock, flags);
  2576. iwl_synchronize_irq(priv);
  2577. iwl_dealloc_ucode_pci(priv);
  2578. if (priv->rxq.bd)
  2579. iwl_rx_queue_free(priv, &priv->rxq);
  2580. iwl_hw_txq_ctx_free(priv);
  2581. iwl_clear_stations_table(priv);
  2582. iwl_eeprom_free(priv);
  2583. /*netif_stop_queue(dev); */
  2584. flush_workqueue(priv->workqueue);
  2585. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2586. * priv->workqueue... so we can't take down the workqueue
  2587. * until now... */
  2588. destroy_workqueue(priv->workqueue);
  2589. priv->workqueue = NULL;
  2590. iwl_free_traffic_mem(priv);
  2591. free_irq(priv->pci_dev->irq, priv);
  2592. pci_disable_msi(priv->pci_dev);
  2593. pci_iounmap(pdev, priv->hw_base);
  2594. pci_release_regions(pdev);
  2595. pci_disable_device(pdev);
  2596. pci_set_drvdata(pdev, NULL);
  2597. iwl_uninit_drv(priv);
  2598. iwl_free_isr_ict(priv);
  2599. if (priv->ibss_beacon)
  2600. dev_kfree_skb(priv->ibss_beacon);
  2601. ieee80211_free_hw(priv->hw);
  2602. }
  2603. /*****************************************************************************
  2604. *
  2605. * driver and module entry point
  2606. *
  2607. *****************************************************************************/
  2608. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2609. static struct pci_device_id iwl_hw_card_ids[] = {
  2610. #ifdef CONFIG_IWL4965
  2611. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2612. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2613. #endif /* CONFIG_IWL4965 */
  2614. #ifdef CONFIG_IWL5000
  2615. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2616. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2617. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2618. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2619. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2620. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2621. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2622. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2623. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2624. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2625. /* 5350 WiFi/WiMax */
  2626. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2627. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2628. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2629. /* 5150 Wifi/WiMax */
  2630. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2631. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2632. /* 6000/6050 Series */
  2633. {IWL_PCI_DEVICE(0x008D, PCI_ANY_ID, iwl6000h_2agn_cfg)},
  2634. {IWL_PCI_DEVICE(0x008E, PCI_ANY_ID, iwl6000h_2agn_cfg)},
  2635. {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2636. {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000i_2agn_cfg)},
  2637. {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
  2638. {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000i_2agn_cfg)},
  2639. {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2640. {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2641. {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
  2642. {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
  2643. /* 1000 Series WiFi */
  2644. {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2645. {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
  2646. #endif /* CONFIG_IWL5000 */
  2647. {0}
  2648. };
  2649. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2650. static struct pci_driver iwl_driver = {
  2651. .name = DRV_NAME,
  2652. .id_table = iwl_hw_card_ids,
  2653. .probe = iwl_pci_probe,
  2654. .remove = __devexit_p(iwl_pci_remove),
  2655. #ifdef CONFIG_PM
  2656. .suspend = iwl_pci_suspend,
  2657. .resume = iwl_pci_resume,
  2658. #endif
  2659. };
  2660. static int __init iwl_init(void)
  2661. {
  2662. int ret;
  2663. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2664. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2665. ret = iwlagn_rate_control_register();
  2666. if (ret) {
  2667. printk(KERN_ERR DRV_NAME
  2668. "Unable to register rate control algorithm: %d\n", ret);
  2669. return ret;
  2670. }
  2671. ret = pci_register_driver(&iwl_driver);
  2672. if (ret) {
  2673. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2674. goto error_register;
  2675. }
  2676. return ret;
  2677. error_register:
  2678. iwlagn_rate_control_unregister();
  2679. return ret;
  2680. }
  2681. static void __exit iwl_exit(void)
  2682. {
  2683. pci_unregister_driver(&iwl_driver);
  2684. iwlagn_rate_control_unregister();
  2685. }
  2686. module_exit(iwl_exit);
  2687. module_init(iwl_init);
  2688. #ifdef CONFIG_IWLWIFI_DEBUG
  2689. module_param_named(debug50, iwl_debug_level, uint, 0444);
  2690. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  2691. module_param_named(debug, iwl_debug_level, uint, 0644);
  2692. MODULE_PARM_DESC(debug, "debug output mask");
  2693. #endif