atl1c_main.c 76 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779
  1. /*
  2. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1c.h"
  22. #define ATL1C_DRV_VERSION "1.0.0.1-NAPI"
  23. char atl1c_driver_name[] = "atl1c";
  24. char atl1c_driver_version[] = ATL1C_DRV_VERSION;
  25. #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
  26. #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
  27. /*
  28. * atl1c_pci_tbl - PCI Device ID Table
  29. *
  30. * Wildcard entries (PCI_ANY_ID) should come last
  31. * Last entry must be all 0s
  32. *
  33. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  34. * Class, Class Mask, private data (not used) }
  35. */
  36. static struct pci_device_id atl1c_pci_tbl[] = {
  37. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  38. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  39. /* required last entry */
  40. { 0 }
  41. };
  42. MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  43. MODULE_AUTHOR("Jie Yang <jie.yang@atheros.com>");
  44. MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
  45. MODULE_LICENSE("GPL");
  46. MODULE_VERSION(ATL1C_DRV_VERSION);
  47. static int atl1c_stop_mac(struct atl1c_hw *hw);
  48. static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
  49. static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
  50. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  51. static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup);
  52. static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
  53. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
  54. int *work_done, int work_to_do);
  55. static const u16 atl1c_pay_load_size[] = {
  56. 128, 256, 512, 1024, 2048, 4096,
  57. };
  58. static const u16 atl1c_rfd_prod_idx_regs[AT_MAX_RECEIVE_QUEUE] =
  59. {
  60. REG_MB_RFD0_PROD_IDX,
  61. REG_MB_RFD1_PROD_IDX,
  62. REG_MB_RFD2_PROD_IDX,
  63. REG_MB_RFD3_PROD_IDX
  64. };
  65. static const u16 atl1c_rfd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
  66. {
  67. REG_RFD0_HEAD_ADDR_LO,
  68. REG_RFD1_HEAD_ADDR_LO,
  69. REG_RFD2_HEAD_ADDR_LO,
  70. REG_RFD3_HEAD_ADDR_LO
  71. };
  72. static const u16 atl1c_rrd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
  73. {
  74. REG_RRD0_HEAD_ADDR_LO,
  75. REG_RRD1_HEAD_ADDR_LO,
  76. REG_RRD2_HEAD_ADDR_LO,
  77. REG_RRD3_HEAD_ADDR_LO
  78. };
  79. static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  80. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  81. /*
  82. * atl1c_init_pcie - init PCIE module
  83. */
  84. static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
  85. {
  86. u32 data;
  87. u32 pci_cmd;
  88. struct pci_dev *pdev = hw->adapter->pdev;
  89. AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
  90. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  91. pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  92. PCI_COMMAND_IO);
  93. AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
  94. /*
  95. * Clear any PowerSaveing Settings
  96. */
  97. pci_enable_wake(pdev, PCI_D3hot, 0);
  98. pci_enable_wake(pdev, PCI_D3cold, 0);
  99. /*
  100. * Mask some pcie error bits
  101. */
  102. AT_READ_REG(hw, REG_PCIE_UC_SEVERITY, &data);
  103. data &= ~PCIE_UC_SERVRITY_DLP;
  104. data &= ~PCIE_UC_SERVRITY_FCP;
  105. AT_WRITE_REG(hw, REG_PCIE_UC_SEVERITY, data);
  106. if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
  107. atl1c_disable_l0s_l1(hw);
  108. if (flag & ATL1C_PCIE_PHY_RESET)
  109. AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
  110. else
  111. AT_WRITE_REG(hw, REG_GPHY_CTRL,
  112. GPHY_CTRL_DEFAULT | GPHY_CTRL_EXT_RESET);
  113. msleep(1);
  114. }
  115. /*
  116. * atl1c_irq_enable - Enable default interrupt generation settings
  117. * @adapter: board private structure
  118. */
  119. static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
  120. {
  121. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  122. AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
  123. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  124. AT_WRITE_FLUSH(&adapter->hw);
  125. }
  126. }
  127. /*
  128. * atl1c_irq_disable - Mask off interrupt generation on the NIC
  129. * @adapter: board private structure
  130. */
  131. static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
  132. {
  133. atomic_inc(&adapter->irq_sem);
  134. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  135. AT_WRITE_FLUSH(&adapter->hw);
  136. synchronize_irq(adapter->pdev->irq);
  137. }
  138. /*
  139. * atl1c_irq_reset - reset interrupt confiure on the NIC
  140. * @adapter: board private structure
  141. */
  142. static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
  143. {
  144. atomic_set(&adapter->irq_sem, 1);
  145. atl1c_irq_enable(adapter);
  146. }
  147. /*
  148. * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
  149. * of the idle status register until the device is actually idle
  150. */
  151. static u32 atl1c_wait_until_idle(struct atl1c_hw *hw)
  152. {
  153. int timeout;
  154. u32 data;
  155. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  156. AT_READ_REG(hw, REG_IDLE_STATUS, &data);
  157. if ((data & IDLE_STATUS_MASK) == 0)
  158. return 0;
  159. msleep(1);
  160. }
  161. return data;
  162. }
  163. /*
  164. * atl1c_phy_config - Timer Call-back
  165. * @data: pointer to netdev cast into an unsigned long
  166. */
  167. static void atl1c_phy_config(unsigned long data)
  168. {
  169. struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
  170. struct atl1c_hw *hw = &adapter->hw;
  171. unsigned long flags;
  172. spin_lock_irqsave(&adapter->mdio_lock, flags);
  173. atl1c_restart_autoneg(hw);
  174. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  175. }
  176. void atl1c_reinit_locked(struct atl1c_adapter *adapter)
  177. {
  178. WARN_ON(in_interrupt());
  179. atl1c_down(adapter);
  180. atl1c_up(adapter);
  181. clear_bit(__AT_RESETTING, &adapter->flags);
  182. }
  183. static void atl1c_reset_task(struct work_struct *work)
  184. {
  185. struct atl1c_adapter *adapter;
  186. struct net_device *netdev;
  187. adapter = container_of(work, struct atl1c_adapter, reset_task);
  188. netdev = adapter->netdev;
  189. netif_device_detach(netdev);
  190. atl1c_down(adapter);
  191. atl1c_up(adapter);
  192. netif_device_attach(netdev);
  193. }
  194. static void atl1c_check_link_status(struct atl1c_adapter *adapter)
  195. {
  196. struct atl1c_hw *hw = &adapter->hw;
  197. struct net_device *netdev = adapter->netdev;
  198. struct pci_dev *pdev = adapter->pdev;
  199. int err;
  200. unsigned long flags;
  201. u16 speed, duplex, phy_data;
  202. spin_lock_irqsave(&adapter->mdio_lock, flags);
  203. /* MII_BMSR must read twise */
  204. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  205. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  206. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  207. if ((phy_data & BMSR_LSTATUS) == 0) {
  208. /* link down */
  209. if (netif_carrier_ok(netdev)) {
  210. hw->hibernate = true;
  211. if (atl1c_stop_mac(hw) != 0)
  212. if (netif_msg_hw(adapter))
  213. dev_warn(&pdev->dev,
  214. "stop mac failed\n");
  215. atl1c_set_aspm(hw, false);
  216. }
  217. netif_carrier_off(netdev);
  218. } else {
  219. /* Link Up */
  220. hw->hibernate = false;
  221. spin_lock_irqsave(&adapter->mdio_lock, flags);
  222. err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
  223. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  224. if (unlikely(err))
  225. return;
  226. /* link result is our setting */
  227. if (adapter->link_speed != speed ||
  228. adapter->link_duplex != duplex) {
  229. adapter->link_speed = speed;
  230. adapter->link_duplex = duplex;
  231. atl1c_set_aspm(hw, true);
  232. atl1c_enable_tx_ctrl(hw);
  233. atl1c_enable_rx_ctrl(hw);
  234. atl1c_setup_mac_ctrl(adapter);
  235. if (netif_msg_link(adapter))
  236. dev_info(&pdev->dev,
  237. "%s: %s NIC Link is Up<%d Mbps %s>\n",
  238. atl1c_driver_name, netdev->name,
  239. adapter->link_speed,
  240. adapter->link_duplex == FULL_DUPLEX ?
  241. "Full Duplex" : "Half Duplex");
  242. }
  243. if (!netif_carrier_ok(netdev))
  244. netif_carrier_on(netdev);
  245. }
  246. }
  247. /*
  248. * atl1c_link_chg_task - deal with link change event Out of interrupt context
  249. * @netdev: network interface device structure
  250. */
  251. static void atl1c_link_chg_task(struct work_struct *work)
  252. {
  253. struct atl1c_adapter *adapter;
  254. adapter = container_of(work, struct atl1c_adapter, link_chg_task);
  255. atl1c_check_link_status(adapter);
  256. }
  257. static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
  258. {
  259. struct net_device *netdev = adapter->netdev;
  260. struct pci_dev *pdev = adapter->pdev;
  261. u16 phy_data;
  262. u16 link_up;
  263. spin_lock(&adapter->mdio_lock);
  264. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  265. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  266. spin_unlock(&adapter->mdio_lock);
  267. link_up = phy_data & BMSR_LSTATUS;
  268. /* notify upper layer link down ASAP */
  269. if (!link_up) {
  270. if (netif_carrier_ok(netdev)) {
  271. /* old link state: Up */
  272. netif_carrier_off(netdev);
  273. if (netif_msg_link(adapter))
  274. dev_info(&pdev->dev,
  275. "%s: %s NIC Link is Down\n",
  276. atl1c_driver_name, netdev->name);
  277. adapter->link_speed = SPEED_0;
  278. }
  279. }
  280. schedule_work(&adapter->link_chg_task);
  281. }
  282. static void atl1c_del_timer(struct atl1c_adapter *adapter)
  283. {
  284. del_timer_sync(&adapter->phy_config_timer);
  285. }
  286. static void atl1c_cancel_work(struct atl1c_adapter *adapter)
  287. {
  288. cancel_work_sync(&adapter->reset_task);
  289. cancel_work_sync(&adapter->link_chg_task);
  290. }
  291. /*
  292. * atl1c_tx_timeout - Respond to a Tx Hang
  293. * @netdev: network interface device structure
  294. */
  295. static void atl1c_tx_timeout(struct net_device *netdev)
  296. {
  297. struct atl1c_adapter *adapter = netdev_priv(netdev);
  298. /* Do the reset outside of interrupt context */
  299. schedule_work(&adapter->reset_task);
  300. }
  301. /*
  302. * atl1c_set_multi - Multicast and Promiscuous mode set
  303. * @netdev: network interface device structure
  304. *
  305. * The set_multi entry point is called whenever the multicast address
  306. * list or the network interface flags are updated. This routine is
  307. * responsible for configuring the hardware for proper multicast,
  308. * promiscuous mode, and all-multi behavior.
  309. */
  310. static void atl1c_set_multi(struct net_device *netdev)
  311. {
  312. struct atl1c_adapter *adapter = netdev_priv(netdev);
  313. struct atl1c_hw *hw = &adapter->hw;
  314. struct dev_mc_list *mc_ptr;
  315. u32 mac_ctrl_data;
  316. u32 hash_value;
  317. /* Check for Promiscuous and All Multicast modes */
  318. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  319. if (netdev->flags & IFF_PROMISC) {
  320. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  321. } else if (netdev->flags & IFF_ALLMULTI) {
  322. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  323. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  324. } else {
  325. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  326. }
  327. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  328. /* clear the old settings from the multicast hash table */
  329. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  330. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  331. /* comoute mc addresses' hash value ,and put it into hash table */
  332. for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
  333. hash_value = atl1c_hash_mc_addr(hw, mc_ptr->dmi_addr);
  334. atl1c_hash_set(hw, hash_value);
  335. }
  336. }
  337. static void atl1c_vlan_rx_register(struct net_device *netdev,
  338. struct vlan_group *grp)
  339. {
  340. struct atl1c_adapter *adapter = netdev_priv(netdev);
  341. struct pci_dev *pdev = adapter->pdev;
  342. u32 mac_ctrl_data = 0;
  343. if (netif_msg_pktdata(adapter))
  344. dev_dbg(&pdev->dev, "atl1c_vlan_rx_register\n");
  345. atl1c_irq_disable(adapter);
  346. adapter->vlgrp = grp;
  347. AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
  348. if (grp) {
  349. /* enable VLAN tag insert/strip */
  350. mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  351. } else {
  352. /* disable VLAN tag insert/strip */
  353. mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  354. }
  355. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  356. atl1c_irq_enable(adapter);
  357. }
  358. static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
  359. {
  360. struct pci_dev *pdev = adapter->pdev;
  361. if (netif_msg_pktdata(adapter))
  362. dev_dbg(&pdev->dev, "atl1c_restore_vlan !");
  363. atl1c_vlan_rx_register(adapter->netdev, adapter->vlgrp);
  364. }
  365. /*
  366. * atl1c_set_mac - Change the Ethernet Address of the NIC
  367. * @netdev: network interface device structure
  368. * @p: pointer to an address structure
  369. *
  370. * Returns 0 on success, negative on failure
  371. */
  372. static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
  373. {
  374. struct atl1c_adapter *adapter = netdev_priv(netdev);
  375. struct sockaddr *addr = p;
  376. if (!is_valid_ether_addr(addr->sa_data))
  377. return -EADDRNOTAVAIL;
  378. if (netif_running(netdev))
  379. return -EBUSY;
  380. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  381. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  382. atl1c_hw_set_mac_addr(&adapter->hw);
  383. return 0;
  384. }
  385. static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
  386. struct net_device *dev)
  387. {
  388. int mtu = dev->mtu;
  389. adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
  390. roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
  391. }
  392. /*
  393. * atl1c_change_mtu - Change the Maximum Transfer Unit
  394. * @netdev: network interface device structure
  395. * @new_mtu: new value for maximum frame size
  396. *
  397. * Returns 0 on success, negative on failure
  398. */
  399. static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
  400. {
  401. struct atl1c_adapter *adapter = netdev_priv(netdev);
  402. int old_mtu = netdev->mtu;
  403. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  404. if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
  405. (max_frame > MAX_JUMBO_FRAME_SIZE)) {
  406. if (netif_msg_link(adapter))
  407. dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
  408. return -EINVAL;
  409. }
  410. /* set MTU */
  411. if (old_mtu != new_mtu && netif_running(netdev)) {
  412. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  413. msleep(1);
  414. netdev->mtu = new_mtu;
  415. adapter->hw.max_frame_size = new_mtu;
  416. atl1c_set_rxbufsize(adapter, netdev);
  417. atl1c_down(adapter);
  418. atl1c_up(adapter);
  419. clear_bit(__AT_RESETTING, &adapter->flags);
  420. if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
  421. u32 phy_data;
  422. AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
  423. phy_data |= 0x10000000;
  424. AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
  425. }
  426. }
  427. return 0;
  428. }
  429. /*
  430. * caller should hold mdio_lock
  431. */
  432. static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  433. {
  434. struct atl1c_adapter *adapter = netdev_priv(netdev);
  435. u16 result;
  436. atl1c_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
  437. return result;
  438. }
  439. static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
  440. int reg_num, int val)
  441. {
  442. struct atl1c_adapter *adapter = netdev_priv(netdev);
  443. atl1c_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
  444. }
  445. /*
  446. * atl1c_mii_ioctl -
  447. * @netdev:
  448. * @ifreq:
  449. * @cmd:
  450. */
  451. static int atl1c_mii_ioctl(struct net_device *netdev,
  452. struct ifreq *ifr, int cmd)
  453. {
  454. struct atl1c_adapter *adapter = netdev_priv(netdev);
  455. struct pci_dev *pdev = adapter->pdev;
  456. struct mii_ioctl_data *data = if_mii(ifr);
  457. unsigned long flags;
  458. int retval = 0;
  459. if (!netif_running(netdev))
  460. return -EINVAL;
  461. spin_lock_irqsave(&adapter->mdio_lock, flags);
  462. switch (cmd) {
  463. case SIOCGMIIPHY:
  464. data->phy_id = 0;
  465. break;
  466. case SIOCGMIIREG:
  467. if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  468. &data->val_out)) {
  469. retval = -EIO;
  470. goto out;
  471. }
  472. break;
  473. case SIOCSMIIREG:
  474. if (data->reg_num & ~(0x1F)) {
  475. retval = -EFAULT;
  476. goto out;
  477. }
  478. dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
  479. data->reg_num, data->val_in);
  480. if (atl1c_write_phy_reg(&adapter->hw,
  481. data->reg_num, data->val_in)) {
  482. retval = -EIO;
  483. goto out;
  484. }
  485. break;
  486. default:
  487. retval = -EOPNOTSUPP;
  488. break;
  489. }
  490. out:
  491. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  492. return retval;
  493. }
  494. /*
  495. * atl1c_ioctl -
  496. * @netdev:
  497. * @ifreq:
  498. * @cmd:
  499. */
  500. static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  501. {
  502. switch (cmd) {
  503. case SIOCGMIIPHY:
  504. case SIOCGMIIREG:
  505. case SIOCSMIIREG:
  506. return atl1c_mii_ioctl(netdev, ifr, cmd);
  507. default:
  508. return -EOPNOTSUPP;
  509. }
  510. }
  511. /*
  512. * atl1c_alloc_queues - Allocate memory for all rings
  513. * @adapter: board private structure to initialize
  514. *
  515. */
  516. static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter)
  517. {
  518. return 0;
  519. }
  520. static void atl1c_set_mac_type(struct atl1c_hw *hw)
  521. {
  522. switch (hw->device_id) {
  523. case PCI_DEVICE_ID_ATTANSIC_L2C:
  524. hw->nic_type = athr_l2c;
  525. break;
  526. case PCI_DEVICE_ID_ATTANSIC_L1C:
  527. hw->nic_type = athr_l1c;
  528. break;
  529. default:
  530. break;
  531. }
  532. }
  533. static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
  534. {
  535. u32 phy_status_data;
  536. u32 link_ctrl_data;
  537. atl1c_set_mac_type(hw);
  538. AT_READ_REG(hw, REG_PHY_STATUS, &phy_status_data);
  539. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  540. hw->ctrl_flags = ATL1C_INTR_CLEAR_ON_READ |
  541. ATL1C_INTR_MODRT_ENABLE |
  542. ATL1C_RX_IPV6_CHKSUM |
  543. ATL1C_TXQ_MODE_ENHANCE;
  544. if (link_ctrl_data & LINK_CTRL_L0S_EN)
  545. hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT;
  546. if (link_ctrl_data & LINK_CTRL_L1_EN)
  547. hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT;
  548. if (hw->nic_type == athr_l1c) {
  549. hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
  550. hw->ctrl_flags |= ATL1C_LINK_CAP_1000M;
  551. }
  552. return 0;
  553. }
  554. /*
  555. * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  556. * @adapter: board private structure to initialize
  557. *
  558. * atl1c_sw_init initializes the Adapter private data structure.
  559. * Fields are initialized based on PCI device information and
  560. * OS network device settings (MTU size).
  561. */
  562. static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
  563. {
  564. struct atl1c_hw *hw = &adapter->hw;
  565. struct pci_dev *pdev = adapter->pdev;
  566. adapter->wol = 0;
  567. adapter->link_speed = SPEED_0;
  568. adapter->link_duplex = FULL_DUPLEX;
  569. adapter->num_rx_queues = AT_DEF_RECEIVE_QUEUE;
  570. adapter->tpd_ring[0].count = 1024;
  571. adapter->rfd_ring[0].count = 512;
  572. hw->vendor_id = pdev->vendor;
  573. hw->device_id = pdev->device;
  574. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  575. hw->subsystem_id = pdev->subsystem_device;
  576. /* before link up, we assume hibernate is true */
  577. hw->hibernate = true;
  578. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  579. if (atl1c_setup_mac_funcs(hw) != 0) {
  580. dev_err(&pdev->dev, "set mac function pointers failed\n");
  581. return -1;
  582. }
  583. hw->intr_mask = IMR_NORMAL_MASK;
  584. hw->phy_configured = false;
  585. hw->preamble_len = 7;
  586. hw->max_frame_size = adapter->netdev->mtu;
  587. if (adapter->num_rx_queues < 2) {
  588. hw->rss_type = atl1c_rss_disable;
  589. hw->rss_mode = atl1c_rss_mode_disable;
  590. } else {
  591. hw->rss_type = atl1c_rss_ipv4;
  592. hw->rss_mode = atl1c_rss_mul_que_mul_int;
  593. hw->rss_hash_bits = 16;
  594. }
  595. hw->autoneg_advertised = ADVERTISED_Autoneg;
  596. hw->indirect_tab = 0xE4E4E4E4;
  597. hw->base_cpu = 0;
  598. hw->ict = 50000; /* 100ms */
  599. hw->smb_timer = 200000; /* 400ms */
  600. hw->cmb_tpd = 4;
  601. hw->cmb_tx_timer = 1; /* 2 us */
  602. hw->rx_imt = 200;
  603. hw->tx_imt = 1000;
  604. hw->tpd_burst = 5;
  605. hw->rfd_burst = 8;
  606. hw->dma_order = atl1c_dma_ord_out;
  607. hw->dmar_block = atl1c_dma_req_1024;
  608. hw->dmaw_block = atl1c_dma_req_1024;
  609. hw->dmar_dly_cnt = 15;
  610. hw->dmaw_dly_cnt = 4;
  611. if (atl1c_alloc_queues(adapter)) {
  612. dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
  613. return -ENOMEM;
  614. }
  615. /* TODO */
  616. atl1c_set_rxbufsize(adapter, adapter->netdev);
  617. atomic_set(&adapter->irq_sem, 1);
  618. spin_lock_init(&adapter->mdio_lock);
  619. spin_lock_init(&adapter->tx_lock);
  620. set_bit(__AT_DOWN, &adapter->flags);
  621. return 0;
  622. }
  623. /*
  624. * atl1c_clean_tx_ring - Free Tx-skb
  625. * @adapter: board private structure
  626. */
  627. static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
  628. enum atl1c_trans_queue type)
  629. {
  630. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  631. struct atl1c_buffer *buffer_info;
  632. struct pci_dev *pdev = adapter->pdev;
  633. u16 index, ring_count;
  634. ring_count = tpd_ring->count;
  635. for (index = 0; index < ring_count; index++) {
  636. buffer_info = &tpd_ring->buffer_info[index];
  637. if (buffer_info->state == ATL1_BUFFER_FREE)
  638. continue;
  639. if (buffer_info->dma)
  640. pci_unmap_single(pdev, buffer_info->dma,
  641. buffer_info->length,
  642. PCI_DMA_TODEVICE);
  643. if (buffer_info->skb)
  644. dev_kfree_skb(buffer_info->skb);
  645. buffer_info->dma = 0;
  646. buffer_info->skb = NULL;
  647. buffer_info->state = ATL1_BUFFER_FREE;
  648. }
  649. /* Zero out Tx-buffers */
  650. memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
  651. ring_count);
  652. atomic_set(&tpd_ring->next_to_clean, 0);
  653. tpd_ring->next_to_use = 0;
  654. }
  655. /*
  656. * atl1c_clean_rx_ring - Free rx-reservation skbs
  657. * @adapter: board private structure
  658. */
  659. static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
  660. {
  661. struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
  662. struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
  663. struct atl1c_buffer *buffer_info;
  664. struct pci_dev *pdev = adapter->pdev;
  665. int i, j;
  666. for (i = 0; i < adapter->num_rx_queues; i++) {
  667. for (j = 0; j < rfd_ring[i].count; j++) {
  668. buffer_info = &rfd_ring[i].buffer_info[j];
  669. if (buffer_info->state == ATL1_BUFFER_FREE)
  670. continue;
  671. if (buffer_info->dma)
  672. pci_unmap_single(pdev, buffer_info->dma,
  673. buffer_info->length,
  674. PCI_DMA_FROMDEVICE);
  675. if (buffer_info->skb)
  676. dev_kfree_skb(buffer_info->skb);
  677. buffer_info->state = ATL1_BUFFER_FREE;
  678. buffer_info->skb = NULL;
  679. }
  680. /* zero out the descriptor ring */
  681. memset(rfd_ring[i].desc, 0, rfd_ring[i].size);
  682. rfd_ring[i].next_to_clean = 0;
  683. rfd_ring[i].next_to_use = 0;
  684. rrd_ring[i].next_to_use = 0;
  685. rrd_ring[i].next_to_clean = 0;
  686. }
  687. }
  688. /*
  689. * Read / Write Ptr Initialize:
  690. */
  691. static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
  692. {
  693. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  694. struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
  695. struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
  696. struct atl1c_buffer *buffer_info;
  697. int i, j;
  698. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  699. tpd_ring[i].next_to_use = 0;
  700. atomic_set(&tpd_ring[i].next_to_clean, 0);
  701. buffer_info = tpd_ring[i].buffer_info;
  702. for (j = 0; j < tpd_ring->count; j++)
  703. buffer_info[i].state = ATL1_BUFFER_FREE;
  704. }
  705. for (i = 0; i < adapter->num_rx_queues; i++) {
  706. rfd_ring[i].next_to_use = 0;
  707. rfd_ring[i].next_to_clean = 0;
  708. rrd_ring[i].next_to_use = 0;
  709. rrd_ring[i].next_to_clean = 0;
  710. for (j = 0; j < rfd_ring[i].count; j++) {
  711. buffer_info = &rfd_ring[i].buffer_info[j];
  712. buffer_info->state = ATL1_BUFFER_FREE;
  713. }
  714. }
  715. }
  716. /*
  717. * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
  718. * @adapter: board private structure
  719. *
  720. * Free all transmit software resources
  721. */
  722. static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
  723. {
  724. struct pci_dev *pdev = adapter->pdev;
  725. pci_free_consistent(pdev, adapter->ring_header.size,
  726. adapter->ring_header.desc,
  727. adapter->ring_header.dma);
  728. adapter->ring_header.desc = NULL;
  729. /* Note: just free tdp_ring.buffer_info,
  730. * it contain rfd_ring.buffer_info, do not double free */
  731. if (adapter->tpd_ring[0].buffer_info) {
  732. kfree(adapter->tpd_ring[0].buffer_info);
  733. adapter->tpd_ring[0].buffer_info = NULL;
  734. }
  735. }
  736. /*
  737. * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
  738. * @adapter: board private structure
  739. *
  740. * Return 0 on success, negative on failure
  741. */
  742. static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
  743. {
  744. struct pci_dev *pdev = adapter->pdev;
  745. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  746. struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
  747. struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
  748. struct atl1c_ring_header *ring_header = &adapter->ring_header;
  749. int num_rx_queues = adapter->num_rx_queues;
  750. int size;
  751. int i;
  752. int count = 0;
  753. int rx_desc_count = 0;
  754. u32 offset = 0;
  755. rrd_ring[0].count = rfd_ring[0].count;
  756. for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
  757. tpd_ring[i].count = tpd_ring[0].count;
  758. for (i = 1; i < adapter->num_rx_queues; i++)
  759. rfd_ring[i].count = rrd_ring[i].count = rfd_ring[0].count;
  760. /* 2 tpd queue, one high priority queue,
  761. * another normal priority queue */
  762. size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
  763. rfd_ring->count * num_rx_queues);
  764. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  765. if (unlikely(!tpd_ring->buffer_info)) {
  766. dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
  767. size);
  768. goto err_nomem;
  769. }
  770. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  771. tpd_ring[i].buffer_info =
  772. (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
  773. count += tpd_ring[i].count;
  774. }
  775. for (i = 0; i < num_rx_queues; i++) {
  776. rfd_ring[i].buffer_info =
  777. (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
  778. count += rfd_ring[i].count;
  779. rx_desc_count += rfd_ring[i].count;
  780. }
  781. /*
  782. * real ring DMA buffer
  783. * each ring/block may need up to 8 bytes for alignment, hence the
  784. * additional bytes tacked onto the end.
  785. */
  786. ring_header->size = size =
  787. sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
  788. sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
  789. sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
  790. sizeof(struct atl1c_hw_stats) +
  791. 8 * 4 + 8 * 2 * num_rx_queues;
  792. ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
  793. &ring_header->dma);
  794. if (unlikely(!ring_header->desc)) {
  795. dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
  796. goto err_nomem;
  797. }
  798. memset(ring_header->desc, 0, ring_header->size);
  799. /* init TPD ring */
  800. tpd_ring[0].dma = roundup(ring_header->dma, 8);
  801. offset = tpd_ring[0].dma - ring_header->dma;
  802. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  803. tpd_ring[i].dma = ring_header->dma + offset;
  804. tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
  805. tpd_ring[i].size =
  806. sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
  807. offset += roundup(tpd_ring[i].size, 8);
  808. }
  809. /* init RFD ring */
  810. for (i = 0; i < num_rx_queues; i++) {
  811. rfd_ring[i].dma = ring_header->dma + offset;
  812. rfd_ring[i].desc = (u8 *) ring_header->desc + offset;
  813. rfd_ring[i].size = sizeof(struct atl1c_rx_free_desc) *
  814. rfd_ring[i].count;
  815. offset += roundup(rfd_ring[i].size, 8);
  816. }
  817. /* init RRD ring */
  818. for (i = 0; i < num_rx_queues; i++) {
  819. rrd_ring[i].dma = ring_header->dma + offset;
  820. rrd_ring[i].desc = (u8 *) ring_header->desc + offset;
  821. rrd_ring[i].size = sizeof(struct atl1c_recv_ret_status) *
  822. rrd_ring[i].count;
  823. offset += roundup(rrd_ring[i].size, 8);
  824. }
  825. adapter->smb.dma = ring_header->dma + offset;
  826. adapter->smb.smb = (u8 *)ring_header->desc + offset;
  827. return 0;
  828. err_nomem:
  829. kfree(tpd_ring->buffer_info);
  830. return -ENOMEM;
  831. }
  832. static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
  833. {
  834. struct atl1c_hw *hw = &adapter->hw;
  835. struct atl1c_rfd_ring *rfd_ring = (struct atl1c_rfd_ring *)
  836. adapter->rfd_ring;
  837. struct atl1c_rrd_ring *rrd_ring = (struct atl1c_rrd_ring *)
  838. adapter->rrd_ring;
  839. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  840. adapter->tpd_ring;
  841. struct atl1c_cmb *cmb = (struct atl1c_cmb *) &adapter->cmb;
  842. struct atl1c_smb *smb = (struct atl1c_smb *) &adapter->smb;
  843. int i;
  844. /* TPD */
  845. AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
  846. (u32)((tpd_ring[atl1c_trans_normal].dma &
  847. AT_DMA_HI_ADDR_MASK) >> 32));
  848. /* just enable normal priority TX queue */
  849. AT_WRITE_REG(hw, REG_NTPD_HEAD_ADDR_LO,
  850. (u32)(tpd_ring[atl1c_trans_normal].dma &
  851. AT_DMA_LO_ADDR_MASK));
  852. AT_WRITE_REG(hw, REG_HTPD_HEAD_ADDR_LO,
  853. (u32)(tpd_ring[atl1c_trans_high].dma &
  854. AT_DMA_LO_ADDR_MASK));
  855. AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
  856. (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
  857. /* RFD */
  858. AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
  859. (u32)((rfd_ring[0].dma & AT_DMA_HI_ADDR_MASK) >> 32));
  860. for (i = 0; i < adapter->num_rx_queues; i++)
  861. AT_WRITE_REG(hw, atl1c_rfd_addr_lo_regs[i],
  862. (u32)(rfd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
  863. AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
  864. rfd_ring[0].count & RFD_RING_SIZE_MASK);
  865. AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
  866. adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
  867. /* RRD */
  868. for (i = 0; i < adapter->num_rx_queues; i++)
  869. AT_WRITE_REG(hw, atl1c_rrd_addr_lo_regs[i],
  870. (u32)(rrd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
  871. AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
  872. (rrd_ring[0].count & RRD_RING_SIZE_MASK));
  873. /* CMB */
  874. AT_WRITE_REG(hw, REG_CMB_BASE_ADDR_LO, cmb->dma & AT_DMA_LO_ADDR_MASK);
  875. /* SMB */
  876. AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_HI,
  877. (u32)((smb->dma & AT_DMA_HI_ADDR_MASK) >> 32));
  878. AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_LO,
  879. (u32)(smb->dma & AT_DMA_LO_ADDR_MASK));
  880. /* Load all of base address above */
  881. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  882. }
  883. static void atl1c_configure_tx(struct atl1c_adapter *adapter)
  884. {
  885. struct atl1c_hw *hw = &adapter->hw;
  886. u32 dev_ctrl_data;
  887. u32 max_pay_load;
  888. u16 tx_offload_thresh;
  889. u32 txq_ctrl_data;
  890. u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
  891. extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
  892. tx_offload_thresh = MAX_TX_OFFLOAD_THRESH;
  893. AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
  894. (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
  895. AT_READ_REG(hw, REG_DEVICE_CTRL, &dev_ctrl_data);
  896. max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT) &
  897. DEVICE_CTRL_MAX_PAYLOAD_MASK;
  898. hw->dmaw_block = min(max_pay_load, hw->dmaw_block);
  899. max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT) &
  900. DEVICE_CTRL_MAX_RREQ_SZ_MASK;
  901. hw->dmar_block = min(max_pay_load, hw->dmar_block);
  902. txq_ctrl_data = (hw->tpd_burst & TXQ_NUM_TPD_BURST_MASK) <<
  903. TXQ_NUM_TPD_BURST_SHIFT;
  904. if (hw->ctrl_flags & ATL1C_TXQ_MODE_ENHANCE)
  905. txq_ctrl_data |= TXQ_CTRL_ENH_MODE;
  906. txq_ctrl_data |= (atl1c_pay_load_size[hw->dmar_block] &
  907. TXQ_TXF_BURST_NUM_MASK) << TXQ_TXF_BURST_NUM_SHIFT;
  908. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
  909. }
  910. static void atl1c_configure_rx(struct atl1c_adapter *adapter)
  911. {
  912. struct atl1c_hw *hw = &adapter->hw;
  913. u32 rxq_ctrl_data;
  914. rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
  915. RXQ_RFD_BURST_NUM_SHIFT;
  916. if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
  917. rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
  918. if (hw->rss_type == atl1c_rss_ipv4)
  919. rxq_ctrl_data |= RSS_HASH_IPV4;
  920. if (hw->rss_type == atl1c_rss_ipv4_tcp)
  921. rxq_ctrl_data |= RSS_HASH_IPV4_TCP;
  922. if (hw->rss_type == atl1c_rss_ipv6)
  923. rxq_ctrl_data |= RSS_HASH_IPV6;
  924. if (hw->rss_type == atl1c_rss_ipv6_tcp)
  925. rxq_ctrl_data |= RSS_HASH_IPV6_TCP;
  926. if (hw->rss_type != atl1c_rss_disable)
  927. rxq_ctrl_data |= RRS_HASH_CTRL_EN;
  928. rxq_ctrl_data |= (hw->rss_mode & RSS_MODE_MASK) <<
  929. RSS_MODE_SHIFT;
  930. rxq_ctrl_data |= (hw->rss_hash_bits & RSS_HASH_BITS_MASK) <<
  931. RSS_HASH_BITS_SHIFT;
  932. if (hw->ctrl_flags & ATL1C_ASPM_CTRL_MON)
  933. rxq_ctrl_data |= (ASPM_THRUPUT_LIMIT_100M &
  934. ASPM_THRUPUT_LIMIT_MASK) << ASPM_THRUPUT_LIMIT_SHIFT;
  935. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  936. }
  937. static void atl1c_configure_rss(struct atl1c_adapter *adapter)
  938. {
  939. struct atl1c_hw *hw = &adapter->hw;
  940. AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
  941. AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
  942. }
  943. static void atl1c_configure_dma(struct atl1c_adapter *adapter)
  944. {
  945. struct atl1c_hw *hw = &adapter->hw;
  946. u32 dma_ctrl_data;
  947. dma_ctrl_data = DMA_CTRL_DMAR_REQ_PRI;
  948. if (hw->ctrl_flags & ATL1C_CMB_ENABLE)
  949. dma_ctrl_data |= DMA_CTRL_CMB_EN;
  950. if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
  951. dma_ctrl_data |= DMA_CTRL_SMB_EN;
  952. else
  953. dma_ctrl_data |= MAC_CTRL_SMB_DIS;
  954. switch (hw->dma_order) {
  955. case atl1c_dma_ord_in:
  956. dma_ctrl_data |= DMA_CTRL_DMAR_IN_ORDER;
  957. break;
  958. case atl1c_dma_ord_enh:
  959. dma_ctrl_data |= DMA_CTRL_DMAR_ENH_ORDER;
  960. break;
  961. case atl1c_dma_ord_out:
  962. dma_ctrl_data |= DMA_CTRL_DMAR_OUT_ORDER;
  963. break;
  964. default:
  965. break;
  966. }
  967. dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
  968. << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
  969. dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
  970. << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
  971. dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
  972. << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
  973. dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
  974. << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
  975. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  976. }
  977. /*
  978. * Stop the mac, transmit and receive units
  979. * hw - Struct containing variables accessed by shared code
  980. * return : 0 or idle status (if error)
  981. */
  982. static int atl1c_stop_mac(struct atl1c_hw *hw)
  983. {
  984. u32 data;
  985. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  986. data &= ~(RXQ1_CTRL_EN | RXQ2_CTRL_EN |
  987. RXQ3_CTRL_EN | RXQ_CTRL_EN);
  988. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  989. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  990. data &= ~TXQ_CTRL_EN;
  991. AT_WRITE_REG(hw, REG_TWSI_CTRL, data);
  992. atl1c_wait_until_idle(hw);
  993. AT_READ_REG(hw, REG_MAC_CTRL, &data);
  994. data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
  995. AT_WRITE_REG(hw, REG_MAC_CTRL, data);
  996. return (int)atl1c_wait_until_idle(hw);
  997. }
  998. static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw)
  999. {
  1000. u32 data;
  1001. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  1002. switch (hw->adapter->num_rx_queues) {
  1003. case 4:
  1004. data |= (RXQ3_CTRL_EN | RXQ2_CTRL_EN | RXQ1_CTRL_EN);
  1005. break;
  1006. case 3:
  1007. data |= (RXQ2_CTRL_EN | RXQ1_CTRL_EN);
  1008. break;
  1009. case 2:
  1010. data |= RXQ1_CTRL_EN;
  1011. break;
  1012. default:
  1013. break;
  1014. }
  1015. data |= RXQ_CTRL_EN;
  1016. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  1017. }
  1018. static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw)
  1019. {
  1020. u32 data;
  1021. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  1022. data |= TXQ_CTRL_EN;
  1023. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  1024. }
  1025. /*
  1026. * Reset the transmit and receive units; mask and clear all interrupts.
  1027. * hw - Struct containing variables accessed by shared code
  1028. * return : 0 or idle status (if error)
  1029. */
  1030. static int atl1c_reset_mac(struct atl1c_hw *hw)
  1031. {
  1032. struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
  1033. struct pci_dev *pdev = adapter->pdev;
  1034. int ret;
  1035. AT_WRITE_REG(hw, REG_IMR, 0);
  1036. AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
  1037. ret = atl1c_stop_mac(hw);
  1038. if (ret)
  1039. return ret;
  1040. /*
  1041. * Issue Soft Reset to the MAC. This will reset the chip's
  1042. * transmit, receive, DMA. It will not effect
  1043. * the current PCI configuration. The global reset bit is self-
  1044. * clearing, and should clear within a microsecond.
  1045. */
  1046. AT_WRITE_REGW(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
  1047. AT_WRITE_FLUSH(hw);
  1048. msleep(10);
  1049. /* Wait at least 10ms for All module to be Idle */
  1050. if (atl1c_wait_until_idle(hw)) {
  1051. dev_err(&pdev->dev,
  1052. "MAC state machine can't be idle since"
  1053. " disabled for 10ms second\n");
  1054. return -1;
  1055. }
  1056. return 0;
  1057. }
  1058. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
  1059. {
  1060. u32 pm_ctrl_data;
  1061. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1062. pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
  1063. PM_CTRL_L1_ENTRY_TIMER_SHIFT);
  1064. pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
  1065. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1066. pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
  1067. pm_ctrl_data &= ~PM_CTRL_MAC_ASPM_CHK;
  1068. pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
  1069. pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
  1070. pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
  1071. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
  1072. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1073. }
  1074. /*
  1075. * Set ASPM state.
  1076. * Enable/disable L0s/L1 depend on link state.
  1077. */
  1078. static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup)
  1079. {
  1080. u32 pm_ctrl_data;
  1081. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1082. pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
  1083. pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
  1084. PM_CTRL_L1_ENTRY_TIMER_SHIFT);
  1085. pm_ctrl_data |= PM_CTRL_MAC_ASPM_CHK;
  1086. if (linkup) {
  1087. pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
  1088. pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
  1089. pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
  1090. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
  1091. } else {
  1092. pm_ctrl_data &= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
  1093. pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
  1094. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1095. pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
  1096. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1097. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1098. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
  1099. else
  1100. pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
  1101. }
  1102. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1103. }
  1104. static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
  1105. {
  1106. struct atl1c_hw *hw = &adapter->hw;
  1107. struct net_device *netdev = adapter->netdev;
  1108. u32 mac_ctrl_data;
  1109. mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
  1110. mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
  1111. if (adapter->link_duplex == FULL_DUPLEX) {
  1112. hw->mac_duplex = true;
  1113. mac_ctrl_data |= MAC_CTRL_DUPLX;
  1114. }
  1115. if (adapter->link_speed == SPEED_1000)
  1116. hw->mac_speed = atl1c_mac_speed_1000;
  1117. else
  1118. hw->mac_speed = atl1c_mac_speed_10_100;
  1119. mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) <<
  1120. MAC_CTRL_SPEED_SHIFT;
  1121. mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
  1122. mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) <<
  1123. MAC_CTRL_PRMLEN_SHIFT);
  1124. if (adapter->vlgrp)
  1125. mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  1126. mac_ctrl_data |= MAC_CTRL_BC_EN;
  1127. if (netdev->flags & IFF_PROMISC)
  1128. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  1129. if (netdev->flags & IFF_ALLMULTI)
  1130. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  1131. mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
  1132. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  1133. }
  1134. /*
  1135. * atl1c_configure - Configure Transmit&Receive Unit after Reset
  1136. * @adapter: board private structure
  1137. *
  1138. * Configure the Tx /Rx unit of the MAC after a reset.
  1139. */
  1140. static int atl1c_configure(struct atl1c_adapter *adapter)
  1141. {
  1142. struct atl1c_hw *hw = &adapter->hw;
  1143. u32 master_ctrl_data = 0;
  1144. u32 intr_modrt_data;
  1145. /* clear interrupt status */
  1146. AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
  1147. /* Clear any WOL status */
  1148. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1149. /* set Interrupt Clear Timer
  1150. * HW will enable self to assert interrupt event to system after
  1151. * waiting x-time for software to notify it accept interrupt.
  1152. */
  1153. AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
  1154. hw->ict & INT_RETRIG_TIMER_MASK);
  1155. atl1c_configure_des_ring(adapter);
  1156. if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
  1157. intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
  1158. IRQ_MODRT_TX_TIMER_SHIFT;
  1159. intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
  1160. IRQ_MODRT_RX_TIMER_SHIFT;
  1161. AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
  1162. master_ctrl_data |=
  1163. MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
  1164. }
  1165. if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
  1166. master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
  1167. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  1168. if (hw->ctrl_flags & ATL1C_CMB_ENABLE) {
  1169. AT_WRITE_REG(hw, REG_CMB_TPD_THRESH,
  1170. hw->cmb_tpd & CMB_TPD_THRESH_MASK);
  1171. AT_WRITE_REG(hw, REG_CMB_TX_TIMER,
  1172. hw->cmb_tx_timer & CMB_TX_TIMER_MASK);
  1173. }
  1174. if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
  1175. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
  1176. hw->smb_timer & SMB_STAT_TIMER_MASK);
  1177. /* set MTU */
  1178. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  1179. VLAN_HLEN + ETH_FCS_LEN);
  1180. /* HDS, disable */
  1181. AT_WRITE_REG(hw, REG_HDS_CTRL, 0);
  1182. atl1c_configure_tx(adapter);
  1183. atl1c_configure_rx(adapter);
  1184. atl1c_configure_rss(adapter);
  1185. atl1c_configure_dma(adapter);
  1186. return 0;
  1187. }
  1188. static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
  1189. {
  1190. u16 hw_reg_addr = 0;
  1191. unsigned long *stats_item = NULL;
  1192. u32 data;
  1193. /* update rx status */
  1194. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1195. stats_item = &adapter->hw_stats.rx_ok;
  1196. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1197. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1198. *stats_item += data;
  1199. stats_item++;
  1200. hw_reg_addr += 4;
  1201. }
  1202. /* update tx status */
  1203. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1204. stats_item = &adapter->hw_stats.tx_ok;
  1205. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1206. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1207. *stats_item += data;
  1208. stats_item++;
  1209. hw_reg_addr += 4;
  1210. }
  1211. }
  1212. /*
  1213. * atl1c_get_stats - Get System Network Statistics
  1214. * @netdev: network interface device structure
  1215. *
  1216. * Returns the address of the device statistics structure.
  1217. * The statistics are actually updated from the timer callback.
  1218. */
  1219. static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
  1220. {
  1221. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1222. struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
  1223. struct net_device_stats *net_stats = &adapter->net_stats;
  1224. atl1c_update_hw_stats(adapter);
  1225. net_stats->rx_packets = hw_stats->rx_ok;
  1226. net_stats->tx_packets = hw_stats->tx_ok;
  1227. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  1228. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  1229. net_stats->multicast = hw_stats->rx_mcast;
  1230. net_stats->collisions = hw_stats->tx_1_col +
  1231. hw_stats->tx_2_col * 2 +
  1232. hw_stats->tx_late_col + hw_stats->tx_abort_col;
  1233. net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
  1234. hw_stats->rx_len_err + hw_stats->rx_sz_ov +
  1235. hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
  1236. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1237. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1238. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1239. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1240. net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1241. net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1242. net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
  1243. hw_stats->tx_underrun + hw_stats->tx_trunc;
  1244. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1245. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1246. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1247. return &adapter->net_stats;
  1248. }
  1249. static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
  1250. {
  1251. u16 phy_data;
  1252. spin_lock(&adapter->mdio_lock);
  1253. atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
  1254. spin_unlock(&adapter->mdio_lock);
  1255. }
  1256. static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
  1257. enum atl1c_trans_queue type)
  1258. {
  1259. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  1260. &adapter->tpd_ring[type];
  1261. struct atl1c_buffer *buffer_info;
  1262. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1263. u16 hw_next_to_clean;
  1264. u16 shift;
  1265. u32 data;
  1266. if (type == atl1c_trans_high)
  1267. shift = MB_HTPD_CONS_IDX_SHIFT;
  1268. else
  1269. shift = MB_NTPD_CONS_IDX_SHIFT;
  1270. AT_READ_REG(&adapter->hw, REG_MB_PRIO_CONS_IDX, &data);
  1271. hw_next_to_clean = (data >> shift) & MB_PRIO_PROD_IDX_MASK;
  1272. while (next_to_clean != hw_next_to_clean) {
  1273. buffer_info = &tpd_ring->buffer_info[next_to_clean];
  1274. if (buffer_info->state == ATL1_BUFFER_BUSY) {
  1275. pci_unmap_page(adapter->pdev, buffer_info->dma,
  1276. buffer_info->length, PCI_DMA_TODEVICE);
  1277. buffer_info->dma = 0;
  1278. if (buffer_info->skb) {
  1279. dev_kfree_skb_irq(buffer_info->skb);
  1280. buffer_info->skb = NULL;
  1281. }
  1282. buffer_info->state = ATL1_BUFFER_FREE;
  1283. }
  1284. if (++next_to_clean == tpd_ring->count)
  1285. next_to_clean = 0;
  1286. atomic_set(&tpd_ring->next_to_clean, next_to_clean);
  1287. }
  1288. if (netif_queue_stopped(adapter->netdev) &&
  1289. netif_carrier_ok(adapter->netdev)) {
  1290. netif_wake_queue(adapter->netdev);
  1291. }
  1292. return true;
  1293. }
  1294. /*
  1295. * atl1c_intr - Interrupt Handler
  1296. * @irq: interrupt number
  1297. * @data: pointer to a network interface device structure
  1298. * @pt_regs: CPU registers structure
  1299. */
  1300. static irqreturn_t atl1c_intr(int irq, void *data)
  1301. {
  1302. struct net_device *netdev = data;
  1303. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1304. struct pci_dev *pdev = adapter->pdev;
  1305. struct atl1c_hw *hw = &adapter->hw;
  1306. int max_ints = AT_MAX_INT_WORK;
  1307. int handled = IRQ_NONE;
  1308. u32 status;
  1309. u32 reg_data;
  1310. do {
  1311. AT_READ_REG(hw, REG_ISR, &reg_data);
  1312. status = reg_data & hw->intr_mask;
  1313. if (status == 0 || (status & ISR_DIS_INT) != 0) {
  1314. if (max_ints != AT_MAX_INT_WORK)
  1315. handled = IRQ_HANDLED;
  1316. break;
  1317. }
  1318. /* link event */
  1319. if (status & ISR_GPHY)
  1320. atl1c_clear_phy_int(adapter);
  1321. /* Ack ISR */
  1322. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1323. if (status & ISR_RX_PKT) {
  1324. if (likely(napi_schedule_prep(&adapter->napi))) {
  1325. hw->intr_mask &= ~ISR_RX_PKT;
  1326. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1327. __napi_schedule(&adapter->napi);
  1328. }
  1329. }
  1330. if (status & ISR_TX_PKT)
  1331. atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
  1332. handled = IRQ_HANDLED;
  1333. /* check if PCIE PHY Link down */
  1334. if (status & ISR_ERROR) {
  1335. if (netif_msg_hw(adapter))
  1336. dev_err(&pdev->dev,
  1337. "atl1c hardware error (status = 0x%x)\n",
  1338. status & ISR_ERROR);
  1339. /* reset MAC */
  1340. hw->intr_mask &= ~ISR_ERROR;
  1341. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1342. schedule_work(&adapter->reset_task);
  1343. break;
  1344. }
  1345. if (status & ISR_OVER)
  1346. if (netif_msg_intr(adapter))
  1347. dev_warn(&pdev->dev,
  1348. "TX/RX over flow (status = 0x%x)\n",
  1349. status & ISR_OVER);
  1350. /* link event */
  1351. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1352. adapter->net_stats.tx_carrier_errors++;
  1353. atl1c_link_chg_event(adapter);
  1354. break;
  1355. }
  1356. } while (--max_ints > 0);
  1357. /* re-enable Interrupt*/
  1358. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1359. return handled;
  1360. }
  1361. static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
  1362. struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
  1363. {
  1364. /*
  1365. * The pid field in RRS in not correct sometimes, so we
  1366. * cannot figure out if the packet is fragmented or not,
  1367. * so we tell the KERNEL CHECKSUM_NONE
  1368. */
  1369. skb->ip_summed = CHECKSUM_NONE;
  1370. }
  1371. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter, const int ringid)
  1372. {
  1373. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[ringid];
  1374. struct pci_dev *pdev = adapter->pdev;
  1375. struct atl1c_buffer *buffer_info, *next_info;
  1376. struct sk_buff *skb;
  1377. void *vir_addr = NULL;
  1378. u16 num_alloc = 0;
  1379. u16 rfd_next_to_use, next_next;
  1380. struct atl1c_rx_free_desc *rfd_desc;
  1381. next_next = rfd_next_to_use = rfd_ring->next_to_use;
  1382. if (++next_next == rfd_ring->count)
  1383. next_next = 0;
  1384. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1385. next_info = &rfd_ring->buffer_info[next_next];
  1386. while (next_info->state == ATL1_BUFFER_FREE) {
  1387. rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
  1388. skb = dev_alloc_skb(adapter->rx_buffer_len);
  1389. if (unlikely(!skb)) {
  1390. if (netif_msg_rx_err(adapter))
  1391. dev_warn(&pdev->dev, "alloc rx buffer failed\n");
  1392. break;
  1393. }
  1394. /*
  1395. * Make buffer alignment 2 beyond a 16 byte boundary
  1396. * this will result in a 16 byte aligned IP header after
  1397. * the 14 byte MAC header is removed
  1398. */
  1399. vir_addr = skb->data;
  1400. buffer_info->state = ATL1_BUFFER_BUSY;
  1401. buffer_info->skb = skb;
  1402. buffer_info->length = adapter->rx_buffer_len;
  1403. buffer_info->dma = pci_map_single(pdev, vir_addr,
  1404. buffer_info->length,
  1405. PCI_DMA_FROMDEVICE);
  1406. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1407. rfd_next_to_use = next_next;
  1408. if (++next_next == rfd_ring->count)
  1409. next_next = 0;
  1410. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1411. next_info = &rfd_ring->buffer_info[next_next];
  1412. num_alloc++;
  1413. }
  1414. if (num_alloc) {
  1415. /* TODO: update mailbox here */
  1416. wmb();
  1417. rfd_ring->next_to_use = rfd_next_to_use;
  1418. AT_WRITE_REG(&adapter->hw, atl1c_rfd_prod_idx_regs[ringid],
  1419. rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
  1420. }
  1421. return num_alloc;
  1422. }
  1423. static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
  1424. struct atl1c_recv_ret_status *rrs, u16 num)
  1425. {
  1426. u16 i;
  1427. /* the relationship between rrd and rfd is one map one */
  1428. for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
  1429. rrd_ring->next_to_clean)) {
  1430. rrs->word3 &= ~RRS_RXD_UPDATED;
  1431. if (++rrd_ring->next_to_clean == rrd_ring->count)
  1432. rrd_ring->next_to_clean = 0;
  1433. }
  1434. }
  1435. static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
  1436. struct atl1c_recv_ret_status *rrs, u16 num)
  1437. {
  1438. u16 i;
  1439. u16 rfd_index;
  1440. struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
  1441. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1442. RRS_RX_RFD_INDEX_MASK;
  1443. for (i = 0; i < num; i++) {
  1444. buffer_info[rfd_index].skb = NULL;
  1445. buffer_info[rfd_index].state = ATL1_BUFFER_FREE;
  1446. if (++rfd_index == rfd_ring->count)
  1447. rfd_index = 0;
  1448. }
  1449. rfd_ring->next_to_clean = rfd_index;
  1450. }
  1451. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
  1452. int *work_done, int work_to_do)
  1453. {
  1454. u16 rfd_num, rfd_index;
  1455. u16 count = 0;
  1456. u16 length;
  1457. struct pci_dev *pdev = adapter->pdev;
  1458. struct net_device *netdev = adapter->netdev;
  1459. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[que];
  1460. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring[que];
  1461. struct sk_buff *skb;
  1462. struct atl1c_recv_ret_status *rrs;
  1463. struct atl1c_buffer *buffer_info;
  1464. while (1) {
  1465. if (*work_done >= work_to_do)
  1466. break;
  1467. rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
  1468. if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
  1469. rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
  1470. RRS_RX_RFD_CNT_MASK;
  1471. if (unlikely(rfd_num != 1))
  1472. /* TODO support mul rfd*/
  1473. if (netif_msg_rx_err(adapter))
  1474. dev_warn(&pdev->dev,
  1475. "Multi rfd not support yet!\n");
  1476. goto rrs_checked;
  1477. } else {
  1478. break;
  1479. }
  1480. rrs_checked:
  1481. atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
  1482. if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
  1483. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1484. if (netif_msg_rx_err(adapter))
  1485. dev_warn(&pdev->dev,
  1486. "wrong packet! rrs word3 is %x\n",
  1487. rrs->word3);
  1488. continue;
  1489. }
  1490. length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
  1491. RRS_PKT_SIZE_MASK);
  1492. /* Good Receive */
  1493. if (likely(rfd_num == 1)) {
  1494. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1495. RRS_RX_RFD_INDEX_MASK;
  1496. buffer_info = &rfd_ring->buffer_info[rfd_index];
  1497. pci_unmap_single(pdev, buffer_info->dma,
  1498. buffer_info->length, PCI_DMA_FROMDEVICE);
  1499. skb = buffer_info->skb;
  1500. } else {
  1501. /* TODO */
  1502. if (netif_msg_rx_err(adapter))
  1503. dev_warn(&pdev->dev,
  1504. "Multi rfd not support yet!\n");
  1505. break;
  1506. }
  1507. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1508. skb_put(skb, length - ETH_FCS_LEN);
  1509. skb->protocol = eth_type_trans(skb, netdev);
  1510. skb->dev = netdev;
  1511. atl1c_rx_checksum(adapter, skb, rrs);
  1512. if (unlikely(adapter->vlgrp) && rrs->word3 & RRS_VLAN_INS) {
  1513. u16 vlan;
  1514. AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
  1515. vlan = le16_to_cpu(vlan);
  1516. vlan_hwaccel_receive_skb(skb, adapter->vlgrp, vlan);
  1517. } else
  1518. netif_receive_skb(skb);
  1519. (*work_done)++;
  1520. count++;
  1521. }
  1522. if (count)
  1523. atl1c_alloc_rx_buffer(adapter, que);
  1524. }
  1525. /*
  1526. * atl1c_clean - NAPI Rx polling callback
  1527. * @adapter: board private structure
  1528. */
  1529. static int atl1c_clean(struct napi_struct *napi, int budget)
  1530. {
  1531. struct atl1c_adapter *adapter =
  1532. container_of(napi, struct atl1c_adapter, napi);
  1533. int work_done = 0;
  1534. /* Keep link state information with original netdev */
  1535. if (!netif_carrier_ok(adapter->netdev))
  1536. goto quit_polling;
  1537. /* just enable one RXQ */
  1538. atl1c_clean_rx_irq(adapter, 0, &work_done, budget);
  1539. if (work_done < budget) {
  1540. quit_polling:
  1541. napi_complete(napi);
  1542. adapter->hw.intr_mask |= ISR_RX_PKT;
  1543. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  1544. }
  1545. return work_done;
  1546. }
  1547. #ifdef CONFIG_NET_POLL_CONTROLLER
  1548. /*
  1549. * Polling 'interrupt' - used by things like netconsole to send skbs
  1550. * without having to re-enable interrupts. It's not called while
  1551. * the interrupt routine is executing.
  1552. */
  1553. static void atl1c_netpoll(struct net_device *netdev)
  1554. {
  1555. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1556. disable_irq(adapter->pdev->irq);
  1557. atl1c_intr(adapter->pdev->irq, netdev);
  1558. enable_irq(adapter->pdev->irq);
  1559. }
  1560. #endif
  1561. static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
  1562. {
  1563. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1564. u16 next_to_use = 0;
  1565. u16 next_to_clean = 0;
  1566. next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1567. next_to_use = tpd_ring->next_to_use;
  1568. return (u16)(next_to_clean > next_to_use) ?
  1569. (next_to_clean - next_to_use - 1) :
  1570. (tpd_ring->count + next_to_clean - next_to_use - 1);
  1571. }
  1572. /*
  1573. * get next usable tpd
  1574. * Note: should call atl1c_tdp_avail to make sure
  1575. * there is enough tpd to use
  1576. */
  1577. static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
  1578. enum atl1c_trans_queue type)
  1579. {
  1580. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1581. struct atl1c_tpd_desc *tpd_desc;
  1582. u16 next_to_use = 0;
  1583. next_to_use = tpd_ring->next_to_use;
  1584. if (++tpd_ring->next_to_use == tpd_ring->count)
  1585. tpd_ring->next_to_use = 0;
  1586. tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
  1587. memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
  1588. return tpd_desc;
  1589. }
  1590. static struct atl1c_buffer *
  1591. atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
  1592. {
  1593. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  1594. return &tpd_ring->buffer_info[tpd -
  1595. (struct atl1c_tpd_desc *)tpd_ring->desc];
  1596. }
  1597. /* Calculate the transmit packet descript needed*/
  1598. static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
  1599. {
  1600. u16 tpd_req;
  1601. u16 proto_hdr_len = 0;
  1602. tpd_req = skb_shinfo(skb)->nr_frags + 1;
  1603. if (skb_is_gso(skb)) {
  1604. proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1605. if (proto_hdr_len < skb_headlen(skb))
  1606. tpd_req++;
  1607. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  1608. tpd_req++;
  1609. }
  1610. return tpd_req;
  1611. }
  1612. static int atl1c_tso_csum(struct atl1c_adapter *adapter,
  1613. struct sk_buff *skb,
  1614. struct atl1c_tpd_desc **tpd,
  1615. enum atl1c_trans_queue type)
  1616. {
  1617. struct pci_dev *pdev = adapter->pdev;
  1618. u8 hdr_len;
  1619. u32 real_len;
  1620. unsigned short offload_type;
  1621. int err;
  1622. if (skb_is_gso(skb)) {
  1623. if (skb_header_cloned(skb)) {
  1624. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1625. if (unlikely(err))
  1626. return -1;
  1627. }
  1628. offload_type = skb_shinfo(skb)->gso_type;
  1629. if (offload_type & SKB_GSO_TCPV4) {
  1630. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1631. + ntohs(ip_hdr(skb)->tot_len));
  1632. if (real_len < skb->len)
  1633. pskb_trim(skb, real_len);
  1634. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1635. if (unlikely(skb->len == hdr_len)) {
  1636. /* only xsum need */
  1637. if (netif_msg_tx_queued(adapter))
  1638. dev_warn(&pdev->dev,
  1639. "IPV4 tso with zero data??\n");
  1640. goto check_sum;
  1641. } else {
  1642. ip_hdr(skb)->check = 0;
  1643. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1644. ip_hdr(skb)->saddr,
  1645. ip_hdr(skb)->daddr,
  1646. 0, IPPROTO_TCP, 0);
  1647. (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
  1648. }
  1649. }
  1650. if (offload_type & SKB_GSO_TCPV6) {
  1651. struct atl1c_tpd_ext_desc *etpd =
  1652. *(struct atl1c_tpd_ext_desc **)(tpd);
  1653. memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
  1654. *tpd = atl1c_get_tpd(adapter, type);
  1655. ipv6_hdr(skb)->payload_len = 0;
  1656. /* check payload == 0 byte ? */
  1657. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1658. if (unlikely(skb->len == hdr_len)) {
  1659. /* only xsum need */
  1660. if (netif_msg_tx_queued(adapter))
  1661. dev_warn(&pdev->dev,
  1662. "IPV6 tso with zero data??\n");
  1663. goto check_sum;
  1664. } else
  1665. tcp_hdr(skb)->check = ~csum_ipv6_magic(
  1666. &ipv6_hdr(skb)->saddr,
  1667. &ipv6_hdr(skb)->daddr,
  1668. 0, IPPROTO_TCP, 0);
  1669. etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1670. etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1671. etpd->pkt_len = cpu_to_le32(skb->len);
  1672. (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1673. }
  1674. (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1675. (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
  1676. TPD_TCPHDR_OFFSET_SHIFT;
  1677. (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
  1678. TPD_MSS_SHIFT;
  1679. return 0;
  1680. }
  1681. check_sum:
  1682. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1683. u8 css, cso;
  1684. cso = skb_transport_offset(skb);
  1685. if (unlikely(cso & 0x1)) {
  1686. if (netif_msg_tx_err(adapter))
  1687. dev_err(&adapter->pdev->dev,
  1688. "payload offset should not an event number\n");
  1689. return -1;
  1690. } else {
  1691. css = cso + skb->csum_offset;
  1692. (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
  1693. TPD_PLOADOFFSET_SHIFT;
  1694. (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
  1695. TPD_CCSUM_OFFSET_SHIFT;
  1696. (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
  1697. }
  1698. }
  1699. return 0;
  1700. }
  1701. static void atl1c_tx_map(struct atl1c_adapter *adapter,
  1702. struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
  1703. enum atl1c_trans_queue type)
  1704. {
  1705. struct atl1c_tpd_desc *use_tpd = NULL;
  1706. struct atl1c_buffer *buffer_info = NULL;
  1707. u16 buf_len = skb_headlen(skb);
  1708. u16 map_len = 0;
  1709. u16 mapped_len = 0;
  1710. u16 hdr_len = 0;
  1711. u16 nr_frags;
  1712. u16 f;
  1713. int tso;
  1714. nr_frags = skb_shinfo(skb)->nr_frags;
  1715. tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
  1716. if (tso) {
  1717. /* TSO */
  1718. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1719. use_tpd = tpd;
  1720. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1721. buffer_info->length = map_len;
  1722. buffer_info->dma = pci_map_single(adapter->pdev,
  1723. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1724. buffer_info->state = ATL1_BUFFER_BUSY;
  1725. mapped_len += map_len;
  1726. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1727. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1728. }
  1729. if (mapped_len < buf_len) {
  1730. /* mapped_len == 0, means we should use the first tpd,
  1731. which is given by caller */
  1732. if (mapped_len == 0)
  1733. use_tpd = tpd;
  1734. else {
  1735. use_tpd = atl1c_get_tpd(adapter, type);
  1736. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1737. use_tpd = atl1c_get_tpd(adapter, type);
  1738. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1739. }
  1740. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1741. buffer_info->length = buf_len - mapped_len;
  1742. buffer_info->dma =
  1743. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1744. buffer_info->length, PCI_DMA_TODEVICE);
  1745. buffer_info->state = ATL1_BUFFER_BUSY;
  1746. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1747. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1748. }
  1749. for (f = 0; f < nr_frags; f++) {
  1750. struct skb_frag_struct *frag;
  1751. frag = &skb_shinfo(skb)->frags[f];
  1752. use_tpd = atl1c_get_tpd(adapter, type);
  1753. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1754. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1755. buffer_info->length = frag->size;
  1756. buffer_info->dma =
  1757. pci_map_page(adapter->pdev, frag->page,
  1758. frag->page_offset,
  1759. buffer_info->length,
  1760. PCI_DMA_TODEVICE);
  1761. buffer_info->state = ATL1_BUFFER_BUSY;
  1762. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1763. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1764. }
  1765. /* The last tpd */
  1766. use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
  1767. /* The last buffer info contain the skb address,
  1768. so it will be free after unmap */
  1769. buffer_info->skb = skb;
  1770. }
  1771. static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
  1772. struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
  1773. {
  1774. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1775. u32 prod_data;
  1776. AT_READ_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, &prod_data);
  1777. switch (type) {
  1778. case atl1c_trans_high:
  1779. prod_data &= 0xFFFF0000;
  1780. prod_data |= tpd_ring->next_to_use & 0xFFFF;
  1781. break;
  1782. case atl1c_trans_normal:
  1783. prod_data &= 0x0000FFFF;
  1784. prod_data |= (tpd_ring->next_to_use & 0xFFFF) << 16;
  1785. break;
  1786. default:
  1787. break;
  1788. }
  1789. wmb();
  1790. AT_WRITE_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, prod_data);
  1791. }
  1792. static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
  1793. struct net_device *netdev)
  1794. {
  1795. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1796. unsigned long flags;
  1797. u16 tpd_req = 1;
  1798. struct atl1c_tpd_desc *tpd;
  1799. enum atl1c_trans_queue type = atl1c_trans_normal;
  1800. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1801. dev_kfree_skb_any(skb);
  1802. return NETDEV_TX_OK;
  1803. }
  1804. tpd_req = atl1c_cal_tpd_req(skb);
  1805. if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
  1806. if (netif_msg_pktdata(adapter))
  1807. dev_info(&adapter->pdev->dev, "tx locked\n");
  1808. return NETDEV_TX_LOCKED;
  1809. }
  1810. if (skb->mark == 0x01)
  1811. type = atl1c_trans_high;
  1812. else
  1813. type = atl1c_trans_normal;
  1814. if (atl1c_tpd_avail(adapter, type) < tpd_req) {
  1815. /* no enough descriptor, just stop queue */
  1816. netif_stop_queue(netdev);
  1817. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1818. return NETDEV_TX_BUSY;
  1819. }
  1820. tpd = atl1c_get_tpd(adapter, type);
  1821. /* do TSO and check sum */
  1822. if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
  1823. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1824. dev_kfree_skb_any(skb);
  1825. return NETDEV_TX_OK;
  1826. }
  1827. if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
  1828. u16 vlan = vlan_tx_tag_get(skb);
  1829. __le16 tag;
  1830. vlan = cpu_to_le16(vlan);
  1831. AT_VLAN_TO_TAG(vlan, tag);
  1832. tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
  1833. tpd->vlan_tag = tag;
  1834. }
  1835. if (skb_network_offset(skb) != ETH_HLEN)
  1836. tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
  1837. atl1c_tx_map(adapter, skb, tpd, type);
  1838. atl1c_tx_queue(adapter, skb, tpd, type);
  1839. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1840. return NETDEV_TX_OK;
  1841. }
  1842. static void atl1c_free_irq(struct atl1c_adapter *adapter)
  1843. {
  1844. struct net_device *netdev = adapter->netdev;
  1845. free_irq(adapter->pdev->irq, netdev);
  1846. if (adapter->have_msi)
  1847. pci_disable_msi(adapter->pdev);
  1848. }
  1849. static int atl1c_request_irq(struct atl1c_adapter *adapter)
  1850. {
  1851. struct pci_dev *pdev = adapter->pdev;
  1852. struct net_device *netdev = adapter->netdev;
  1853. int flags = 0;
  1854. int err = 0;
  1855. adapter->have_msi = true;
  1856. err = pci_enable_msi(adapter->pdev);
  1857. if (err) {
  1858. if (netif_msg_ifup(adapter))
  1859. dev_err(&pdev->dev,
  1860. "Unable to allocate MSI interrupt Error: %d\n",
  1861. err);
  1862. adapter->have_msi = false;
  1863. } else
  1864. netdev->irq = pdev->irq;
  1865. if (!adapter->have_msi)
  1866. flags |= IRQF_SHARED;
  1867. err = request_irq(adapter->pdev->irq, &atl1c_intr, flags,
  1868. netdev->name, netdev);
  1869. if (err) {
  1870. if (netif_msg_ifup(adapter))
  1871. dev_err(&pdev->dev,
  1872. "Unable to allocate interrupt Error: %d\n",
  1873. err);
  1874. if (adapter->have_msi)
  1875. pci_disable_msi(adapter->pdev);
  1876. return err;
  1877. }
  1878. if (netif_msg_ifup(adapter))
  1879. dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
  1880. return err;
  1881. }
  1882. int atl1c_up(struct atl1c_adapter *adapter)
  1883. {
  1884. struct net_device *netdev = adapter->netdev;
  1885. int num;
  1886. int err;
  1887. int i;
  1888. netif_carrier_off(netdev);
  1889. atl1c_init_ring_ptrs(adapter);
  1890. atl1c_set_multi(netdev);
  1891. atl1c_restore_vlan(adapter);
  1892. for (i = 0; i < adapter->num_rx_queues; i++) {
  1893. num = atl1c_alloc_rx_buffer(adapter, i);
  1894. if (unlikely(num == 0)) {
  1895. err = -ENOMEM;
  1896. goto err_alloc_rx;
  1897. }
  1898. }
  1899. if (atl1c_configure(adapter)) {
  1900. err = -EIO;
  1901. goto err_up;
  1902. }
  1903. err = atl1c_request_irq(adapter);
  1904. if (unlikely(err))
  1905. goto err_up;
  1906. clear_bit(__AT_DOWN, &adapter->flags);
  1907. napi_enable(&adapter->napi);
  1908. atl1c_irq_enable(adapter);
  1909. atl1c_check_link_status(adapter);
  1910. netif_start_queue(netdev);
  1911. return err;
  1912. err_up:
  1913. err_alloc_rx:
  1914. atl1c_clean_rx_ring(adapter);
  1915. return err;
  1916. }
  1917. void atl1c_down(struct atl1c_adapter *adapter)
  1918. {
  1919. struct net_device *netdev = adapter->netdev;
  1920. atl1c_del_timer(adapter);
  1921. atl1c_cancel_work(adapter);
  1922. /* signal that we're down so the interrupt handler does not
  1923. * reschedule our watchdog timer */
  1924. set_bit(__AT_DOWN, &adapter->flags);
  1925. netif_carrier_off(netdev);
  1926. napi_disable(&adapter->napi);
  1927. atl1c_irq_disable(adapter);
  1928. atl1c_free_irq(adapter);
  1929. AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
  1930. /* reset MAC to disable all RX/TX */
  1931. atl1c_reset_mac(&adapter->hw);
  1932. msleep(1);
  1933. adapter->link_speed = SPEED_0;
  1934. adapter->link_duplex = -1;
  1935. atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
  1936. atl1c_clean_tx_ring(adapter, atl1c_trans_high);
  1937. atl1c_clean_rx_ring(adapter);
  1938. }
  1939. /*
  1940. * atl1c_open - Called when a network interface is made active
  1941. * @netdev: network interface device structure
  1942. *
  1943. * Returns 0 on success, negative value on failure
  1944. *
  1945. * The open entry point is called when a network interface is made
  1946. * active by the system (IFF_UP). At this point all resources needed
  1947. * for transmit and receive operations are allocated, the interrupt
  1948. * handler is registered with the OS, the watchdog timer is started,
  1949. * and the stack is notified that the interface is ready.
  1950. */
  1951. static int atl1c_open(struct net_device *netdev)
  1952. {
  1953. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1954. int err;
  1955. /* disallow open during test */
  1956. if (test_bit(__AT_TESTING, &adapter->flags))
  1957. return -EBUSY;
  1958. /* allocate rx/tx dma buffer & descriptors */
  1959. err = atl1c_setup_ring_resources(adapter);
  1960. if (unlikely(err))
  1961. return err;
  1962. err = atl1c_up(adapter);
  1963. if (unlikely(err))
  1964. goto err_up;
  1965. if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
  1966. u32 phy_data;
  1967. AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data);
  1968. phy_data |= MDIO_AP_EN;
  1969. AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
  1970. }
  1971. return 0;
  1972. err_up:
  1973. atl1c_free_irq(adapter);
  1974. atl1c_free_ring_resources(adapter);
  1975. atl1c_reset_mac(&adapter->hw);
  1976. return err;
  1977. }
  1978. /*
  1979. * atl1c_close - Disables a network interface
  1980. * @netdev: network interface device structure
  1981. *
  1982. * Returns 0, this is not allowed to fail
  1983. *
  1984. * The close entry point is called when an interface is de-activated
  1985. * by the OS. The hardware is still under the drivers control, but
  1986. * needs to be disabled. A global MAC reset is issued to stop the
  1987. * hardware, and all transmit and receive resources are freed.
  1988. */
  1989. static int atl1c_close(struct net_device *netdev)
  1990. {
  1991. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1992. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  1993. atl1c_down(adapter);
  1994. atl1c_free_ring_resources(adapter);
  1995. return 0;
  1996. }
  1997. static int atl1c_suspend(struct pci_dev *pdev, pm_message_t state)
  1998. {
  1999. struct net_device *netdev = pci_get_drvdata(pdev);
  2000. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2001. struct atl1c_hw *hw = &adapter->hw;
  2002. u32 ctrl;
  2003. u32 mac_ctrl_data;
  2004. u32 master_ctrl_data;
  2005. u32 wol_ctrl_data = 0;
  2006. u16 mii_bmsr_data;
  2007. u16 save_autoneg_advertised;
  2008. u16 mii_intr_status_data;
  2009. u32 wufc = adapter->wol;
  2010. u32 i;
  2011. int retval = 0;
  2012. if (netif_running(netdev)) {
  2013. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2014. atl1c_down(adapter);
  2015. }
  2016. netif_device_detach(netdev);
  2017. atl1c_disable_l0s_l1(hw);
  2018. retval = pci_save_state(pdev);
  2019. if (retval)
  2020. return retval;
  2021. if (wufc) {
  2022. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  2023. master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  2024. /* get link status */
  2025. atl1c_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
  2026. atl1c_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
  2027. save_autoneg_advertised = hw->autoneg_advertised;
  2028. hw->autoneg_advertised = ADVERTISED_10baseT_Half;
  2029. if (atl1c_restart_autoneg(hw) != 0)
  2030. if (netif_msg_link(adapter))
  2031. dev_warn(&pdev->dev, "phy autoneg failed\n");
  2032. hw->phy_configured = false; /* re-init PHY when resume */
  2033. hw->autoneg_advertised = save_autoneg_advertised;
  2034. /* turn on magic packet wol */
  2035. if (wufc & AT_WUFC_MAG)
  2036. wol_ctrl_data = WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
  2037. if (wufc & AT_WUFC_LNKC) {
  2038. for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
  2039. msleep(100);
  2040. atl1c_read_phy_reg(hw, MII_BMSR,
  2041. (u16 *)&mii_bmsr_data);
  2042. if (mii_bmsr_data & BMSR_LSTATUS)
  2043. break;
  2044. }
  2045. if ((mii_bmsr_data & BMSR_LSTATUS) == 0)
  2046. if (netif_msg_link(adapter))
  2047. dev_warn(&pdev->dev,
  2048. "%s: Link may change"
  2049. "when suspend\n",
  2050. atl1c_driver_name);
  2051. wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
  2052. /* only link up can wake up */
  2053. if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
  2054. if (netif_msg_link(adapter))
  2055. dev_err(&pdev->dev,
  2056. "%s: read write phy "
  2057. "register failed.\n",
  2058. atl1c_driver_name);
  2059. goto wol_dis;
  2060. }
  2061. }
  2062. /* clear phy interrupt */
  2063. atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data);
  2064. /* Config MAC Ctrl register */
  2065. mac_ctrl_data = MAC_CTRL_RX_EN;
  2066. /* set to 10/100M halt duplex */
  2067. mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
  2068. mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
  2069. MAC_CTRL_PRMLEN_MASK) <<
  2070. MAC_CTRL_PRMLEN_SHIFT);
  2071. if (adapter->vlgrp)
  2072. mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  2073. /* magic packet maybe Broadcast&multicast&Unicast frame */
  2074. if (wufc & AT_WUFC_MAG)
  2075. mac_ctrl_data |= MAC_CTRL_BC_EN;
  2076. if (netif_msg_hw(adapter))
  2077. dev_dbg(&pdev->dev,
  2078. "%s: suspend MAC=0x%x\n",
  2079. atl1c_driver_name, mac_ctrl_data);
  2080. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  2081. AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
  2082. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  2083. /* pcie patch */
  2084. AT_READ_REG(hw, REG_PCIE_PHYMISC, &ctrl);
  2085. ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
  2086. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
  2087. pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
  2088. goto suspend_exit;
  2089. }
  2090. wol_dis:
  2091. /* WOL disabled */
  2092. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  2093. /* pcie patch */
  2094. AT_READ_REG(hw, REG_PCIE_PHYMISC, &ctrl);
  2095. ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
  2096. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
  2097. atl1c_phy_disable(hw);
  2098. hw->phy_configured = false; /* re-init PHY when resume */
  2099. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  2100. suspend_exit:
  2101. pci_disable_device(pdev);
  2102. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2103. return 0;
  2104. }
  2105. static int atl1c_resume(struct pci_dev *pdev)
  2106. {
  2107. struct net_device *netdev = pci_get_drvdata(pdev);
  2108. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2109. pci_set_power_state(pdev, PCI_D0);
  2110. pci_restore_state(pdev);
  2111. pci_enable_wake(pdev, PCI_D3hot, 0);
  2112. pci_enable_wake(pdev, PCI_D3cold, 0);
  2113. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  2114. atl1c_phy_reset(&adapter->hw);
  2115. atl1c_reset_mac(&adapter->hw);
  2116. netif_device_attach(netdev);
  2117. if (netif_running(netdev))
  2118. atl1c_up(adapter);
  2119. return 0;
  2120. }
  2121. static void atl1c_shutdown(struct pci_dev *pdev)
  2122. {
  2123. atl1c_suspend(pdev, PMSG_SUSPEND);
  2124. }
  2125. static const struct net_device_ops atl1c_netdev_ops = {
  2126. .ndo_open = atl1c_open,
  2127. .ndo_stop = atl1c_close,
  2128. .ndo_validate_addr = eth_validate_addr,
  2129. .ndo_start_xmit = atl1c_xmit_frame,
  2130. .ndo_set_mac_address = atl1c_set_mac_addr,
  2131. .ndo_set_multicast_list = atl1c_set_multi,
  2132. .ndo_change_mtu = atl1c_change_mtu,
  2133. .ndo_do_ioctl = atl1c_ioctl,
  2134. .ndo_tx_timeout = atl1c_tx_timeout,
  2135. .ndo_get_stats = atl1c_get_stats,
  2136. .ndo_vlan_rx_register = atl1c_vlan_rx_register,
  2137. #ifdef CONFIG_NET_POLL_CONTROLLER
  2138. .ndo_poll_controller = atl1c_netpoll,
  2139. #endif
  2140. };
  2141. static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  2142. {
  2143. SET_NETDEV_DEV(netdev, &pdev->dev);
  2144. pci_set_drvdata(pdev, netdev);
  2145. netdev->irq = pdev->irq;
  2146. netdev->netdev_ops = &atl1c_netdev_ops;
  2147. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  2148. atl1c_set_ethtool_ops(netdev);
  2149. /* TODO: add when ready */
  2150. netdev->features = NETIF_F_SG |
  2151. NETIF_F_HW_CSUM |
  2152. NETIF_F_HW_VLAN_TX |
  2153. NETIF_F_HW_VLAN_RX |
  2154. NETIF_F_TSO |
  2155. NETIF_F_TSO6;
  2156. return 0;
  2157. }
  2158. /*
  2159. * atl1c_probe - Device Initialization Routine
  2160. * @pdev: PCI device information struct
  2161. * @ent: entry in atl1c_pci_tbl
  2162. *
  2163. * Returns 0 on success, negative on failure
  2164. *
  2165. * atl1c_probe initializes an adapter identified by a pci_dev structure.
  2166. * The OS initialization, configuring of the adapter private structure,
  2167. * and a hardware reset occur.
  2168. */
  2169. static int __devinit atl1c_probe(struct pci_dev *pdev,
  2170. const struct pci_device_id *ent)
  2171. {
  2172. struct net_device *netdev;
  2173. struct atl1c_adapter *adapter;
  2174. static int cards_found;
  2175. int err = 0;
  2176. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  2177. err = pci_enable_device_mem(pdev);
  2178. if (err) {
  2179. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2180. return err;
  2181. }
  2182. /*
  2183. * The atl1c chip can DMA to 64-bit addresses, but it uses a single
  2184. * shared register for the high 32 bits, so only a single, aligned,
  2185. * 4 GB physical address range can be used at a time.
  2186. *
  2187. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2188. * worth. It is far easier to limit to 32-bit DMA than update
  2189. * various kernel subsystems to support the mechanics required by a
  2190. * fixed-high-32-bit system.
  2191. */
  2192. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  2193. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  2194. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  2195. goto err_dma;
  2196. }
  2197. err = pci_request_regions(pdev, atl1c_driver_name);
  2198. if (err) {
  2199. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2200. goto err_pci_reg;
  2201. }
  2202. pci_set_master(pdev);
  2203. netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
  2204. if (netdev == NULL) {
  2205. err = -ENOMEM;
  2206. dev_err(&pdev->dev, "etherdev alloc failed\n");
  2207. goto err_alloc_etherdev;
  2208. }
  2209. err = atl1c_init_netdev(netdev, pdev);
  2210. if (err) {
  2211. dev_err(&pdev->dev, "init netdevice failed\n");
  2212. goto err_init_netdev;
  2213. }
  2214. adapter = netdev_priv(netdev);
  2215. adapter->bd_number = cards_found;
  2216. adapter->netdev = netdev;
  2217. adapter->pdev = pdev;
  2218. adapter->hw.adapter = adapter;
  2219. adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
  2220. adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  2221. if (!adapter->hw.hw_addr) {
  2222. err = -EIO;
  2223. dev_err(&pdev->dev, "cannot map device registers\n");
  2224. goto err_ioremap;
  2225. }
  2226. netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
  2227. /* init mii data */
  2228. adapter->mii.dev = netdev;
  2229. adapter->mii.mdio_read = atl1c_mdio_read;
  2230. adapter->mii.mdio_write = atl1c_mdio_write;
  2231. adapter->mii.phy_id_mask = 0x1f;
  2232. adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
  2233. netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
  2234. setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
  2235. (unsigned long)adapter);
  2236. /* setup the private structure */
  2237. err = atl1c_sw_init(adapter);
  2238. if (err) {
  2239. dev_err(&pdev->dev, "net device private data init failed\n");
  2240. goto err_sw_init;
  2241. }
  2242. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
  2243. ATL1C_PCIE_PHY_RESET);
  2244. /* Init GPHY as early as possible due to power saving issue */
  2245. atl1c_phy_reset(&adapter->hw);
  2246. err = atl1c_reset_mac(&adapter->hw);
  2247. if (err) {
  2248. err = -EIO;
  2249. goto err_reset;
  2250. }
  2251. device_init_wakeup(&pdev->dev, 1);
  2252. /* reset the controller to
  2253. * put the device in a known good starting state */
  2254. err = atl1c_phy_init(&adapter->hw);
  2255. if (err) {
  2256. err = -EIO;
  2257. goto err_reset;
  2258. }
  2259. if (atl1c_read_mac_addr(&adapter->hw) != 0) {
  2260. err = -EIO;
  2261. dev_err(&pdev->dev, "get mac address failed\n");
  2262. goto err_eeprom;
  2263. }
  2264. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2265. memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
  2266. if (netif_msg_probe(adapter))
  2267. dev_dbg(&pdev->dev,
  2268. "mac address : %02x-%02x-%02x-%02x-%02x-%02x\n",
  2269. adapter->hw.mac_addr[0], adapter->hw.mac_addr[1],
  2270. adapter->hw.mac_addr[2], adapter->hw.mac_addr[3],
  2271. adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]);
  2272. atl1c_hw_set_mac_addr(&adapter->hw);
  2273. INIT_WORK(&adapter->reset_task, atl1c_reset_task);
  2274. INIT_WORK(&adapter->link_chg_task, atl1c_link_chg_task);
  2275. err = register_netdev(netdev);
  2276. if (err) {
  2277. dev_err(&pdev->dev, "register netdevice failed\n");
  2278. goto err_register;
  2279. }
  2280. if (netif_msg_probe(adapter))
  2281. dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
  2282. cards_found++;
  2283. return 0;
  2284. err_reset:
  2285. err_register:
  2286. err_sw_init:
  2287. err_eeprom:
  2288. iounmap(adapter->hw.hw_addr);
  2289. err_init_netdev:
  2290. err_ioremap:
  2291. free_netdev(netdev);
  2292. err_alloc_etherdev:
  2293. pci_release_regions(pdev);
  2294. err_pci_reg:
  2295. err_dma:
  2296. pci_disable_device(pdev);
  2297. return err;
  2298. }
  2299. /*
  2300. * atl1c_remove - Device Removal Routine
  2301. * @pdev: PCI device information struct
  2302. *
  2303. * atl1c_remove is called by the PCI subsystem to alert the driver
  2304. * that it should release a PCI device. The could be caused by a
  2305. * Hot-Plug event, or because the driver is going to be removed from
  2306. * memory.
  2307. */
  2308. static void __devexit atl1c_remove(struct pci_dev *pdev)
  2309. {
  2310. struct net_device *netdev = pci_get_drvdata(pdev);
  2311. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2312. unregister_netdev(netdev);
  2313. atl1c_phy_disable(&adapter->hw);
  2314. iounmap(adapter->hw.hw_addr);
  2315. pci_release_regions(pdev);
  2316. pci_disable_device(pdev);
  2317. free_netdev(netdev);
  2318. }
  2319. /*
  2320. * atl1c_io_error_detected - called when PCI error is detected
  2321. * @pdev: Pointer to PCI device
  2322. * @state: The current pci connection state
  2323. *
  2324. * This function is called after a PCI bus error affecting
  2325. * this device has been detected.
  2326. */
  2327. static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
  2328. pci_channel_state_t state)
  2329. {
  2330. struct net_device *netdev = pci_get_drvdata(pdev);
  2331. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2332. netif_device_detach(netdev);
  2333. if (state == pci_channel_io_perm_failure)
  2334. return PCI_ERS_RESULT_DISCONNECT;
  2335. if (netif_running(netdev))
  2336. atl1c_down(adapter);
  2337. pci_disable_device(pdev);
  2338. /* Request a slot slot reset. */
  2339. return PCI_ERS_RESULT_NEED_RESET;
  2340. }
  2341. /*
  2342. * atl1c_io_slot_reset - called after the pci bus has been reset.
  2343. * @pdev: Pointer to PCI device
  2344. *
  2345. * Restart the card from scratch, as if from a cold-boot. Implementation
  2346. * resembles the first-half of the e1000_resume routine.
  2347. */
  2348. static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
  2349. {
  2350. struct net_device *netdev = pci_get_drvdata(pdev);
  2351. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2352. if (pci_enable_device(pdev)) {
  2353. if (netif_msg_hw(adapter))
  2354. dev_err(&pdev->dev,
  2355. "Cannot re-enable PCI device after reset\n");
  2356. return PCI_ERS_RESULT_DISCONNECT;
  2357. }
  2358. pci_set_master(pdev);
  2359. pci_enable_wake(pdev, PCI_D3hot, 0);
  2360. pci_enable_wake(pdev, PCI_D3cold, 0);
  2361. atl1c_reset_mac(&adapter->hw);
  2362. return PCI_ERS_RESULT_RECOVERED;
  2363. }
  2364. /*
  2365. * atl1c_io_resume - called when traffic can start flowing again.
  2366. * @pdev: Pointer to PCI device
  2367. *
  2368. * This callback is called when the error recovery driver tells us that
  2369. * its OK to resume normal operation. Implementation resembles the
  2370. * second-half of the atl1c_resume routine.
  2371. */
  2372. static void atl1c_io_resume(struct pci_dev *pdev)
  2373. {
  2374. struct net_device *netdev = pci_get_drvdata(pdev);
  2375. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2376. if (netif_running(netdev)) {
  2377. if (atl1c_up(adapter)) {
  2378. if (netif_msg_hw(adapter))
  2379. dev_err(&pdev->dev,
  2380. "Cannot bring device back up after reset\n");
  2381. return;
  2382. }
  2383. }
  2384. netif_device_attach(netdev);
  2385. }
  2386. static struct pci_error_handlers atl1c_err_handler = {
  2387. .error_detected = atl1c_io_error_detected,
  2388. .slot_reset = atl1c_io_slot_reset,
  2389. .resume = atl1c_io_resume,
  2390. };
  2391. static struct pci_driver atl1c_driver = {
  2392. .name = atl1c_driver_name,
  2393. .id_table = atl1c_pci_tbl,
  2394. .probe = atl1c_probe,
  2395. .remove = __devexit_p(atl1c_remove),
  2396. /* Power Managment Hooks */
  2397. .suspend = atl1c_suspend,
  2398. .resume = atl1c_resume,
  2399. .shutdown = atl1c_shutdown,
  2400. .err_handler = &atl1c_err_handler
  2401. };
  2402. /*
  2403. * atl1c_init_module - Driver Registration Routine
  2404. *
  2405. * atl1c_init_module is the first routine called when the driver is
  2406. * loaded. All it does is register with the PCI subsystem.
  2407. */
  2408. static int __init atl1c_init_module(void)
  2409. {
  2410. return pci_register_driver(&atl1c_driver);
  2411. }
  2412. /*
  2413. * atl1c_exit_module - Driver Exit Cleanup Routine
  2414. *
  2415. * atl1c_exit_module is called just before the driver is removed
  2416. * from memory.
  2417. */
  2418. static void __exit atl1c_exit_module(void)
  2419. {
  2420. pci_unregister_driver(&atl1c_driver);
  2421. }
  2422. module_init(atl1c_init_module);
  2423. module_exit(atl1c_exit_module);