phy_common.c 9.2 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. Common PHY routines
  4. Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
  5. Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  6. Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
  7. Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  8. Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  9. This program is free software; you can redistribute it and/or modify
  10. it under the terms of the GNU General Public License as published by
  11. the Free Software Foundation; either version 2 of the License, or
  12. (at your option) any later version.
  13. This program is distributed in the hope that it will be useful,
  14. but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. GNU General Public License for more details.
  17. You should have received a copy of the GNU General Public License
  18. along with this program; see the file COPYING. If not, write to
  19. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  20. Boston, MA 02110-1301, USA.
  21. */
  22. #include "phy_common.h"
  23. #include "phy_g.h"
  24. #include "phy_a.h"
  25. #include "nphy.h"
  26. #include "b43.h"
  27. #include "main.h"
  28. int b43_phy_operations_setup(struct b43_wldev *dev)
  29. {
  30. struct b43_phy *phy = &(dev->phy);
  31. int err;
  32. phy->ops = NULL;
  33. switch (phy->type) {
  34. case B43_PHYTYPE_A:
  35. phy->ops = &b43_phyops_a;
  36. break;
  37. case B43_PHYTYPE_G:
  38. phy->ops = &b43_phyops_g;
  39. break;
  40. case B43_PHYTYPE_N:
  41. #ifdef CONFIG_B43_NPHY
  42. phy->ops = &b43_phyops_n;
  43. #endif
  44. break;
  45. case B43_PHYTYPE_LP:
  46. /* FIXME: Not yet */
  47. break;
  48. }
  49. if (B43_WARN_ON(!phy->ops))
  50. return -ENODEV;
  51. err = phy->ops->allocate(dev);
  52. if (err)
  53. phy->ops = NULL;
  54. return err;
  55. }
  56. int b43_phy_init(struct b43_wldev *dev)
  57. {
  58. struct b43_phy *phy = &dev->phy;
  59. const struct b43_phy_operations *ops = phy->ops;
  60. int err;
  61. phy->channel = ops->get_default_chan(dev);
  62. ops->software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
  63. err = ops->init(dev);
  64. if (err) {
  65. b43err(dev->wl, "PHY init failed\n");
  66. goto err_block_rf;
  67. }
  68. /* Make sure to switch hardware and firmware (SHM) to
  69. * the default channel. */
  70. err = b43_switch_channel(dev, ops->get_default_chan(dev));
  71. if (err) {
  72. b43err(dev->wl, "PHY init: Channel switch to default failed\n");
  73. goto err_phy_exit;
  74. }
  75. return 0;
  76. err_phy_exit:
  77. if (ops->exit)
  78. ops->exit(dev);
  79. err_block_rf:
  80. ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
  81. return err;
  82. }
  83. void b43_phy_exit(struct b43_wldev *dev)
  84. {
  85. const struct b43_phy_operations *ops = dev->phy.ops;
  86. ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
  87. if (ops->exit)
  88. ops->exit(dev);
  89. }
  90. bool b43_has_hardware_pctl(struct b43_wldev *dev)
  91. {
  92. if (!dev->phy.hardware_power_control)
  93. return 0;
  94. if (!dev->phy.ops->supports_hwpctl)
  95. return 0;
  96. return dev->phy.ops->supports_hwpctl(dev);
  97. }
  98. void b43_radio_lock(struct b43_wldev *dev)
  99. {
  100. u32 macctl;
  101. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  102. B43_WARN_ON(macctl & B43_MACCTL_RADIOLOCK);
  103. macctl |= B43_MACCTL_RADIOLOCK;
  104. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  105. /* Commit the write and wait for the device
  106. * to exit any radio register access. */
  107. b43_read32(dev, B43_MMIO_MACCTL);
  108. udelay(10);
  109. }
  110. void b43_radio_unlock(struct b43_wldev *dev)
  111. {
  112. u32 macctl;
  113. /* Commit any write */
  114. b43_read16(dev, B43_MMIO_PHY_VER);
  115. /* unlock */
  116. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  117. B43_WARN_ON(!(macctl & B43_MACCTL_RADIOLOCK));
  118. macctl &= ~B43_MACCTL_RADIOLOCK;
  119. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  120. }
  121. void b43_phy_lock(struct b43_wldev *dev)
  122. {
  123. #if B43_DEBUG
  124. B43_WARN_ON(dev->phy.phy_locked);
  125. dev->phy.phy_locked = 1;
  126. #endif
  127. B43_WARN_ON(dev->dev->id.revision < 3);
  128. if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
  129. b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
  130. }
  131. void b43_phy_unlock(struct b43_wldev *dev)
  132. {
  133. #if B43_DEBUG
  134. B43_WARN_ON(!dev->phy.phy_locked);
  135. dev->phy.phy_locked = 0;
  136. #endif
  137. B43_WARN_ON(dev->dev->id.revision < 3);
  138. if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
  139. b43_power_saving_ctl_bits(dev, 0);
  140. }
  141. u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
  142. {
  143. return dev->phy.ops->radio_read(dev, reg);
  144. }
  145. void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
  146. {
  147. dev->phy.ops->radio_write(dev, reg, value);
  148. }
  149. void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
  150. {
  151. b43_radio_write16(dev, offset,
  152. b43_radio_read16(dev, offset) & mask);
  153. }
  154. void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
  155. {
  156. b43_radio_write16(dev, offset,
  157. b43_radio_read16(dev, offset) | set);
  158. }
  159. void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
  160. {
  161. b43_radio_write16(dev, offset,
  162. (b43_radio_read16(dev, offset) & mask) | set);
  163. }
  164. u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
  165. {
  166. return dev->phy.ops->phy_read(dev, reg);
  167. }
  168. void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
  169. {
  170. dev->phy.ops->phy_write(dev, reg, value);
  171. }
  172. void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
  173. {
  174. b43_phy_write(dev, offset,
  175. b43_phy_read(dev, offset) & mask);
  176. }
  177. void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
  178. {
  179. b43_phy_write(dev, offset,
  180. b43_phy_read(dev, offset) | set);
  181. }
  182. void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
  183. {
  184. b43_phy_write(dev, offset,
  185. (b43_phy_read(dev, offset) & mask) | set);
  186. }
  187. int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
  188. {
  189. struct b43_phy *phy = &(dev->phy);
  190. u16 channelcookie, savedcookie;
  191. int err;
  192. if (new_channel == B43_DEFAULT_CHANNEL)
  193. new_channel = phy->ops->get_default_chan(dev);
  194. /* First we set the channel radio code to prevent the
  195. * firmware from sending ghost packets.
  196. */
  197. channelcookie = new_channel;
  198. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  199. channelcookie |= 0x100;
  200. //FIXME set 40Mhz flag if required
  201. savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
  202. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
  203. /* Now try to switch the PHY hardware channel. */
  204. err = phy->ops->switch_channel(dev, new_channel);
  205. if (err)
  206. goto err_restore_cookie;
  207. dev->phy.channel = new_channel;
  208. /* Wait for the radio to tune to the channel and stabilize. */
  209. msleep(8);
  210. return 0;
  211. err_restore_cookie:
  212. b43_shm_write16(dev, B43_SHM_SHARED,
  213. B43_SHM_SH_CHAN, savedcookie);
  214. return err;
  215. }
  216. void b43_software_rfkill(struct b43_wldev *dev, enum rfkill_state state)
  217. {
  218. struct b43_phy *phy = &dev->phy;
  219. if (state == RFKILL_STATE_HARD_BLOCKED) {
  220. /* We cannot hardware-block the device */
  221. state = RFKILL_STATE_SOFT_BLOCKED;
  222. }
  223. phy->ops->software_rfkill(dev, state);
  224. phy->radio_on = (state == RFKILL_STATE_UNBLOCKED);
  225. }
  226. /**
  227. * b43_phy_txpower_adjust_work - TX power workqueue.
  228. *
  229. * Workqueue for updating the TX power parameters in hardware.
  230. */
  231. void b43_phy_txpower_adjust_work(struct work_struct *work)
  232. {
  233. struct b43_wl *wl = container_of(work, struct b43_wl,
  234. txpower_adjust_work);
  235. struct b43_wldev *dev;
  236. mutex_lock(&wl->mutex);
  237. dev = wl->current_dev;
  238. if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
  239. dev->phy.ops->adjust_txpower(dev);
  240. mutex_unlock(&wl->mutex);
  241. }
  242. /* Called with wl->irq_lock locked */
  243. void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
  244. {
  245. struct b43_phy *phy = &dev->phy;
  246. unsigned long now = jiffies;
  247. enum b43_txpwr_result result;
  248. if (!(flags & B43_TXPWR_IGNORE_TIME)) {
  249. /* Check if it's time for a TXpower check. */
  250. if (time_before(now, phy->next_txpwr_check_time))
  251. return; /* Not yet */
  252. }
  253. /* The next check will be needed in two seconds, or later. */
  254. phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
  255. if ((dev->dev->bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
  256. (dev->dev->bus->boardinfo.type == SSB_BOARD_BU4306))
  257. return; /* No software txpower adjustment needed */
  258. result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
  259. if (result == B43_TXPWR_RES_DONE)
  260. return; /* We are done. */
  261. B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
  262. B43_WARN_ON(phy->ops->adjust_txpower == NULL);
  263. /* We must adjust the transmission power in hardware.
  264. * Schedule b43_phy_txpower_adjust_work(). */
  265. queue_work(dev->wl->hw->workqueue, &dev->wl->txpower_adjust_work);
  266. }
  267. int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
  268. {
  269. const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
  270. unsigned int a, b, c, d;
  271. unsigned int average;
  272. u32 tmp;
  273. tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
  274. a = tmp & 0xFF;
  275. b = (tmp >> 8) & 0xFF;
  276. c = (tmp >> 16) & 0xFF;
  277. d = (tmp >> 24) & 0xFF;
  278. if (a == 0 || a == B43_TSSI_MAX ||
  279. b == 0 || b == B43_TSSI_MAX ||
  280. c == 0 || c == B43_TSSI_MAX ||
  281. d == 0 || d == B43_TSSI_MAX)
  282. return -ENOENT;
  283. /* The values are OK. Clear them. */
  284. tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
  285. (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
  286. b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
  287. if (is_ofdm) {
  288. a = (a + 32) & 0x3F;
  289. b = (b + 32) & 0x3F;
  290. c = (c + 32) & 0x3F;
  291. d = (d + 32) & 0x3F;
  292. }
  293. /* Get the average of the values with 0.5 added to each value. */
  294. average = (a + b + c + d + 2) / 4;
  295. if (is_ofdm) {
  296. /* Adjust for CCK-boost */
  297. if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
  298. & B43_HF_CCKBOOST)
  299. average = (average >= 13) ? (average - 13) : 0;
  300. }
  301. return average;
  302. }