au1000_eth.c 33 KB

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  1. /*
  2. *
  3. * Alchemy Au1x00 ethernet driver
  4. *
  5. * Copyright 2001-2003, 2006 MontaVista Software Inc.
  6. * Copyright 2002 TimeSys Corp.
  7. * Added ethtool/mii-tool support,
  8. * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
  9. * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
  10. * or riemer@riemer-nt.de: fixed the link beat detection with
  11. * ioctls (SIOCGMIIPHY)
  12. * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
  13. * converted to use linux-2.6.x's PHY framework
  14. *
  15. * Author: MontaVista Software, Inc.
  16. * ppopov@mvista.com or source@mvista.com
  17. *
  18. * ########################################################################
  19. *
  20. * This program is free software; you can distribute it and/or modify it
  21. * under the terms of the GNU General Public License (Version 2) as
  22. * published by the Free Software Foundation.
  23. *
  24. * This program is distributed in the hope it will be useful, but WITHOUT
  25. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  27. * for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License along
  30. * with this program; if not, write to the Free Software Foundation, Inc.,
  31. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  32. *
  33. * ########################################################################
  34. *
  35. *
  36. */
  37. #include <linux/capability.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/module.h>
  40. #include <linux/kernel.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/errno.h>
  44. #include <linux/in.h>
  45. #include <linux/ioport.h>
  46. #include <linux/bitops.h>
  47. #include <linux/slab.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/init.h>
  50. #include <linux/netdevice.h>
  51. #include <linux/etherdevice.h>
  52. #include <linux/ethtool.h>
  53. #include <linux/mii.h>
  54. #include <linux/skbuff.h>
  55. #include <linux/delay.h>
  56. #include <linux/crc32.h>
  57. #include <linux/phy.h>
  58. #include <linux/platform_device.h>
  59. #include <asm/cpu.h>
  60. #include <asm/mipsregs.h>
  61. #include <asm/irq.h>
  62. #include <asm/io.h>
  63. #include <asm/processor.h>
  64. #include <au1000.h>
  65. #include <au1xxx_eth.h>
  66. #include <prom.h>
  67. #include "au1000_eth.h"
  68. #ifdef AU1000_ETH_DEBUG
  69. static int au1000_debug = 5;
  70. #else
  71. static int au1000_debug = 3;
  72. #endif
  73. #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
  74. NETIF_MSG_PROBE | \
  75. NETIF_MSG_LINK)
  76. #define DRV_NAME "au1000_eth"
  77. #define DRV_VERSION "1.7"
  78. #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
  79. #define DRV_DESC "Au1xxx on-chip Ethernet driver"
  80. MODULE_AUTHOR(DRV_AUTHOR);
  81. MODULE_DESCRIPTION(DRV_DESC);
  82. MODULE_LICENSE("GPL");
  83. MODULE_VERSION(DRV_VERSION);
  84. /*
  85. * Theory of operation
  86. *
  87. * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
  88. * There are four receive and four transmit descriptors. These
  89. * descriptors are not in memory; rather, they are just a set of
  90. * hardware registers.
  91. *
  92. * Since the Au1000 has a coherent data cache, the receive and
  93. * transmit buffers are allocated from the KSEG0 segment. The
  94. * hardware registers, however, are still mapped at KSEG1 to
  95. * make sure there's no out-of-order writes, and that all writes
  96. * complete immediately.
  97. */
  98. struct au1000_private *au_macs[NUM_ETH_INTERFACES];
  99. /*
  100. * board-specific configurations
  101. *
  102. * PHY detection algorithm
  103. *
  104. * If phy_static_config is undefined, the PHY setup is
  105. * autodetected:
  106. *
  107. * mii_probe() first searches the current MAC's MII bus for a PHY,
  108. * selecting the first (or last, if phy_search_highest_addr is
  109. * defined) PHY address not already claimed by another netdev.
  110. *
  111. * If nothing was found that way when searching for the 2nd ethernet
  112. * controller's PHY and phy1_search_mac0 is defined, then
  113. * the first MII bus is searched as well for an unclaimed PHY; this is
  114. * needed in case of a dual-PHY accessible only through the MAC0's MII
  115. * bus.
  116. *
  117. * Finally, if no PHY is found, then the corresponding ethernet
  118. * controller is not registered to the network subsystem.
  119. */
  120. /* autodetection defaults: phy1_search_mac0 */
  121. /* static PHY setup
  122. *
  123. * most boards PHY setup should be detectable properly with the
  124. * autodetection algorithm in mii_probe(), but in some cases (e.g. if
  125. * you have a switch attached, or want to use the PHY's interrupt
  126. * notification capabilities) you can provide a static PHY
  127. * configuration here
  128. *
  129. * IRQs may only be set, if a PHY address was configured
  130. * If a PHY address is given, also a bus id is required to be set
  131. *
  132. * ps: make sure the used irqs are configured properly in the board
  133. * specific irq-map
  134. */
  135. static void au1000_enable_mac(struct net_device *dev, int force_reset)
  136. {
  137. unsigned long flags;
  138. struct au1000_private *aup = netdev_priv(dev);
  139. spin_lock_irqsave(&aup->lock, flags);
  140. if (force_reset || (!aup->mac_enabled)) {
  141. *aup->enable = MAC_EN_CLOCK_ENABLE;
  142. au_sync_delay(2);
  143. *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
  144. | MAC_EN_CLOCK_ENABLE);
  145. au_sync_delay(2);
  146. aup->mac_enabled = 1;
  147. }
  148. spin_unlock_irqrestore(&aup->lock, flags);
  149. }
  150. /*
  151. * MII operations
  152. */
  153. static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
  154. {
  155. struct au1000_private *aup = netdev_priv(dev);
  156. volatile u32 *const mii_control_reg = &aup->mac->mii_control;
  157. volatile u32 *const mii_data_reg = &aup->mac->mii_data;
  158. u32 timedout = 20;
  159. u32 mii_control;
  160. while (*mii_control_reg & MAC_MII_BUSY) {
  161. mdelay(1);
  162. if (--timedout == 0) {
  163. netdev_err(dev, "read_MII busy timeout!!\n");
  164. return -1;
  165. }
  166. }
  167. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  168. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
  169. *mii_control_reg = mii_control;
  170. timedout = 20;
  171. while (*mii_control_reg & MAC_MII_BUSY) {
  172. mdelay(1);
  173. if (--timedout == 0) {
  174. netdev_err(dev, "mdio_read busy timeout!!\n");
  175. return -1;
  176. }
  177. }
  178. return (int)*mii_data_reg;
  179. }
  180. static void au1000_mdio_write(struct net_device *dev, int phy_addr,
  181. int reg, u16 value)
  182. {
  183. struct au1000_private *aup = netdev_priv(dev);
  184. volatile u32 *const mii_control_reg = &aup->mac->mii_control;
  185. volatile u32 *const mii_data_reg = &aup->mac->mii_data;
  186. u32 timedout = 20;
  187. u32 mii_control;
  188. while (*mii_control_reg & MAC_MII_BUSY) {
  189. mdelay(1);
  190. if (--timedout == 0) {
  191. netdev_err(dev, "mdio_write busy timeout!!\n");
  192. return;
  193. }
  194. }
  195. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  196. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
  197. *mii_data_reg = value;
  198. *mii_control_reg = mii_control;
  199. }
  200. static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
  201. {
  202. /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
  203. * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
  204. struct net_device *const dev = bus->priv;
  205. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  206. * mii_bus is enabled */
  207. return au1000_mdio_read(dev, phy_addr, regnum);
  208. }
  209. static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
  210. u16 value)
  211. {
  212. struct net_device *const dev = bus->priv;
  213. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  214. * mii_bus is enabled */
  215. au1000_mdio_write(dev, phy_addr, regnum, value);
  216. return 0;
  217. }
  218. static int au1000_mdiobus_reset(struct mii_bus *bus)
  219. {
  220. struct net_device *const dev = bus->priv;
  221. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  222. * mii_bus is enabled */
  223. return 0;
  224. }
  225. static void au1000_hard_stop(struct net_device *dev)
  226. {
  227. struct au1000_private *aup = netdev_priv(dev);
  228. netif_dbg(aup, drv, dev, "hard stop\n");
  229. aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
  230. au_sync_delay(10);
  231. }
  232. static void au1000_enable_rx_tx(struct net_device *dev)
  233. {
  234. struct au1000_private *aup = netdev_priv(dev);
  235. netif_dbg(aup, hw, dev, "enable_rx_tx\n");
  236. aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
  237. au_sync_delay(10);
  238. }
  239. static void
  240. au1000_adjust_link(struct net_device *dev)
  241. {
  242. struct au1000_private *aup = netdev_priv(dev);
  243. struct phy_device *phydev = aup->phy_dev;
  244. unsigned long flags;
  245. int status_change = 0;
  246. BUG_ON(!aup->phy_dev);
  247. spin_lock_irqsave(&aup->lock, flags);
  248. if (phydev->link && (aup->old_speed != phydev->speed)) {
  249. /* speed changed */
  250. switch (phydev->speed) {
  251. case SPEED_10:
  252. case SPEED_100:
  253. break;
  254. default:
  255. netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
  256. phydev->speed);
  257. break;
  258. }
  259. aup->old_speed = phydev->speed;
  260. status_change = 1;
  261. }
  262. if (phydev->link && (aup->old_duplex != phydev->duplex)) {
  263. /* duplex mode changed */
  264. /* switching duplex mode requires to disable rx and tx! */
  265. au1000_hard_stop(dev);
  266. if (DUPLEX_FULL == phydev->duplex)
  267. aup->mac->control = ((aup->mac->control
  268. | MAC_FULL_DUPLEX)
  269. & ~MAC_DISABLE_RX_OWN);
  270. else
  271. aup->mac->control = ((aup->mac->control
  272. & ~MAC_FULL_DUPLEX)
  273. | MAC_DISABLE_RX_OWN);
  274. au_sync_delay(1);
  275. au1000_enable_rx_tx(dev);
  276. aup->old_duplex = phydev->duplex;
  277. status_change = 1;
  278. }
  279. if (phydev->link != aup->old_link) {
  280. /* link state changed */
  281. if (!phydev->link) {
  282. /* link went down */
  283. aup->old_speed = 0;
  284. aup->old_duplex = -1;
  285. }
  286. aup->old_link = phydev->link;
  287. status_change = 1;
  288. }
  289. spin_unlock_irqrestore(&aup->lock, flags);
  290. if (status_change) {
  291. if (phydev->link)
  292. netdev_info(dev, "link up (%d/%s)\n",
  293. phydev->speed,
  294. DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
  295. else
  296. netdev_info(dev, "link down\n");
  297. }
  298. }
  299. static int au1000_mii_probe(struct net_device *dev)
  300. {
  301. struct au1000_private *const aup = netdev_priv(dev);
  302. struct phy_device *phydev = NULL;
  303. int phy_addr;
  304. if (aup->phy_static_config) {
  305. BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
  306. if (aup->phy_addr)
  307. phydev = aup->mii_bus->phy_map[aup->phy_addr];
  308. else
  309. netdev_info(dev, "using PHY-less setup\n");
  310. return 0;
  311. }
  312. /* find the first (lowest address) PHY
  313. * on the current MAC's MII bus */
  314. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
  315. if (aup->mii_bus->phy_map[phy_addr]) {
  316. phydev = aup->mii_bus->phy_map[phy_addr];
  317. if (!aup->phy_search_highest_addr)
  318. /* break out with first one found */
  319. break;
  320. }
  321. if (aup->phy1_search_mac0) {
  322. /* try harder to find a PHY */
  323. if (!phydev && (aup->mac_id == 1)) {
  324. /* no PHY found, maybe we have a dual PHY? */
  325. dev_info(&dev->dev, ": no PHY found on MAC1, "
  326. "let's see if it's attached to MAC0...\n");
  327. /* find the first (lowest address) non-attached
  328. * PHY on the MAC0 MII bus
  329. */
  330. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  331. struct phy_device *const tmp_phydev =
  332. aup->mii_bus->phy_map[phy_addr];
  333. if (aup->mac_id == 1)
  334. break;
  335. /* no PHY here... */
  336. if (!tmp_phydev)
  337. continue;
  338. /* already claimed by MAC0 */
  339. if (tmp_phydev->attached_dev)
  340. continue;
  341. phydev = tmp_phydev;
  342. break; /* found it */
  343. }
  344. }
  345. }
  346. if (!phydev) {
  347. netdev_err(dev, "no PHY found\n");
  348. return -1;
  349. }
  350. /* now we are supposed to have a proper phydev, to attach to... */
  351. BUG_ON(phydev->attached_dev);
  352. phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
  353. 0, PHY_INTERFACE_MODE_MII);
  354. if (IS_ERR(phydev)) {
  355. netdev_err(dev, "Could not attach to PHY\n");
  356. return PTR_ERR(phydev);
  357. }
  358. /* mask with MAC supported features */
  359. phydev->supported &= (SUPPORTED_10baseT_Half
  360. | SUPPORTED_10baseT_Full
  361. | SUPPORTED_100baseT_Half
  362. | SUPPORTED_100baseT_Full
  363. | SUPPORTED_Autoneg
  364. /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
  365. | SUPPORTED_MII
  366. | SUPPORTED_TP);
  367. phydev->advertising = phydev->supported;
  368. aup->old_link = 0;
  369. aup->old_speed = 0;
  370. aup->old_duplex = -1;
  371. aup->phy_dev = phydev;
  372. netdev_info(dev, "attached PHY driver [%s] "
  373. "(mii_bus:phy_addr=%s, irq=%d)\n",
  374. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  375. return 0;
  376. }
  377. /*
  378. * Buffer allocation/deallocation routines. The buffer descriptor returned
  379. * has the virtual and dma address of a buffer suitable for
  380. * both, receive and transmit operations.
  381. */
  382. static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
  383. {
  384. struct db_dest *pDB;
  385. pDB = aup->pDBfree;
  386. if (pDB)
  387. aup->pDBfree = pDB->pnext;
  388. return pDB;
  389. }
  390. void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
  391. {
  392. struct db_dest *pDBfree = aup->pDBfree;
  393. if (pDBfree)
  394. pDBfree->pnext = pDB;
  395. aup->pDBfree = pDB;
  396. }
  397. static void au1000_reset_mac_unlocked(struct net_device *dev)
  398. {
  399. struct au1000_private *const aup = netdev_priv(dev);
  400. int i;
  401. au1000_hard_stop(dev);
  402. *aup->enable = MAC_EN_CLOCK_ENABLE;
  403. au_sync_delay(2);
  404. *aup->enable = 0;
  405. au_sync_delay(2);
  406. aup->tx_full = 0;
  407. for (i = 0; i < NUM_RX_DMA; i++) {
  408. /* reset control bits */
  409. aup->rx_dma_ring[i]->buff_stat &= ~0xf;
  410. }
  411. for (i = 0; i < NUM_TX_DMA; i++) {
  412. /* reset control bits */
  413. aup->tx_dma_ring[i]->buff_stat &= ~0xf;
  414. }
  415. aup->mac_enabled = 0;
  416. }
  417. static void au1000_reset_mac(struct net_device *dev)
  418. {
  419. struct au1000_private *const aup = netdev_priv(dev);
  420. unsigned long flags;
  421. netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
  422. (unsigned)aup);
  423. spin_lock_irqsave(&aup->lock, flags);
  424. au1000_reset_mac_unlocked(dev);
  425. spin_unlock_irqrestore(&aup->lock, flags);
  426. }
  427. /*
  428. * Setup the receive and transmit "rings". These pointers are the addresses
  429. * of the rx and tx MAC DMA registers so they are fixed by the hardware --
  430. * these are not descriptors sitting in memory.
  431. */
  432. static void
  433. au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
  434. {
  435. int i;
  436. for (i = 0; i < NUM_RX_DMA; i++) {
  437. aup->rx_dma_ring[i] =
  438. (volatile struct rx_dma *)
  439. (rx_base + sizeof(struct rx_dma)*i);
  440. }
  441. for (i = 0; i < NUM_TX_DMA; i++) {
  442. aup->tx_dma_ring[i] =
  443. (volatile struct tx_dma *)
  444. (tx_base + sizeof(struct tx_dma)*i);
  445. }
  446. }
  447. /*
  448. * ethtool operations
  449. */
  450. static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  451. {
  452. struct au1000_private *aup = netdev_priv(dev);
  453. if (aup->phy_dev)
  454. return phy_ethtool_gset(aup->phy_dev, cmd);
  455. return -EINVAL;
  456. }
  457. static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  458. {
  459. struct au1000_private *aup = netdev_priv(dev);
  460. if (!capable(CAP_NET_ADMIN))
  461. return -EPERM;
  462. if (aup->phy_dev)
  463. return phy_ethtool_sset(aup->phy_dev, cmd);
  464. return -EINVAL;
  465. }
  466. static void
  467. au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  468. {
  469. struct au1000_private *aup = netdev_priv(dev);
  470. strcpy(info->driver, DRV_NAME);
  471. strcpy(info->version, DRV_VERSION);
  472. info->fw_version[0] = '\0';
  473. sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
  474. info->regdump_len = 0;
  475. }
  476. static void au1000_set_msglevel(struct net_device *dev, u32 value)
  477. {
  478. struct au1000_private *aup = netdev_priv(dev);
  479. aup->msg_enable = value;
  480. }
  481. static u32 au1000_get_msglevel(struct net_device *dev)
  482. {
  483. struct au1000_private *aup = netdev_priv(dev);
  484. return aup->msg_enable;
  485. }
  486. static const struct ethtool_ops au1000_ethtool_ops = {
  487. .get_settings = au1000_get_settings,
  488. .set_settings = au1000_set_settings,
  489. .get_drvinfo = au1000_get_drvinfo,
  490. .get_link = ethtool_op_get_link,
  491. .get_msglevel = au1000_get_msglevel,
  492. .set_msglevel = au1000_set_msglevel,
  493. };
  494. /*
  495. * Initialize the interface.
  496. *
  497. * When the device powers up, the clocks are disabled and the
  498. * mac is in reset state. When the interface is closed, we
  499. * do the same -- reset the device and disable the clocks to
  500. * conserve power. Thus, whenever au1000_init() is called,
  501. * the device should already be in reset state.
  502. */
  503. static int au1000_init(struct net_device *dev)
  504. {
  505. struct au1000_private *aup = netdev_priv(dev);
  506. unsigned long flags;
  507. int i;
  508. u32 control;
  509. netif_dbg(aup, hw, dev, "au1000_init\n");
  510. /* bring the device out of reset */
  511. au1000_enable_mac(dev, 1);
  512. spin_lock_irqsave(&aup->lock, flags);
  513. aup->mac->control = 0;
  514. aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
  515. aup->tx_tail = aup->tx_head;
  516. aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
  517. aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
  518. aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
  519. dev->dev_addr[1]<<8 | dev->dev_addr[0];
  520. for (i = 0; i < NUM_RX_DMA; i++)
  521. aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
  522. au_sync();
  523. control = MAC_RX_ENABLE | MAC_TX_ENABLE;
  524. #ifndef CONFIG_CPU_LITTLE_ENDIAN
  525. control |= MAC_BIG_ENDIAN;
  526. #endif
  527. if (aup->phy_dev) {
  528. if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
  529. control |= MAC_FULL_DUPLEX;
  530. else
  531. control |= MAC_DISABLE_RX_OWN;
  532. } else { /* PHY-less op, assume full-duplex */
  533. control |= MAC_FULL_DUPLEX;
  534. }
  535. aup->mac->control = control;
  536. aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
  537. au_sync();
  538. spin_unlock_irqrestore(&aup->lock, flags);
  539. return 0;
  540. }
  541. static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
  542. {
  543. struct net_device_stats *ps = &dev->stats;
  544. ps->rx_packets++;
  545. if (status & RX_MCAST_FRAME)
  546. ps->multicast++;
  547. if (status & RX_ERROR) {
  548. ps->rx_errors++;
  549. if (status & RX_MISSED_FRAME)
  550. ps->rx_missed_errors++;
  551. if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
  552. ps->rx_length_errors++;
  553. if (status & RX_CRC_ERROR)
  554. ps->rx_crc_errors++;
  555. if (status & RX_COLL)
  556. ps->collisions++;
  557. } else
  558. ps->rx_bytes += status & RX_FRAME_LEN_MASK;
  559. }
  560. /*
  561. * Au1000 receive routine.
  562. */
  563. static int au1000_rx(struct net_device *dev)
  564. {
  565. struct au1000_private *aup = netdev_priv(dev);
  566. struct sk_buff *skb;
  567. volatile struct rx_dma *prxd;
  568. u32 buff_stat, status;
  569. struct db_dest *pDB;
  570. u32 frmlen;
  571. netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
  572. prxd = aup->rx_dma_ring[aup->rx_head];
  573. buff_stat = prxd->buff_stat;
  574. while (buff_stat & RX_T_DONE) {
  575. status = prxd->status;
  576. pDB = aup->rx_db_inuse[aup->rx_head];
  577. au1000_update_rx_stats(dev, status);
  578. if (!(status & RX_ERROR)) {
  579. /* good frame */
  580. frmlen = (status & RX_FRAME_LEN_MASK);
  581. frmlen -= 4; /* Remove FCS */
  582. skb = dev_alloc_skb(frmlen + 2);
  583. if (skb == NULL) {
  584. netdev_err(dev, "Memory squeeze, dropping packet.\n");
  585. dev->stats.rx_dropped++;
  586. continue;
  587. }
  588. skb_reserve(skb, 2); /* 16 byte IP header align */
  589. skb_copy_to_linear_data(skb,
  590. (unsigned char *)pDB->vaddr, frmlen);
  591. skb_put(skb, frmlen);
  592. skb->protocol = eth_type_trans(skb, dev);
  593. netif_rx(skb); /* pass the packet to upper layers */
  594. } else {
  595. if (au1000_debug > 4) {
  596. if (status & RX_MISSED_FRAME)
  597. printk("rx miss\n");
  598. if (status & RX_WDOG_TIMER)
  599. printk("rx wdog\n");
  600. if (status & RX_RUNT)
  601. printk("rx runt\n");
  602. if (status & RX_OVERLEN)
  603. printk("rx overlen\n");
  604. if (status & RX_COLL)
  605. printk("rx coll\n");
  606. if (status & RX_MII_ERROR)
  607. printk("rx mii error\n");
  608. if (status & RX_CRC_ERROR)
  609. printk("rx crc error\n");
  610. if (status & RX_LEN_ERROR)
  611. printk("rx len error\n");
  612. if (status & RX_U_CNTRL_FRAME)
  613. printk("rx u control frame\n");
  614. }
  615. }
  616. prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
  617. aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
  618. au_sync();
  619. /* next descriptor */
  620. prxd = aup->rx_dma_ring[aup->rx_head];
  621. buff_stat = prxd->buff_stat;
  622. }
  623. return 0;
  624. }
  625. static void au1000_update_tx_stats(struct net_device *dev, u32 status)
  626. {
  627. struct au1000_private *aup = netdev_priv(dev);
  628. struct net_device_stats *ps = &dev->stats;
  629. if (status & TX_FRAME_ABORTED) {
  630. if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
  631. if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
  632. /* any other tx errors are only valid
  633. * in half duplex mode */
  634. ps->tx_errors++;
  635. ps->tx_aborted_errors++;
  636. }
  637. } else {
  638. ps->tx_errors++;
  639. ps->tx_aborted_errors++;
  640. if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
  641. ps->tx_carrier_errors++;
  642. }
  643. }
  644. }
  645. /*
  646. * Called from the interrupt service routine to acknowledge
  647. * the TX DONE bits. This is a must if the irq is setup as
  648. * edge triggered.
  649. */
  650. static void au1000_tx_ack(struct net_device *dev)
  651. {
  652. struct au1000_private *aup = netdev_priv(dev);
  653. volatile struct tx_dma *ptxd;
  654. ptxd = aup->tx_dma_ring[aup->tx_tail];
  655. while (ptxd->buff_stat & TX_T_DONE) {
  656. au1000_update_tx_stats(dev, ptxd->status);
  657. ptxd->buff_stat &= ~TX_T_DONE;
  658. ptxd->len = 0;
  659. au_sync();
  660. aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
  661. ptxd = aup->tx_dma_ring[aup->tx_tail];
  662. if (aup->tx_full) {
  663. aup->tx_full = 0;
  664. netif_wake_queue(dev);
  665. }
  666. }
  667. }
  668. /*
  669. * Au1000 interrupt service routine.
  670. */
  671. static irqreturn_t au1000_interrupt(int irq, void *dev_id)
  672. {
  673. struct net_device *dev = dev_id;
  674. /* Handle RX interrupts first to minimize chance of overrun */
  675. au1000_rx(dev);
  676. au1000_tx_ack(dev);
  677. return IRQ_RETVAL(1);
  678. }
  679. static int au1000_open(struct net_device *dev)
  680. {
  681. int retval;
  682. struct au1000_private *aup = netdev_priv(dev);
  683. netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
  684. retval = request_irq(dev->irq, au1000_interrupt, 0,
  685. dev->name, dev);
  686. if (retval) {
  687. netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
  688. return retval;
  689. }
  690. retval = au1000_init(dev);
  691. if (retval) {
  692. netdev_err(dev, "error in au1000_init\n");
  693. free_irq(dev->irq, dev);
  694. return retval;
  695. }
  696. if (aup->phy_dev) {
  697. /* cause the PHY state machine to schedule a link state check */
  698. aup->phy_dev->state = PHY_CHANGELINK;
  699. phy_start(aup->phy_dev);
  700. }
  701. netif_start_queue(dev);
  702. netif_dbg(aup, drv, dev, "open: Initialization done.\n");
  703. return 0;
  704. }
  705. static int au1000_close(struct net_device *dev)
  706. {
  707. unsigned long flags;
  708. struct au1000_private *const aup = netdev_priv(dev);
  709. netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
  710. if (aup->phy_dev)
  711. phy_stop(aup->phy_dev);
  712. spin_lock_irqsave(&aup->lock, flags);
  713. au1000_reset_mac_unlocked(dev);
  714. /* stop the device */
  715. netif_stop_queue(dev);
  716. /* disable the interrupt */
  717. free_irq(dev->irq, dev);
  718. spin_unlock_irqrestore(&aup->lock, flags);
  719. return 0;
  720. }
  721. /*
  722. * Au1000 transmit routine.
  723. */
  724. static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
  725. {
  726. struct au1000_private *aup = netdev_priv(dev);
  727. struct net_device_stats *ps = &dev->stats;
  728. volatile struct tx_dma *ptxd;
  729. u32 buff_stat;
  730. struct db_dest *pDB;
  731. int i;
  732. netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
  733. (unsigned)aup, skb->len,
  734. skb->data, aup->tx_head);
  735. ptxd = aup->tx_dma_ring[aup->tx_head];
  736. buff_stat = ptxd->buff_stat;
  737. if (buff_stat & TX_DMA_ENABLE) {
  738. /* We've wrapped around and the transmitter is still busy */
  739. netif_stop_queue(dev);
  740. aup->tx_full = 1;
  741. return NETDEV_TX_BUSY;
  742. } else if (buff_stat & TX_T_DONE) {
  743. au1000_update_tx_stats(dev, ptxd->status);
  744. ptxd->len = 0;
  745. }
  746. if (aup->tx_full) {
  747. aup->tx_full = 0;
  748. netif_wake_queue(dev);
  749. }
  750. pDB = aup->tx_db_inuse[aup->tx_head];
  751. skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
  752. if (skb->len < ETH_ZLEN) {
  753. for (i = skb->len; i < ETH_ZLEN; i++)
  754. ((char *)pDB->vaddr)[i] = 0;
  755. ptxd->len = ETH_ZLEN;
  756. } else
  757. ptxd->len = skb->len;
  758. ps->tx_packets++;
  759. ps->tx_bytes += ptxd->len;
  760. ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
  761. au_sync();
  762. dev_kfree_skb(skb);
  763. aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
  764. return NETDEV_TX_OK;
  765. }
  766. /*
  767. * The Tx ring has been full longer than the watchdog timeout
  768. * value. The transmitter must be hung?
  769. */
  770. static void au1000_tx_timeout(struct net_device *dev)
  771. {
  772. netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
  773. au1000_reset_mac(dev);
  774. au1000_init(dev);
  775. dev->trans_start = jiffies; /* prevent tx timeout */
  776. netif_wake_queue(dev);
  777. }
  778. static void au1000_multicast_list(struct net_device *dev)
  779. {
  780. struct au1000_private *aup = netdev_priv(dev);
  781. netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
  782. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  783. aup->mac->control |= MAC_PROMISCUOUS;
  784. } else if ((dev->flags & IFF_ALLMULTI) ||
  785. netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
  786. aup->mac->control |= MAC_PASS_ALL_MULTI;
  787. aup->mac->control &= ~MAC_PROMISCUOUS;
  788. netdev_info(dev, "Pass all multicast\n");
  789. } else {
  790. struct netdev_hw_addr *ha;
  791. u32 mc_filter[2]; /* Multicast hash filter */
  792. mc_filter[1] = mc_filter[0] = 0;
  793. netdev_for_each_mc_addr(ha, dev)
  794. set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
  795. (long *)mc_filter);
  796. aup->mac->multi_hash_high = mc_filter[1];
  797. aup->mac->multi_hash_low = mc_filter[0];
  798. aup->mac->control &= ~MAC_PROMISCUOUS;
  799. aup->mac->control |= MAC_HASH_MODE;
  800. }
  801. }
  802. static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  803. {
  804. struct au1000_private *aup = netdev_priv(dev);
  805. if (!netif_running(dev))
  806. return -EINVAL;
  807. if (!aup->phy_dev)
  808. return -EINVAL; /* PHY not controllable */
  809. return phy_mii_ioctl(aup->phy_dev, rq, cmd);
  810. }
  811. static const struct net_device_ops au1000_netdev_ops = {
  812. .ndo_open = au1000_open,
  813. .ndo_stop = au1000_close,
  814. .ndo_start_xmit = au1000_tx,
  815. .ndo_set_multicast_list = au1000_multicast_list,
  816. .ndo_do_ioctl = au1000_ioctl,
  817. .ndo_tx_timeout = au1000_tx_timeout,
  818. .ndo_set_mac_address = eth_mac_addr,
  819. .ndo_validate_addr = eth_validate_addr,
  820. .ndo_change_mtu = eth_change_mtu,
  821. };
  822. static int __devinit au1000_probe(struct platform_device *pdev)
  823. {
  824. static unsigned version_printed;
  825. struct au1000_private *aup = NULL;
  826. struct au1000_eth_platform_data *pd;
  827. struct net_device *dev = NULL;
  828. struct db_dest *pDB, *pDBfree;
  829. int irq, i, err = 0;
  830. struct resource *base, *macen;
  831. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  832. if (!base) {
  833. dev_err(&pdev->dev, "failed to retrieve base register\n");
  834. err = -ENODEV;
  835. goto out;
  836. }
  837. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  838. if (!macen) {
  839. dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
  840. err = -ENODEV;
  841. goto out;
  842. }
  843. irq = platform_get_irq(pdev, 0);
  844. if (irq < 0) {
  845. dev_err(&pdev->dev, "failed to retrieve IRQ\n");
  846. err = -ENODEV;
  847. goto out;
  848. }
  849. if (!request_mem_region(base->start, resource_size(base),
  850. pdev->name)) {
  851. dev_err(&pdev->dev, "failed to request memory region for base registers\n");
  852. err = -ENXIO;
  853. goto out;
  854. }
  855. if (!request_mem_region(macen->start, resource_size(macen),
  856. pdev->name)) {
  857. dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
  858. err = -ENXIO;
  859. goto err_request;
  860. }
  861. dev = alloc_etherdev(sizeof(struct au1000_private));
  862. if (!dev) {
  863. dev_err(&pdev->dev, "alloc_etherdev failed\n");
  864. err = -ENOMEM;
  865. goto err_alloc;
  866. }
  867. SET_NETDEV_DEV(dev, &pdev->dev);
  868. platform_set_drvdata(pdev, dev);
  869. aup = netdev_priv(dev);
  870. spin_lock_init(&aup->lock);
  871. aup->msg_enable = (au1000_debug < 4 ?
  872. AU1000_DEF_MSG_ENABLE : au1000_debug);
  873. /* Allocate the data buffers */
  874. /* Snooping works fine with eth on all au1xxx */
  875. aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
  876. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  877. &aup->dma_addr, 0);
  878. if (!aup->vaddr) {
  879. dev_err(&pdev->dev, "failed to allocate data buffers\n");
  880. err = -ENOMEM;
  881. goto err_vaddr;
  882. }
  883. /* aup->mac is the base address of the MAC's registers */
  884. aup->mac = (volatile struct mac_reg *)
  885. ioremap_nocache(base->start, resource_size(base));
  886. if (!aup->mac) {
  887. dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
  888. err = -ENXIO;
  889. goto err_remap1;
  890. }
  891. /* Setup some variables for quick register address access */
  892. aup->enable = (volatile u32 *)ioremap_nocache(macen->start,
  893. resource_size(macen));
  894. if (!aup->enable) {
  895. dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
  896. err = -ENXIO;
  897. goto err_remap2;
  898. }
  899. aup->mac_id = pdev->id;
  900. if (pdev->id == 0)
  901. au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
  902. else if (pdev->id == 1)
  903. au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
  904. /* set a random MAC now in case platform_data doesn't provide one */
  905. random_ether_addr(dev->dev_addr);
  906. *aup->enable = 0;
  907. aup->mac_enabled = 0;
  908. pd = pdev->dev.platform_data;
  909. if (!pd) {
  910. dev_info(&pdev->dev, "no platform_data passed,"
  911. " PHY search on MAC0\n");
  912. aup->phy1_search_mac0 = 1;
  913. } else {
  914. if (is_valid_ether_addr(pd->mac))
  915. memcpy(dev->dev_addr, pd->mac, 6);
  916. aup->phy_static_config = pd->phy_static_config;
  917. aup->phy_search_highest_addr = pd->phy_search_highest_addr;
  918. aup->phy1_search_mac0 = pd->phy1_search_mac0;
  919. aup->phy_addr = pd->phy_addr;
  920. aup->phy_busid = pd->phy_busid;
  921. aup->phy_irq = pd->phy_irq;
  922. }
  923. if (aup->phy_busid && aup->phy_busid > 0) {
  924. dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
  925. err = -ENODEV;
  926. goto err_mdiobus_alloc;
  927. }
  928. aup->mii_bus = mdiobus_alloc();
  929. if (aup->mii_bus == NULL) {
  930. dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
  931. err = -ENOMEM;
  932. goto err_mdiobus_alloc;
  933. }
  934. aup->mii_bus->priv = dev;
  935. aup->mii_bus->read = au1000_mdiobus_read;
  936. aup->mii_bus->write = au1000_mdiobus_write;
  937. aup->mii_bus->reset = au1000_mdiobus_reset;
  938. aup->mii_bus->name = "au1000_eth_mii";
  939. snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
  940. aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  941. if (aup->mii_bus->irq == NULL)
  942. goto err_out;
  943. for (i = 0; i < PHY_MAX_ADDR; ++i)
  944. aup->mii_bus->irq[i] = PHY_POLL;
  945. /* if known, set corresponding PHY IRQs */
  946. if (aup->phy_static_config)
  947. if (aup->phy_irq && aup->phy_busid == aup->mac_id)
  948. aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
  949. err = mdiobus_register(aup->mii_bus);
  950. if (err) {
  951. dev_err(&pdev->dev, "failed to register MDIO bus\n");
  952. goto err_mdiobus_reg;
  953. }
  954. if (au1000_mii_probe(dev) != 0)
  955. goto err_out;
  956. pDBfree = NULL;
  957. /* setup the data buffer descriptors and attach a buffer to each one */
  958. pDB = aup->db;
  959. for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
  960. pDB->pnext = pDBfree;
  961. pDBfree = pDB;
  962. pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
  963. pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
  964. pDB++;
  965. }
  966. aup->pDBfree = pDBfree;
  967. for (i = 0; i < NUM_RX_DMA; i++) {
  968. pDB = au1000_GetFreeDB(aup);
  969. if (!pDB)
  970. goto err_out;
  971. aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  972. aup->rx_db_inuse[i] = pDB;
  973. }
  974. for (i = 0; i < NUM_TX_DMA; i++) {
  975. pDB = au1000_GetFreeDB(aup);
  976. if (!pDB)
  977. goto err_out;
  978. aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  979. aup->tx_dma_ring[i]->len = 0;
  980. aup->tx_db_inuse[i] = pDB;
  981. }
  982. dev->base_addr = base->start;
  983. dev->irq = irq;
  984. dev->netdev_ops = &au1000_netdev_ops;
  985. SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
  986. dev->watchdog_timeo = ETH_TX_TIMEOUT;
  987. /*
  988. * The boot code uses the ethernet controller, so reset it to start
  989. * fresh. au1000_init() expects that the device is in reset state.
  990. */
  991. au1000_reset_mac(dev);
  992. err = register_netdev(dev);
  993. if (err) {
  994. netdev_err(dev, "Cannot register net device, aborting.\n");
  995. goto err_out;
  996. }
  997. netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
  998. (unsigned long)base->start, irq);
  999. if (version_printed++ == 0)
  1000. printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
  1001. return 0;
  1002. err_out:
  1003. if (aup->mii_bus != NULL)
  1004. mdiobus_unregister(aup->mii_bus);
  1005. /* here we should have a valid dev plus aup-> register addresses
  1006. * so we can reset the mac properly.*/
  1007. au1000_reset_mac(dev);
  1008. for (i = 0; i < NUM_RX_DMA; i++) {
  1009. if (aup->rx_db_inuse[i])
  1010. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1011. }
  1012. for (i = 0; i < NUM_TX_DMA; i++) {
  1013. if (aup->tx_db_inuse[i])
  1014. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1015. }
  1016. err_mdiobus_reg:
  1017. mdiobus_free(aup->mii_bus);
  1018. err_mdiobus_alloc:
  1019. iounmap(aup->enable);
  1020. err_remap2:
  1021. iounmap(aup->mac);
  1022. err_remap1:
  1023. dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1024. (void *)aup->vaddr, aup->dma_addr);
  1025. err_vaddr:
  1026. free_netdev(dev);
  1027. err_alloc:
  1028. release_mem_region(macen->start, resource_size(macen));
  1029. err_request:
  1030. release_mem_region(base->start, resource_size(base));
  1031. out:
  1032. return err;
  1033. }
  1034. static int __devexit au1000_remove(struct platform_device *pdev)
  1035. {
  1036. struct net_device *dev = platform_get_drvdata(pdev);
  1037. struct au1000_private *aup = netdev_priv(dev);
  1038. int i;
  1039. struct resource *base, *macen;
  1040. platform_set_drvdata(pdev, NULL);
  1041. unregister_netdev(dev);
  1042. mdiobus_unregister(aup->mii_bus);
  1043. mdiobus_free(aup->mii_bus);
  1044. for (i = 0; i < NUM_RX_DMA; i++)
  1045. if (aup->rx_db_inuse[i])
  1046. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1047. for (i = 0; i < NUM_TX_DMA; i++)
  1048. if (aup->tx_db_inuse[i])
  1049. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1050. dma_free_noncoherent(NULL, MAX_BUF_SIZE *
  1051. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1052. (void *)aup->vaddr, aup->dma_addr);
  1053. iounmap(aup->mac);
  1054. iounmap(aup->enable);
  1055. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1056. release_mem_region(base->start, resource_size(base));
  1057. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1058. release_mem_region(macen->start, resource_size(macen));
  1059. free_netdev(dev);
  1060. return 0;
  1061. }
  1062. static struct platform_driver au1000_eth_driver = {
  1063. .probe = au1000_probe,
  1064. .remove = __devexit_p(au1000_remove),
  1065. .driver = {
  1066. .name = "au1000-eth",
  1067. .owner = THIS_MODULE,
  1068. },
  1069. };
  1070. MODULE_ALIAS("platform:au1000-eth");
  1071. static int __init au1000_init_module(void)
  1072. {
  1073. return platform_driver_register(&au1000_eth_driver);
  1074. }
  1075. static void __exit au1000_exit_module(void)
  1076. {
  1077. platform_driver_unregister(&au1000_eth_driver);
  1078. }
  1079. module_init(au1000_init_module);
  1080. module_exit(au1000_exit_module);