twl4030.c 60 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /* codec private data */
  117. struct twl4030_priv {
  118. unsigned int bypass_state;
  119. unsigned int codec_powered;
  120. unsigned int codec_muted;
  121. struct snd_pcm_substream *master_substream;
  122. struct snd_pcm_substream *slave_substream;
  123. unsigned int configured;
  124. unsigned int rate;
  125. unsigned int sample_bits;
  126. unsigned int channels;
  127. };
  128. /*
  129. * read twl4030 register cache
  130. */
  131. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  132. unsigned int reg)
  133. {
  134. u8 *cache = codec->reg_cache;
  135. if (reg >= TWL4030_CACHEREGNUM)
  136. return -EIO;
  137. return cache[reg];
  138. }
  139. /*
  140. * write twl4030 register cache
  141. */
  142. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  143. u8 reg, u8 value)
  144. {
  145. u8 *cache = codec->reg_cache;
  146. if (reg >= TWL4030_CACHEREGNUM)
  147. return;
  148. cache[reg] = value;
  149. }
  150. /*
  151. * write to the twl4030 register space
  152. */
  153. static int twl4030_write(struct snd_soc_codec *codec,
  154. unsigned int reg, unsigned int value)
  155. {
  156. twl4030_write_reg_cache(codec, reg, value);
  157. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  158. }
  159. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  160. {
  161. struct twl4030_priv *twl4030 = codec->private_data;
  162. u8 mode;
  163. if (enable == twl4030->codec_powered)
  164. return;
  165. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  166. if (enable)
  167. mode |= TWL4030_CODECPDZ;
  168. else
  169. mode &= ~TWL4030_CODECPDZ;
  170. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  171. twl4030->codec_powered = enable;
  172. /* REVISIT: this delay is present in TI sample drivers */
  173. /* but there seems to be no TRM requirement for it */
  174. udelay(10);
  175. }
  176. static void twl4030_init_chip(struct snd_soc_codec *codec)
  177. {
  178. int i;
  179. /* clear CODECPDZ prior to setting register defaults */
  180. twl4030_codec_enable(codec, 0);
  181. /* set all audio section registers to reasonable defaults */
  182. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  183. twl4030_write(codec, i, twl4030_reg[i]);
  184. }
  185. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  186. {
  187. struct twl4030_priv *twl4030 = codec->private_data;
  188. u8 reg_val;
  189. if (mute == twl4030->codec_muted)
  190. return;
  191. if (mute) {
  192. /* Bypass the reg_cache and mute the volumes
  193. * Headset mute is done in it's own event handler
  194. * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
  195. */
  196. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
  197. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  198. reg_val & (~TWL4030_EAR_GAIN),
  199. TWL4030_REG_EAR_CTL);
  200. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
  201. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  202. reg_val & (~TWL4030_PREDL_GAIN),
  203. TWL4030_REG_PREDL_CTL);
  204. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
  205. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  206. reg_val & (~TWL4030_PREDR_GAIN),
  207. TWL4030_REG_PREDL_CTL);
  208. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
  209. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  210. reg_val & (~TWL4030_PRECKL_GAIN),
  211. TWL4030_REG_PRECKL_CTL);
  212. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
  213. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  214. reg_val & (~TWL4030_PRECKR_GAIN),
  215. TWL4030_REG_PRECKR_CTL);
  216. /* Disable PLL */
  217. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  218. reg_val &= ~TWL4030_APLL_EN;
  219. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  220. } else {
  221. /* Restore the volumes
  222. * Headset mute is done in it's own event handler
  223. * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
  224. */
  225. twl4030_write(codec, TWL4030_REG_EAR_CTL,
  226. twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
  227. twl4030_write(codec, TWL4030_REG_PREDL_CTL,
  228. twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
  229. twl4030_write(codec, TWL4030_REG_PREDR_CTL,
  230. twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
  231. twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
  232. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
  233. twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
  234. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
  235. /* Enable PLL */
  236. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  237. reg_val |= TWL4030_APLL_EN;
  238. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  239. }
  240. twl4030->codec_muted = mute;
  241. }
  242. static void twl4030_power_up(struct snd_soc_codec *codec)
  243. {
  244. struct twl4030_priv *twl4030 = codec->private_data;
  245. u8 anamicl, regmisc1, byte;
  246. int i = 0;
  247. if (twl4030->codec_powered)
  248. return;
  249. /* set CODECPDZ to turn on codec */
  250. twl4030_codec_enable(codec, 1);
  251. /* initiate offset cancellation */
  252. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  253. twl4030_write(codec, TWL4030_REG_ANAMICL,
  254. anamicl | TWL4030_CNCL_OFFSET_START);
  255. /* wait for offset cancellation to complete */
  256. do {
  257. /* this takes a little while, so don't slam i2c */
  258. udelay(2000);
  259. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  260. TWL4030_REG_ANAMICL);
  261. } while ((i++ < 100) &&
  262. ((byte & TWL4030_CNCL_OFFSET_START) ==
  263. TWL4030_CNCL_OFFSET_START));
  264. /* Make sure that the reg_cache has the same value as the HW */
  265. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  266. /* anti-pop when changing analog gain */
  267. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  268. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  269. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  270. /* toggle CODECPDZ as per TRM */
  271. twl4030_codec_enable(codec, 0);
  272. twl4030_codec_enable(codec, 1);
  273. }
  274. /*
  275. * Unconditional power down
  276. */
  277. static void twl4030_power_down(struct snd_soc_codec *codec)
  278. {
  279. /* power down */
  280. twl4030_codec_enable(codec, 0);
  281. }
  282. /* Earpiece */
  283. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  284. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  285. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  286. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  287. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  288. };
  289. /* PreDrive Left */
  290. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  291. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  292. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  293. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  294. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  295. };
  296. /* PreDrive Right */
  297. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  298. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  299. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  300. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  301. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  302. };
  303. /* Headset Left */
  304. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  305. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  306. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  307. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  308. };
  309. /* Headset Right */
  310. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  311. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  312. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  313. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  314. };
  315. /* Carkit Left */
  316. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  317. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  318. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  319. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  320. };
  321. /* Carkit Right */
  322. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  323. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  324. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  325. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  326. };
  327. /* Handsfree Left */
  328. static const char *twl4030_handsfreel_texts[] =
  329. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  330. static const struct soc_enum twl4030_handsfreel_enum =
  331. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  332. ARRAY_SIZE(twl4030_handsfreel_texts),
  333. twl4030_handsfreel_texts);
  334. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  335. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  336. /* Handsfree Right */
  337. static const char *twl4030_handsfreer_texts[] =
  338. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  339. static const struct soc_enum twl4030_handsfreer_enum =
  340. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  341. ARRAY_SIZE(twl4030_handsfreer_texts),
  342. twl4030_handsfreer_texts);
  343. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  344. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  345. /* Vibra */
  346. /* Vibra audio path selection */
  347. static const char *twl4030_vibra_texts[] =
  348. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  349. static const struct soc_enum twl4030_vibra_enum =
  350. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  351. ARRAY_SIZE(twl4030_vibra_texts),
  352. twl4030_vibra_texts);
  353. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  354. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  355. /* Vibra path selection: local vibrator (PWM) or audio driven */
  356. static const char *twl4030_vibrapath_texts[] =
  357. {"Local vibrator", "Audio"};
  358. static const struct soc_enum twl4030_vibrapath_enum =
  359. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  360. ARRAY_SIZE(twl4030_vibrapath_texts),
  361. twl4030_vibrapath_texts);
  362. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  363. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  364. /* Left analog microphone selection */
  365. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  366. SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
  367. SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
  368. SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
  369. SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
  370. };
  371. /* Right analog microphone selection */
  372. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  373. SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
  374. SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
  375. };
  376. /* TX1 L/R Analog/Digital microphone selection */
  377. static const char *twl4030_micpathtx1_texts[] =
  378. {"Analog", "Digimic0"};
  379. static const struct soc_enum twl4030_micpathtx1_enum =
  380. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  381. ARRAY_SIZE(twl4030_micpathtx1_texts),
  382. twl4030_micpathtx1_texts);
  383. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  384. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  385. /* TX2 L/R Analog/Digital microphone selection */
  386. static const char *twl4030_micpathtx2_texts[] =
  387. {"Analog", "Digimic1"};
  388. static const struct soc_enum twl4030_micpathtx2_enum =
  389. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  390. ARRAY_SIZE(twl4030_micpathtx2_texts),
  391. twl4030_micpathtx2_texts);
  392. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  393. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  394. /* Analog bypass for AudioR1 */
  395. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  396. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  397. /* Analog bypass for AudioL1 */
  398. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  399. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  400. /* Analog bypass for AudioR2 */
  401. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  402. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  403. /* Analog bypass for AudioL2 */
  404. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  405. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  406. /* Analog bypass for Voice */
  407. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  408. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  409. /* Digital bypass gain, 0 mutes the bypass */
  410. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  411. TLV_DB_RANGE_HEAD(2),
  412. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  413. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  414. };
  415. /* Digital bypass left (TX1L -> RX2L) */
  416. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  417. SOC_DAPM_SINGLE_TLV("Volume",
  418. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  419. twl4030_dapm_dbypass_tlv);
  420. /* Digital bypass right (TX1R -> RX2R) */
  421. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  422. SOC_DAPM_SINGLE_TLV("Volume",
  423. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  424. twl4030_dapm_dbypass_tlv);
  425. /*
  426. * Voice Sidetone GAIN volume control:
  427. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  428. */
  429. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  430. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  431. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  432. SOC_DAPM_SINGLE_TLV("Volume",
  433. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  434. twl4030_dapm_dbypassv_tlv);
  435. static int micpath_event(struct snd_soc_dapm_widget *w,
  436. struct snd_kcontrol *kcontrol, int event)
  437. {
  438. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  439. unsigned char adcmicsel, micbias_ctl;
  440. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  441. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  442. /* Prepare the bits for the given TX path:
  443. * shift_l == 0: TX1 microphone path
  444. * shift_l == 2: TX2 microphone path */
  445. if (e->shift_l) {
  446. /* TX2 microphone path */
  447. if (adcmicsel & TWL4030_TX2IN_SEL)
  448. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  449. else
  450. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  451. } else {
  452. /* TX1 microphone path */
  453. if (adcmicsel & TWL4030_TX1IN_SEL)
  454. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  455. else
  456. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  457. }
  458. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  459. return 0;
  460. }
  461. static int handsfree_event(struct snd_soc_dapm_widget *w,
  462. struct snd_kcontrol *kcontrol, int event)
  463. {
  464. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  465. unsigned char hs_ctl;
  466. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  467. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  468. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  469. twl4030_write(w->codec, e->reg, hs_ctl);
  470. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  471. twl4030_write(w->codec, e->reg, hs_ctl);
  472. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  473. twl4030_write(w->codec, e->reg, hs_ctl);
  474. } else {
  475. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  476. | TWL4030_HF_CTL_HB_EN);
  477. twl4030_write(w->codec, e->reg, hs_ctl);
  478. }
  479. return 0;
  480. }
  481. static int headsetl_event(struct snd_soc_dapm_widget *w,
  482. struct snd_kcontrol *kcontrol, int event)
  483. {
  484. unsigned char hs_gain, hs_pop;
  485. /* Save the current volume */
  486. hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
  487. hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
  488. switch (event) {
  489. case SND_SOC_DAPM_POST_PMU:
  490. /* Do the anti-pop/bias ramp enable according to the TRM */
  491. hs_pop |= TWL4030_VMID_EN;
  492. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  493. /* Is this needed? Can we just use whatever gain here? */
  494. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
  495. (hs_gain & (~0x0f)) | 0x0a);
  496. hs_pop |= TWL4030_RAMP_EN;
  497. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  498. /* Restore the original volume */
  499. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  500. break;
  501. case SND_SOC_DAPM_POST_PMD:
  502. /* Do the anti-pop/bias ramp disable according to the TRM */
  503. hs_pop &= ~TWL4030_RAMP_EN;
  504. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  505. /* Bypass the reg_cache to mute the headset */
  506. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  507. hs_gain & (~0x0f),
  508. TWL4030_REG_HS_GAIN_SET);
  509. hs_pop &= ~TWL4030_VMID_EN;
  510. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  511. break;
  512. }
  513. return 0;
  514. }
  515. static int bypass_event(struct snd_soc_dapm_widget *w,
  516. struct snd_kcontrol *kcontrol, int event)
  517. {
  518. struct soc_mixer_control *m =
  519. (struct soc_mixer_control *)w->kcontrols->private_value;
  520. struct twl4030_priv *twl4030 = w->codec->private_data;
  521. unsigned char reg, misc;
  522. reg = twl4030_read_reg_cache(w->codec, m->reg);
  523. if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  524. /* Analog bypass */
  525. if (reg & (1 << m->shift))
  526. twl4030->bypass_state |=
  527. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  528. else
  529. twl4030->bypass_state &=
  530. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  531. } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
  532. /* Analog voice bypass */
  533. if (reg & (1 << m->shift))
  534. twl4030->bypass_state |= (1 << 4);
  535. else
  536. twl4030->bypass_state &= ~(1 << 4);
  537. } else if (m->reg == TWL4030_REG_VSTPGA) {
  538. /* Voice digital bypass */
  539. if (reg)
  540. twl4030->bypass_state |= (1 << 5);
  541. else
  542. twl4030->bypass_state &= ~(1 << 5);
  543. } else {
  544. /* Digital bypass */
  545. if (reg & (0x7 << m->shift))
  546. twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
  547. else
  548. twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
  549. }
  550. /* Enable master analog loopback mode if any analog switch is enabled*/
  551. misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
  552. if (twl4030->bypass_state & 0x1F)
  553. misc |= TWL4030_FMLOOP_EN;
  554. else
  555. misc &= ~TWL4030_FMLOOP_EN;
  556. twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
  557. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  558. if (twl4030->bypass_state)
  559. twl4030_codec_mute(w->codec, 0);
  560. else
  561. twl4030_codec_mute(w->codec, 1);
  562. }
  563. return 0;
  564. }
  565. /*
  566. * Some of the gain controls in TWL (mostly those which are associated with
  567. * the outputs) are implemented in an interesting way:
  568. * 0x0 : Power down (mute)
  569. * 0x1 : 6dB
  570. * 0x2 : 0 dB
  571. * 0x3 : -6 dB
  572. * Inverting not going to help with these.
  573. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  574. */
  575. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  576. xinvert, tlv_array) \
  577. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  578. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  579. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  580. .tlv.p = (tlv_array), \
  581. .info = snd_soc_info_volsw, \
  582. .get = snd_soc_get_volsw_twl4030, \
  583. .put = snd_soc_put_volsw_twl4030, \
  584. .private_value = (unsigned long)&(struct soc_mixer_control) \
  585. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  586. .max = xmax, .invert = xinvert} }
  587. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  588. xinvert, tlv_array) \
  589. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  590. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  591. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  592. .tlv.p = (tlv_array), \
  593. .info = snd_soc_info_volsw_2r, \
  594. .get = snd_soc_get_volsw_r2_twl4030,\
  595. .put = snd_soc_put_volsw_r2_twl4030, \
  596. .private_value = (unsigned long)&(struct soc_mixer_control) \
  597. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  598. .rshift = xshift, .max = xmax, .invert = xinvert} }
  599. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  600. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  601. xinvert, tlv_array)
  602. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  603. struct snd_ctl_elem_value *ucontrol)
  604. {
  605. struct soc_mixer_control *mc =
  606. (struct soc_mixer_control *)kcontrol->private_value;
  607. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  608. unsigned int reg = mc->reg;
  609. unsigned int shift = mc->shift;
  610. unsigned int rshift = mc->rshift;
  611. int max = mc->max;
  612. int mask = (1 << fls(max)) - 1;
  613. ucontrol->value.integer.value[0] =
  614. (snd_soc_read(codec, reg) >> shift) & mask;
  615. if (ucontrol->value.integer.value[0])
  616. ucontrol->value.integer.value[0] =
  617. max + 1 - ucontrol->value.integer.value[0];
  618. if (shift != rshift) {
  619. ucontrol->value.integer.value[1] =
  620. (snd_soc_read(codec, reg) >> rshift) & mask;
  621. if (ucontrol->value.integer.value[1])
  622. ucontrol->value.integer.value[1] =
  623. max + 1 - ucontrol->value.integer.value[1];
  624. }
  625. return 0;
  626. }
  627. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  628. struct snd_ctl_elem_value *ucontrol)
  629. {
  630. struct soc_mixer_control *mc =
  631. (struct soc_mixer_control *)kcontrol->private_value;
  632. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  633. unsigned int reg = mc->reg;
  634. unsigned int shift = mc->shift;
  635. unsigned int rshift = mc->rshift;
  636. int max = mc->max;
  637. int mask = (1 << fls(max)) - 1;
  638. unsigned short val, val2, val_mask;
  639. val = (ucontrol->value.integer.value[0] & mask);
  640. val_mask = mask << shift;
  641. if (val)
  642. val = max + 1 - val;
  643. val = val << shift;
  644. if (shift != rshift) {
  645. val2 = (ucontrol->value.integer.value[1] & mask);
  646. val_mask |= mask << rshift;
  647. if (val2)
  648. val2 = max + 1 - val2;
  649. val |= val2 << rshift;
  650. }
  651. return snd_soc_update_bits(codec, reg, val_mask, val);
  652. }
  653. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  654. struct snd_ctl_elem_value *ucontrol)
  655. {
  656. struct soc_mixer_control *mc =
  657. (struct soc_mixer_control *)kcontrol->private_value;
  658. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  659. unsigned int reg = mc->reg;
  660. unsigned int reg2 = mc->rreg;
  661. unsigned int shift = mc->shift;
  662. int max = mc->max;
  663. int mask = (1<<fls(max))-1;
  664. ucontrol->value.integer.value[0] =
  665. (snd_soc_read(codec, reg) >> shift) & mask;
  666. ucontrol->value.integer.value[1] =
  667. (snd_soc_read(codec, reg2) >> shift) & mask;
  668. if (ucontrol->value.integer.value[0])
  669. ucontrol->value.integer.value[0] =
  670. max + 1 - ucontrol->value.integer.value[0];
  671. if (ucontrol->value.integer.value[1])
  672. ucontrol->value.integer.value[1] =
  673. max + 1 - ucontrol->value.integer.value[1];
  674. return 0;
  675. }
  676. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  677. struct snd_ctl_elem_value *ucontrol)
  678. {
  679. struct soc_mixer_control *mc =
  680. (struct soc_mixer_control *)kcontrol->private_value;
  681. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  682. unsigned int reg = mc->reg;
  683. unsigned int reg2 = mc->rreg;
  684. unsigned int shift = mc->shift;
  685. int max = mc->max;
  686. int mask = (1 << fls(max)) - 1;
  687. int err;
  688. unsigned short val, val2, val_mask;
  689. val_mask = mask << shift;
  690. val = (ucontrol->value.integer.value[0] & mask);
  691. val2 = (ucontrol->value.integer.value[1] & mask);
  692. if (val)
  693. val = max + 1 - val;
  694. if (val2)
  695. val2 = max + 1 - val2;
  696. val = val << shift;
  697. val2 = val2 << shift;
  698. err = snd_soc_update_bits(codec, reg, val_mask, val);
  699. if (err < 0)
  700. return err;
  701. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  702. return err;
  703. }
  704. /*
  705. * FGAIN volume control:
  706. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  707. */
  708. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  709. /*
  710. * CGAIN volume control:
  711. * 0 dB to 12 dB in 6 dB steps
  712. * value 2 and 3 means 12 dB
  713. */
  714. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  715. /*
  716. * Voice Downlink GAIN volume control:
  717. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  718. */
  719. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  720. /*
  721. * Analog playback gain
  722. * -24 dB to 12 dB in 2 dB steps
  723. */
  724. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  725. /*
  726. * Gain controls tied to outputs
  727. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  728. */
  729. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  730. /*
  731. * Gain control for earpiece amplifier
  732. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  733. */
  734. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  735. /*
  736. * Capture gain after the ADCs
  737. * from 0 dB to 31 dB in 1 dB steps
  738. */
  739. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  740. /*
  741. * Gain control for input amplifiers
  742. * 0 dB to 30 dB in 6 dB steps
  743. */
  744. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  745. static const char *twl4030_rampdelay_texts[] = {
  746. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  747. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  748. "3495/2581/1748 ms"
  749. };
  750. static const struct soc_enum twl4030_rampdelay_enum =
  751. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  752. ARRAY_SIZE(twl4030_rampdelay_texts),
  753. twl4030_rampdelay_texts);
  754. /* Vibra H-bridge direction mode */
  755. static const char *twl4030_vibradirmode_texts[] = {
  756. "Vibra H-bridge direction", "Audio data MSB",
  757. };
  758. static const struct soc_enum twl4030_vibradirmode_enum =
  759. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  760. ARRAY_SIZE(twl4030_vibradirmode_texts),
  761. twl4030_vibradirmode_texts);
  762. /* Vibra H-bridge direction */
  763. static const char *twl4030_vibradir_texts[] = {
  764. "Positive polarity", "Negative polarity",
  765. };
  766. static const struct soc_enum twl4030_vibradir_enum =
  767. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  768. ARRAY_SIZE(twl4030_vibradir_texts),
  769. twl4030_vibradir_texts);
  770. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  771. /* Common playback gain controls */
  772. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  773. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  774. 0, 0x3f, 0, digital_fine_tlv),
  775. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  776. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  777. 0, 0x3f, 0, digital_fine_tlv),
  778. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  779. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  780. 6, 0x2, 0, digital_coarse_tlv),
  781. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  782. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  783. 6, 0x2, 0, digital_coarse_tlv),
  784. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  785. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  786. 3, 0x12, 1, analog_tlv),
  787. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  788. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  789. 3, 0x12, 1, analog_tlv),
  790. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  791. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  792. 1, 1, 0),
  793. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  794. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  795. 1, 1, 0),
  796. /* Common voice downlink gain controls */
  797. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  798. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  799. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  800. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  801. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  802. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  803. /* Separate output gain controls */
  804. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  805. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  806. 4, 3, 0, output_tvl),
  807. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  808. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  809. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  810. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  811. 4, 3, 0, output_tvl),
  812. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  813. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  814. /* Common capture gain controls */
  815. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  816. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  817. 0, 0x1f, 0, digital_capture_tlv),
  818. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  819. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  820. 0, 0x1f, 0, digital_capture_tlv),
  821. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  822. 0, 3, 5, 0, input_gain_tlv),
  823. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  824. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  825. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  826. };
  827. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  828. /* Left channel inputs */
  829. SND_SOC_DAPM_INPUT("MAINMIC"),
  830. SND_SOC_DAPM_INPUT("HSMIC"),
  831. SND_SOC_DAPM_INPUT("AUXL"),
  832. SND_SOC_DAPM_INPUT("CARKITMIC"),
  833. /* Right channel inputs */
  834. SND_SOC_DAPM_INPUT("SUBMIC"),
  835. SND_SOC_DAPM_INPUT("AUXR"),
  836. /* Digital microphones (Stereo) */
  837. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  838. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  839. /* Outputs */
  840. SND_SOC_DAPM_OUTPUT("OUTL"),
  841. SND_SOC_DAPM_OUTPUT("OUTR"),
  842. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  843. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  844. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  845. SND_SOC_DAPM_OUTPUT("HSOL"),
  846. SND_SOC_DAPM_OUTPUT("HSOR"),
  847. SND_SOC_DAPM_OUTPUT("CARKITL"),
  848. SND_SOC_DAPM_OUTPUT("CARKITR"),
  849. SND_SOC_DAPM_OUTPUT("HFL"),
  850. SND_SOC_DAPM_OUTPUT("HFR"),
  851. SND_SOC_DAPM_OUTPUT("VIBRA"),
  852. /* DACs */
  853. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  854. SND_SOC_NOPM, 0, 0),
  855. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  856. SND_SOC_NOPM, 0, 0),
  857. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  858. SND_SOC_NOPM, 0, 0),
  859. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  860. SND_SOC_NOPM, 0, 0),
  861. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  862. SND_SOC_NOPM, 0, 0),
  863. /* Analog PGAs */
  864. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  865. 0, 0, NULL, 0),
  866. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  867. 0, 0, NULL, 0),
  868. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  869. 0, 0, NULL, 0),
  870. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  871. 0, 0, NULL, 0),
  872. SND_SOC_DAPM_PGA("VDL_APGA", TWL4030_REG_VDL_APGA_CTL,
  873. 0, 0, NULL, 0),
  874. /* Analog bypasses */
  875. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  876. &twl4030_dapm_abypassr1_control, bypass_event,
  877. SND_SOC_DAPM_POST_REG),
  878. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  879. &twl4030_dapm_abypassl1_control,
  880. bypass_event, SND_SOC_DAPM_POST_REG),
  881. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  882. &twl4030_dapm_abypassr2_control,
  883. bypass_event, SND_SOC_DAPM_POST_REG),
  884. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  885. &twl4030_dapm_abypassl2_control,
  886. bypass_event, SND_SOC_DAPM_POST_REG),
  887. SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  888. &twl4030_dapm_abypassv_control,
  889. bypass_event, SND_SOC_DAPM_POST_REG),
  890. /* Digital bypasses */
  891. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  892. &twl4030_dapm_dbypassl_control, bypass_event,
  893. SND_SOC_DAPM_POST_REG),
  894. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  895. &twl4030_dapm_dbypassr_control, bypass_event,
  896. SND_SOC_DAPM_POST_REG),
  897. SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  898. &twl4030_dapm_dbypassv_control, bypass_event,
  899. SND_SOC_DAPM_POST_REG),
  900. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  901. 0, 0, NULL, 0),
  902. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  903. 1, 0, NULL, 0),
  904. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  905. 2, 0, NULL, 0),
  906. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  907. 3, 0, NULL, 0),
  908. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", TWL4030_REG_AVDAC_CTL,
  909. 4, 0, NULL, 0),
  910. /* Output MIXER controls */
  911. /* Earpiece */
  912. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  913. &twl4030_dapm_earpiece_controls[0],
  914. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  915. /* PreDrivL/R */
  916. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  917. &twl4030_dapm_predrivel_controls[0],
  918. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  919. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  920. &twl4030_dapm_predriver_controls[0],
  921. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  922. /* HeadsetL/R */
  923. SND_SOC_DAPM_MIXER_E("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  924. &twl4030_dapm_hsol_controls[0],
  925. ARRAY_SIZE(twl4030_dapm_hsol_controls), headsetl_event,
  926. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  927. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  928. &twl4030_dapm_hsor_controls[0],
  929. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  930. /* CarkitL/R */
  931. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  932. &twl4030_dapm_carkitl_controls[0],
  933. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  934. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  935. &twl4030_dapm_carkitr_controls[0],
  936. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  937. /* Output MUX controls */
  938. /* HandsfreeL/R */
  939. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  940. &twl4030_dapm_handsfreel_control, handsfree_event,
  941. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  942. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  943. &twl4030_dapm_handsfreer_control, handsfree_event,
  944. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  945. /* Vibra */
  946. SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  947. &twl4030_dapm_vibra_control),
  948. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  949. &twl4030_dapm_vibrapath_control),
  950. /* Introducing four virtual ADC, since TWL4030 have four channel for
  951. capture */
  952. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  953. SND_SOC_NOPM, 0, 0),
  954. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  955. SND_SOC_NOPM, 0, 0),
  956. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  957. SND_SOC_NOPM, 0, 0),
  958. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  959. SND_SOC_NOPM, 0, 0),
  960. /* Analog/Digital mic path selection.
  961. TX1 Left/Right: either analog Left/Right or Digimic0
  962. TX2 Left/Right: either analog Left/Right or Digimic1 */
  963. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  964. &twl4030_dapm_micpathtx1_control, micpath_event,
  965. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  966. SND_SOC_DAPM_POST_REG),
  967. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  968. &twl4030_dapm_micpathtx2_control, micpath_event,
  969. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  970. SND_SOC_DAPM_POST_REG),
  971. /* Analog input mixers for the capture amplifiers */
  972. SND_SOC_DAPM_MIXER("Analog Left Capture Route",
  973. TWL4030_REG_ANAMICL, 4, 0,
  974. &twl4030_dapm_analoglmic_controls[0],
  975. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  976. SND_SOC_DAPM_MIXER("Analog Right Capture Route",
  977. TWL4030_REG_ANAMICR, 4, 0,
  978. &twl4030_dapm_analogrmic_controls[0],
  979. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  980. SND_SOC_DAPM_PGA("ADC Physical Left",
  981. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  982. SND_SOC_DAPM_PGA("ADC Physical Right",
  983. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  984. SND_SOC_DAPM_PGA("Digimic0 Enable",
  985. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  986. SND_SOC_DAPM_PGA("Digimic1 Enable",
  987. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  988. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  989. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  990. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  991. };
  992. static const struct snd_soc_dapm_route intercon[] = {
  993. {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
  994. {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
  995. {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
  996. {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
  997. {"Analog Voice Playback Mixer", NULL, "DAC Voice"},
  998. {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
  999. {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
  1000. {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
  1001. {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
  1002. {"VDL_APGA", NULL, "Analog Voice Playback Mixer"},
  1003. /* Internal playback routings */
  1004. /* Earpiece */
  1005. {"Earpiece Mixer", "Voice", "VDL_APGA"},
  1006. {"Earpiece Mixer", "AudioL1", "ARXL1_APGA"},
  1007. {"Earpiece Mixer", "AudioL2", "ARXL2_APGA"},
  1008. {"Earpiece Mixer", "AudioR1", "ARXR1_APGA"},
  1009. /* PreDrivL */
  1010. {"PredriveL Mixer", "Voice", "VDL_APGA"},
  1011. {"PredriveL Mixer", "AudioL1", "ARXL1_APGA"},
  1012. {"PredriveL Mixer", "AudioL2", "ARXL2_APGA"},
  1013. {"PredriveL Mixer", "AudioR2", "ARXR2_APGA"},
  1014. /* PreDrivR */
  1015. {"PredriveR Mixer", "Voice", "VDL_APGA"},
  1016. {"PredriveR Mixer", "AudioR1", "ARXR1_APGA"},
  1017. {"PredriveR Mixer", "AudioR2", "ARXR2_APGA"},
  1018. {"PredriveR Mixer", "AudioL2", "ARXL2_APGA"},
  1019. /* HeadsetL */
  1020. {"HeadsetL Mixer", "Voice", "VDL_APGA"},
  1021. {"HeadsetL Mixer", "AudioL1", "ARXL1_APGA"},
  1022. {"HeadsetL Mixer", "AudioL2", "ARXL2_APGA"},
  1023. /* HeadsetR */
  1024. {"HeadsetR Mixer", "Voice", "VDL_APGA"},
  1025. {"HeadsetR Mixer", "AudioR1", "ARXR1_APGA"},
  1026. {"HeadsetR Mixer", "AudioR2", "ARXR2_APGA"},
  1027. /* CarkitL */
  1028. {"CarkitL Mixer", "Voice", "VDL_APGA"},
  1029. {"CarkitL Mixer", "AudioL1", "ARXL1_APGA"},
  1030. {"CarkitL Mixer", "AudioL2", "ARXL2_APGA"},
  1031. /* CarkitR */
  1032. {"CarkitR Mixer", "Voice", "VDL_APGA"},
  1033. {"CarkitR Mixer", "AudioR1", "ARXR1_APGA"},
  1034. {"CarkitR Mixer", "AudioR2", "ARXR2_APGA"},
  1035. /* HandsfreeL */
  1036. {"HandsfreeL Mux", "Voice", "VDL_APGA"},
  1037. {"HandsfreeL Mux", "AudioL1", "ARXL1_APGA"},
  1038. {"HandsfreeL Mux", "AudioL2", "ARXL2_APGA"},
  1039. {"HandsfreeL Mux", "AudioR2", "ARXR2_APGA"},
  1040. /* HandsfreeR */
  1041. {"HandsfreeR Mux", "Voice", "VDL_APGA"},
  1042. {"HandsfreeR Mux", "AudioR1", "ARXR1_APGA"},
  1043. {"HandsfreeR Mux", "AudioR2", "ARXR2_APGA"},
  1044. {"HandsfreeR Mux", "AudioL2", "ARXL2_APGA"},
  1045. /* Vibra */
  1046. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1047. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1048. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1049. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1050. /* outputs */
  1051. {"OUTL", NULL, "ARXL2_APGA"},
  1052. {"OUTR", NULL, "ARXR2_APGA"},
  1053. {"EARPIECE", NULL, "Earpiece Mixer"},
  1054. {"PREDRIVEL", NULL, "PredriveL Mixer"},
  1055. {"PREDRIVER", NULL, "PredriveR Mixer"},
  1056. {"HSOL", NULL, "HeadsetL Mixer"},
  1057. {"HSOR", NULL, "HeadsetR Mixer"},
  1058. {"CARKITL", NULL, "CarkitL Mixer"},
  1059. {"CARKITR", NULL, "CarkitR Mixer"},
  1060. {"HFL", NULL, "HandsfreeL Mux"},
  1061. {"HFR", NULL, "HandsfreeR Mux"},
  1062. {"Vibra Route", "Audio", "Vibra Mux"},
  1063. {"VIBRA", NULL, "Vibra Route"},
  1064. /* Capture path */
  1065. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  1066. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  1067. {"Analog Left Capture Route", "AUXL", "AUXL"},
  1068. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  1069. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  1070. {"Analog Right Capture Route", "AUXR", "AUXR"},
  1071. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  1072. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  1073. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1074. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1075. /* TX1 Left capture path */
  1076. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1077. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1078. /* TX1 Right capture path */
  1079. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1080. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1081. /* TX2 Left capture path */
  1082. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1083. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1084. /* TX2 Right capture path */
  1085. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1086. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1087. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1088. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1089. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1090. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1091. /* Analog bypass routes */
  1092. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1093. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1094. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1095. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1096. {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
  1097. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1098. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1099. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1100. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1101. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1102. /* Digital bypass routes */
  1103. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1104. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1105. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1106. {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1107. {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1108. {"Analog Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1109. };
  1110. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1111. {
  1112. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1113. ARRAY_SIZE(twl4030_dapm_widgets));
  1114. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1115. snd_soc_dapm_new_widgets(codec);
  1116. return 0;
  1117. }
  1118. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1119. enum snd_soc_bias_level level)
  1120. {
  1121. struct twl4030_priv *twl4030 = codec->private_data;
  1122. switch (level) {
  1123. case SND_SOC_BIAS_ON:
  1124. twl4030_codec_mute(codec, 0);
  1125. break;
  1126. case SND_SOC_BIAS_PREPARE:
  1127. twl4030_power_up(codec);
  1128. if (twl4030->bypass_state)
  1129. twl4030_codec_mute(codec, 0);
  1130. else
  1131. twl4030_codec_mute(codec, 1);
  1132. break;
  1133. case SND_SOC_BIAS_STANDBY:
  1134. twl4030_power_up(codec);
  1135. if (twl4030->bypass_state)
  1136. twl4030_codec_mute(codec, 0);
  1137. else
  1138. twl4030_codec_mute(codec, 1);
  1139. break;
  1140. case SND_SOC_BIAS_OFF:
  1141. twl4030_power_down(codec);
  1142. break;
  1143. }
  1144. codec->bias_level = level;
  1145. return 0;
  1146. }
  1147. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1148. struct snd_pcm_substream *mst_substream)
  1149. {
  1150. struct snd_pcm_substream *slv_substream;
  1151. /* Pick the stream, which need to be constrained */
  1152. if (mst_substream == twl4030->master_substream)
  1153. slv_substream = twl4030->slave_substream;
  1154. else if (mst_substream == twl4030->slave_substream)
  1155. slv_substream = twl4030->master_substream;
  1156. else /* This should not happen.. */
  1157. return;
  1158. /* Set the constraints according to the already configured stream */
  1159. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1160. SNDRV_PCM_HW_PARAM_RATE,
  1161. twl4030->rate,
  1162. twl4030->rate);
  1163. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1164. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1165. twl4030->sample_bits,
  1166. twl4030->sample_bits);
  1167. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1168. SNDRV_PCM_HW_PARAM_CHANNELS,
  1169. twl4030->channels,
  1170. twl4030->channels);
  1171. }
  1172. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1173. * capture has to be enabled/disabled. */
  1174. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1175. int enable)
  1176. {
  1177. u8 reg, mask;
  1178. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1179. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1180. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1181. else
  1182. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1183. if (enable)
  1184. reg |= mask;
  1185. else
  1186. reg &= ~mask;
  1187. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1188. }
  1189. static int twl4030_startup(struct snd_pcm_substream *substream,
  1190. struct snd_soc_dai *dai)
  1191. {
  1192. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1193. struct snd_soc_device *socdev = rtd->socdev;
  1194. struct snd_soc_codec *codec = socdev->card->codec;
  1195. struct twl4030_priv *twl4030 = codec->private_data;
  1196. if (twl4030->master_substream) {
  1197. twl4030->slave_substream = substream;
  1198. /* The DAI has one configuration for playback and capture, so
  1199. * if the DAI has been already configured then constrain this
  1200. * substream to match it. */
  1201. if (twl4030->configured)
  1202. twl4030_constraints(twl4030, twl4030->master_substream);
  1203. } else {
  1204. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1205. TWL4030_OPTION_1)) {
  1206. /* In option2 4 channel is not supported, set the
  1207. * constraint for the first stream for channels, the
  1208. * second stream will 'inherit' this cosntraint */
  1209. snd_pcm_hw_constraint_minmax(substream->runtime,
  1210. SNDRV_PCM_HW_PARAM_CHANNELS,
  1211. 2, 2);
  1212. }
  1213. twl4030->master_substream = substream;
  1214. }
  1215. return 0;
  1216. }
  1217. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1218. struct snd_soc_dai *dai)
  1219. {
  1220. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1221. struct snd_soc_device *socdev = rtd->socdev;
  1222. struct snd_soc_codec *codec = socdev->card->codec;
  1223. struct twl4030_priv *twl4030 = codec->private_data;
  1224. if (twl4030->master_substream == substream)
  1225. twl4030->master_substream = twl4030->slave_substream;
  1226. twl4030->slave_substream = NULL;
  1227. /* If all streams are closed, or the remaining stream has not yet
  1228. * been configured than set the DAI as not configured. */
  1229. if (!twl4030->master_substream)
  1230. twl4030->configured = 0;
  1231. else if (!twl4030->master_substream->runtime->channels)
  1232. twl4030->configured = 0;
  1233. /* If the closing substream had 4 channel, do the necessary cleanup */
  1234. if (substream->runtime->channels == 4)
  1235. twl4030_tdm_enable(codec, substream->stream, 0);
  1236. }
  1237. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1238. struct snd_pcm_hw_params *params,
  1239. struct snd_soc_dai *dai)
  1240. {
  1241. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1242. struct snd_soc_device *socdev = rtd->socdev;
  1243. struct snd_soc_codec *codec = socdev->card->codec;
  1244. struct twl4030_priv *twl4030 = codec->private_data;
  1245. u8 mode, old_mode, format, old_format;
  1246. /* If the substream has 4 channel, do the necessary setup */
  1247. if (params_channels(params) == 4) {
  1248. /* Safety check: are we in the correct operating mode? */
  1249. if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1250. TWL4030_OPTION_1))
  1251. twl4030_tdm_enable(codec, substream->stream, 1);
  1252. else
  1253. return -EINVAL;
  1254. }
  1255. if (twl4030->configured)
  1256. /* Ignoring hw_params for already configured DAI */
  1257. return 0;
  1258. /* bit rate */
  1259. old_mode = twl4030_read_reg_cache(codec,
  1260. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1261. mode = old_mode & ~TWL4030_APLL_RATE;
  1262. switch (params_rate(params)) {
  1263. case 8000:
  1264. mode |= TWL4030_APLL_RATE_8000;
  1265. break;
  1266. case 11025:
  1267. mode |= TWL4030_APLL_RATE_11025;
  1268. break;
  1269. case 12000:
  1270. mode |= TWL4030_APLL_RATE_12000;
  1271. break;
  1272. case 16000:
  1273. mode |= TWL4030_APLL_RATE_16000;
  1274. break;
  1275. case 22050:
  1276. mode |= TWL4030_APLL_RATE_22050;
  1277. break;
  1278. case 24000:
  1279. mode |= TWL4030_APLL_RATE_24000;
  1280. break;
  1281. case 32000:
  1282. mode |= TWL4030_APLL_RATE_32000;
  1283. break;
  1284. case 44100:
  1285. mode |= TWL4030_APLL_RATE_44100;
  1286. break;
  1287. case 48000:
  1288. mode |= TWL4030_APLL_RATE_48000;
  1289. break;
  1290. case 96000:
  1291. mode |= TWL4030_APLL_RATE_96000;
  1292. break;
  1293. default:
  1294. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1295. params_rate(params));
  1296. return -EINVAL;
  1297. }
  1298. if (mode != old_mode) {
  1299. /* change rate and set CODECPDZ */
  1300. twl4030_codec_enable(codec, 0);
  1301. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1302. twl4030_codec_enable(codec, 1);
  1303. }
  1304. /* sample size */
  1305. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1306. format = old_format;
  1307. format &= ~TWL4030_DATA_WIDTH;
  1308. switch (params_format(params)) {
  1309. case SNDRV_PCM_FORMAT_S16_LE:
  1310. format |= TWL4030_DATA_WIDTH_16S_16W;
  1311. break;
  1312. case SNDRV_PCM_FORMAT_S24_LE:
  1313. format |= TWL4030_DATA_WIDTH_32S_24W;
  1314. break;
  1315. default:
  1316. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1317. params_format(params));
  1318. return -EINVAL;
  1319. }
  1320. if (format != old_format) {
  1321. /* clear CODECPDZ before changing format (codec requirement) */
  1322. twl4030_codec_enable(codec, 0);
  1323. /* change format */
  1324. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1325. /* set CODECPDZ afterwards */
  1326. twl4030_codec_enable(codec, 1);
  1327. }
  1328. /* Store the important parameters for the DAI configuration and set
  1329. * the DAI as configured */
  1330. twl4030->configured = 1;
  1331. twl4030->rate = params_rate(params);
  1332. twl4030->sample_bits = hw_param_interval(params,
  1333. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1334. twl4030->channels = params_channels(params);
  1335. /* If both playback and capture streams are open, and one of them
  1336. * is setting the hw parameters right now (since we are here), set
  1337. * constraints to the other stream to match the current one. */
  1338. if (twl4030->slave_substream)
  1339. twl4030_constraints(twl4030, substream);
  1340. return 0;
  1341. }
  1342. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1343. int clk_id, unsigned int freq, int dir)
  1344. {
  1345. struct snd_soc_codec *codec = codec_dai->codec;
  1346. u8 infreq;
  1347. switch (freq) {
  1348. case 19200000:
  1349. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1350. break;
  1351. case 26000000:
  1352. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1353. break;
  1354. case 38400000:
  1355. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1356. break;
  1357. default:
  1358. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1359. freq);
  1360. return -EINVAL;
  1361. }
  1362. infreq |= TWL4030_APLL_EN;
  1363. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1364. return 0;
  1365. }
  1366. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1367. unsigned int fmt)
  1368. {
  1369. struct snd_soc_codec *codec = codec_dai->codec;
  1370. u8 old_format, format;
  1371. /* get format */
  1372. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1373. format = old_format;
  1374. /* set master/slave audio interface */
  1375. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1376. case SND_SOC_DAIFMT_CBM_CFM:
  1377. format &= ~(TWL4030_AIF_SLAVE_EN);
  1378. format &= ~(TWL4030_CLK256FS_EN);
  1379. break;
  1380. case SND_SOC_DAIFMT_CBS_CFS:
  1381. format |= TWL4030_AIF_SLAVE_EN;
  1382. format |= TWL4030_CLK256FS_EN;
  1383. break;
  1384. default:
  1385. return -EINVAL;
  1386. }
  1387. /* interface format */
  1388. format &= ~TWL4030_AIF_FORMAT;
  1389. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1390. case SND_SOC_DAIFMT_I2S:
  1391. format |= TWL4030_AIF_FORMAT_CODEC;
  1392. break;
  1393. case SND_SOC_DAIFMT_DSP_A:
  1394. format |= TWL4030_AIF_FORMAT_TDM;
  1395. break;
  1396. default:
  1397. return -EINVAL;
  1398. }
  1399. if (format != old_format) {
  1400. /* clear CODECPDZ before changing format (codec requirement) */
  1401. twl4030_codec_enable(codec, 0);
  1402. /* change format */
  1403. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1404. /* set CODECPDZ afterwards */
  1405. twl4030_codec_enable(codec, 1);
  1406. }
  1407. return 0;
  1408. }
  1409. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1410. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1411. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1412. int enable)
  1413. {
  1414. u8 reg, mask;
  1415. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1416. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1417. mask = TWL4030_ARXL1_VRX_EN;
  1418. else
  1419. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1420. if (enable)
  1421. reg |= mask;
  1422. else
  1423. reg &= ~mask;
  1424. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1425. }
  1426. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1427. struct snd_soc_dai *dai)
  1428. {
  1429. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1430. struct snd_soc_device *socdev = rtd->socdev;
  1431. struct snd_soc_codec *codec = socdev->card->codec;
  1432. u8 infreq;
  1433. u8 mode;
  1434. /* If the system master clock is not 26MHz, the voice PCM interface is
  1435. * not avilable.
  1436. */
  1437. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1438. & TWL4030_APLL_INFREQ;
  1439. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1440. printk(KERN_ERR "TWL4030 voice startup: "
  1441. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1442. return -EINVAL;
  1443. }
  1444. /* If the codec mode is not option2, the voice PCM interface is not
  1445. * avilable.
  1446. */
  1447. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1448. & TWL4030_OPT_MODE;
  1449. if (mode != TWL4030_OPTION_2) {
  1450. printk(KERN_ERR "TWL4030 voice startup: "
  1451. "the codec mode is not option2\n");
  1452. return -EINVAL;
  1453. }
  1454. return 0;
  1455. }
  1456. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1457. struct snd_soc_dai *dai)
  1458. {
  1459. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1460. struct snd_soc_device *socdev = rtd->socdev;
  1461. struct snd_soc_codec *codec = socdev->card->codec;
  1462. /* Enable voice digital filters */
  1463. twl4030_voice_enable(codec, substream->stream, 0);
  1464. }
  1465. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1466. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1467. {
  1468. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1469. struct snd_soc_device *socdev = rtd->socdev;
  1470. struct snd_soc_codec *codec = socdev->card->codec;
  1471. u8 old_mode, mode;
  1472. /* Enable voice digital filters */
  1473. twl4030_voice_enable(codec, substream->stream, 1);
  1474. /* bit rate */
  1475. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1476. & ~(TWL4030_CODECPDZ);
  1477. mode = old_mode;
  1478. switch (params_rate(params)) {
  1479. case 8000:
  1480. mode &= ~(TWL4030_SEL_16K);
  1481. break;
  1482. case 16000:
  1483. mode |= TWL4030_SEL_16K;
  1484. break;
  1485. default:
  1486. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1487. params_rate(params));
  1488. return -EINVAL;
  1489. }
  1490. if (mode != old_mode) {
  1491. /* change rate and set CODECPDZ */
  1492. twl4030_codec_enable(codec, 0);
  1493. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1494. twl4030_codec_enable(codec, 1);
  1495. }
  1496. return 0;
  1497. }
  1498. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1499. int clk_id, unsigned int freq, int dir)
  1500. {
  1501. struct snd_soc_codec *codec = codec_dai->codec;
  1502. u8 infreq;
  1503. switch (freq) {
  1504. case 26000000:
  1505. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1506. break;
  1507. default:
  1508. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1509. freq);
  1510. return -EINVAL;
  1511. }
  1512. infreq |= TWL4030_APLL_EN;
  1513. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1514. return 0;
  1515. }
  1516. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1517. unsigned int fmt)
  1518. {
  1519. struct snd_soc_codec *codec = codec_dai->codec;
  1520. u8 old_format, format;
  1521. /* get format */
  1522. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1523. format = old_format;
  1524. /* set master/slave audio interface */
  1525. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1526. case SND_SOC_DAIFMT_CBS_CFM:
  1527. format &= ~(TWL4030_VIF_SLAVE_EN);
  1528. break;
  1529. case SND_SOC_DAIFMT_CBS_CFS:
  1530. format |= TWL4030_VIF_SLAVE_EN;
  1531. break;
  1532. default:
  1533. return -EINVAL;
  1534. }
  1535. /* clock inversion */
  1536. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1537. case SND_SOC_DAIFMT_IB_NF:
  1538. format &= ~(TWL4030_VIF_FORMAT);
  1539. break;
  1540. case SND_SOC_DAIFMT_NB_IF:
  1541. format |= TWL4030_VIF_FORMAT;
  1542. break;
  1543. default:
  1544. return -EINVAL;
  1545. }
  1546. if (format != old_format) {
  1547. /* change format and set CODECPDZ */
  1548. twl4030_codec_enable(codec, 0);
  1549. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1550. twl4030_codec_enable(codec, 1);
  1551. }
  1552. return 0;
  1553. }
  1554. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1555. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1556. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1557. .startup = twl4030_startup,
  1558. .shutdown = twl4030_shutdown,
  1559. .hw_params = twl4030_hw_params,
  1560. .set_sysclk = twl4030_set_dai_sysclk,
  1561. .set_fmt = twl4030_set_dai_fmt,
  1562. };
  1563. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1564. .startup = twl4030_voice_startup,
  1565. .shutdown = twl4030_voice_shutdown,
  1566. .hw_params = twl4030_voice_hw_params,
  1567. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1568. .set_fmt = twl4030_voice_set_dai_fmt,
  1569. };
  1570. struct snd_soc_dai twl4030_dai[] = {
  1571. {
  1572. .name = "twl4030",
  1573. .playback = {
  1574. .stream_name = "Playback",
  1575. .channels_min = 2,
  1576. .channels_max = 4,
  1577. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1578. .formats = TWL4030_FORMATS,},
  1579. .capture = {
  1580. .stream_name = "Capture",
  1581. .channels_min = 2,
  1582. .channels_max = 4,
  1583. .rates = TWL4030_RATES,
  1584. .formats = TWL4030_FORMATS,},
  1585. .ops = &twl4030_dai_ops,
  1586. },
  1587. {
  1588. .name = "twl4030 Voice",
  1589. .playback = {
  1590. .stream_name = "Playback",
  1591. .channels_min = 1,
  1592. .channels_max = 1,
  1593. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1594. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1595. .capture = {
  1596. .stream_name = "Capture",
  1597. .channels_min = 1,
  1598. .channels_max = 2,
  1599. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1600. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1601. .ops = &twl4030_dai_voice_ops,
  1602. },
  1603. };
  1604. EXPORT_SYMBOL_GPL(twl4030_dai);
  1605. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1606. {
  1607. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1608. struct snd_soc_codec *codec = socdev->card->codec;
  1609. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1610. return 0;
  1611. }
  1612. static int twl4030_resume(struct platform_device *pdev)
  1613. {
  1614. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1615. struct snd_soc_codec *codec = socdev->card->codec;
  1616. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1617. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1618. return 0;
  1619. }
  1620. /*
  1621. * initialize the driver
  1622. * register the mixer and dsp interfaces with the kernel
  1623. */
  1624. static int twl4030_init(struct snd_soc_device *socdev)
  1625. {
  1626. struct snd_soc_codec *codec = socdev->card->codec;
  1627. int ret = 0;
  1628. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1629. codec->name = "twl4030";
  1630. codec->owner = THIS_MODULE;
  1631. codec->read = twl4030_read_reg_cache;
  1632. codec->write = twl4030_write;
  1633. codec->set_bias_level = twl4030_set_bias_level;
  1634. codec->dai = twl4030_dai;
  1635. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1636. codec->reg_cache_size = sizeof(twl4030_reg);
  1637. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1638. GFP_KERNEL);
  1639. if (codec->reg_cache == NULL)
  1640. return -ENOMEM;
  1641. /* register pcms */
  1642. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1643. if (ret < 0) {
  1644. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1645. goto pcm_err;
  1646. }
  1647. twl4030_init_chip(codec);
  1648. /* power on device */
  1649. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1650. snd_soc_add_controls(codec, twl4030_snd_controls,
  1651. ARRAY_SIZE(twl4030_snd_controls));
  1652. twl4030_add_widgets(codec);
  1653. ret = snd_soc_init_card(socdev);
  1654. if (ret < 0) {
  1655. printk(KERN_ERR "twl4030: failed to register card\n");
  1656. goto card_err;
  1657. }
  1658. return ret;
  1659. card_err:
  1660. snd_soc_free_pcms(socdev);
  1661. snd_soc_dapm_free(socdev);
  1662. pcm_err:
  1663. kfree(codec->reg_cache);
  1664. return ret;
  1665. }
  1666. static struct snd_soc_device *twl4030_socdev;
  1667. static int twl4030_probe(struct platform_device *pdev)
  1668. {
  1669. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1670. struct snd_soc_codec *codec;
  1671. struct twl4030_priv *twl4030;
  1672. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1673. if (codec == NULL)
  1674. return -ENOMEM;
  1675. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1676. if (twl4030 == NULL) {
  1677. kfree(codec);
  1678. return -ENOMEM;
  1679. }
  1680. codec->private_data = twl4030;
  1681. socdev->card->codec = codec;
  1682. mutex_init(&codec->mutex);
  1683. INIT_LIST_HEAD(&codec->dapm_widgets);
  1684. INIT_LIST_HEAD(&codec->dapm_paths);
  1685. twl4030_socdev = socdev;
  1686. twl4030_init(socdev);
  1687. return 0;
  1688. }
  1689. static int twl4030_remove(struct platform_device *pdev)
  1690. {
  1691. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1692. struct snd_soc_codec *codec = socdev->card->codec;
  1693. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1694. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1695. snd_soc_free_pcms(socdev);
  1696. snd_soc_dapm_free(socdev);
  1697. kfree(codec->private_data);
  1698. kfree(codec);
  1699. return 0;
  1700. }
  1701. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1702. .probe = twl4030_probe,
  1703. .remove = twl4030_remove,
  1704. .suspend = twl4030_suspend,
  1705. .resume = twl4030_resume,
  1706. };
  1707. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1708. static int __init twl4030_modinit(void)
  1709. {
  1710. return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1711. }
  1712. module_init(twl4030_modinit);
  1713. static void __exit twl4030_exit(void)
  1714. {
  1715. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1716. }
  1717. module_exit(twl4030_exit);
  1718. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1719. MODULE_AUTHOR("Steve Sakoman");
  1720. MODULE_LICENSE("GPL");