at91sam9x5.dtsi 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490
  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9x5 family SoC";
  14. compatible = "atmel,at91sam9x5";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. tcb0 = &tcb0;
  26. tcb1 = &tcb1;
  27. i2c0 = &i2c0;
  28. i2c1 = &i2c1;
  29. i2c2 = &i2c2;
  30. };
  31. cpus {
  32. cpu@0 {
  33. compatible = "arm,arm926ejs";
  34. };
  35. };
  36. memory {
  37. reg = <0x20000000 0x10000000>;
  38. };
  39. ahb {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges;
  44. apb {
  45. compatible = "simple-bus";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. ranges;
  49. aic: interrupt-controller@fffff000 {
  50. #interrupt-cells = <3>;
  51. compatible = "atmel,at91rm9200-aic";
  52. interrupt-controller;
  53. reg = <0xfffff000 0x200>;
  54. atmel,external-irqs = <31>;
  55. };
  56. ramc0: ramc@ffffe800 {
  57. compatible = "atmel,at91sam9g45-ddramc";
  58. reg = <0xffffe800 0x200>;
  59. };
  60. pmc: pmc@fffffc00 {
  61. compatible = "atmel,at91rm9200-pmc";
  62. reg = <0xfffffc00 0x100>;
  63. };
  64. rstc@fffffe00 {
  65. compatible = "atmel,at91sam9g45-rstc";
  66. reg = <0xfffffe00 0x10>;
  67. };
  68. shdwc@fffffe10 {
  69. compatible = "atmel,at91sam9x5-shdwc";
  70. reg = <0xfffffe10 0x10>;
  71. };
  72. pit: timer@fffffe30 {
  73. compatible = "atmel,at91sam9260-pit";
  74. reg = <0xfffffe30 0xf>;
  75. interrupts = <1 4 7>;
  76. };
  77. tcb0: timer@f8008000 {
  78. compatible = "atmel,at91sam9x5-tcb";
  79. reg = <0xf8008000 0x100>;
  80. interrupts = <17 4 0>;
  81. };
  82. tcb1: timer@f800c000 {
  83. compatible = "atmel,at91sam9x5-tcb";
  84. reg = <0xf800c000 0x100>;
  85. interrupts = <17 4 0>;
  86. };
  87. dma0: dma-controller@ffffec00 {
  88. compatible = "atmel,at91sam9g45-dma";
  89. reg = <0xffffec00 0x200>;
  90. interrupts = <20 4 0>;
  91. };
  92. dma1: dma-controller@ffffee00 {
  93. compatible = "atmel,at91sam9g45-dma";
  94. reg = <0xffffee00 0x200>;
  95. interrupts = <21 4 0>;
  96. };
  97. pinctrl@fffff400 {
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  101. ranges = <0xfffff400 0xfffff400 0x800>;
  102. /* shared pinctrl settings */
  103. dbgu {
  104. pinctrl_dbgu: dbgu-0 {
  105. atmel,pins =
  106. <0 9 0x1 0x0 /* PA9 periph A */
  107. 0 10 0x1 0x1>; /* PA10 periph A with pullup */
  108. };
  109. };
  110. usart0 {
  111. pinctrl_usart0: usart0-0 {
  112. atmel,pins =
  113. <0 0 0x1 0x1 /* PA0 periph A with pullup */
  114. 0 1 0x1 0x0>; /* PA1 periph A */
  115. };
  116. pinctrl_usart0_rts: usart0_rts-0 {
  117. atmel,pins =
  118. <0 2 0x1 0x0>; /* PA2 periph A */
  119. };
  120. pinctrl_usart0_cts: usart0_cts-0 {
  121. atmel,pins =
  122. <0 3 0x1 0x0>; /* PA3 periph A */
  123. };
  124. };
  125. usart1 {
  126. pinctrl_usart1: usart1-0 {
  127. atmel,pins =
  128. <0 5 0x1 0x1 /* PA5 periph A with pullup */
  129. 0 6 0x1 0x0>; /* PA6 periph A */
  130. };
  131. pinctrl_usart1_rts: usart1_rts-0 {
  132. atmel,pins =
  133. <3 27 0x3 0x0>; /* PC27 periph C */
  134. };
  135. pinctrl_usart1_cts: usart1_cts-0 {
  136. atmel,pins =
  137. <3 28 0x3 0x0>; /* PC28 periph C */
  138. };
  139. };
  140. usart2 {
  141. pinctrl_usart2: usart2-0 {
  142. atmel,pins =
  143. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  144. 0 8 0x1 0x0>; /* PA8 periph A */
  145. };
  146. pinctrl_uart2_rts: uart2_rts-0 {
  147. atmel,pins =
  148. <0 0 0x2 0x0>; /* PB0 periph B */
  149. };
  150. pinctrl_uart2_cts: uart2_cts-0 {
  151. atmel,pins =
  152. <0 1 0x2 0x0>; /* PB1 periph B */
  153. };
  154. };
  155. usart3 {
  156. pinctrl_uart3: usart3-0 {
  157. atmel,pins =
  158. <3 23 0x2 0x1 /* PC22 periph B with pullup */
  159. 3 23 0x2 0x0>; /* PC23 periph B */
  160. };
  161. pinctrl_usart3_rts: usart3_rts-0 {
  162. atmel,pins =
  163. <3 24 0x2 0x0>; /* PC24 periph B */
  164. };
  165. pinctrl_usart3_cts: usart3_cts-0 {
  166. atmel,pins =
  167. <3 25 0x2 0x0>; /* PC25 periph B */
  168. };
  169. };
  170. uart0 {
  171. pinctrl_uart0: uart0-0 {
  172. atmel,pins =
  173. <3 8 0x3 0x0 /* PC8 periph C */
  174. 3 9 0x3 0x1>; /* PC9 periph C with pullup */
  175. };
  176. };
  177. uart1 {
  178. pinctrl_uart1: uart1-0 {
  179. atmel,pins =
  180. <3 16 0x3 0x0 /* PC16 periph C */
  181. 3 17 0x3 0x1>; /* PC17 periph C with pullup */
  182. };
  183. };
  184. nand {
  185. pinctrl_nand: nand-0 {
  186. atmel,pins =
  187. <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
  188. 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  189. };
  190. };
  191. macb0 {
  192. pinctrl_macb0_rmii: macb0_rmii-0 {
  193. atmel,pins =
  194. <1 0 0x1 0x0 /* PB0 periph A */
  195. 1 1 0x1 0x0 /* PB1 periph A */
  196. 1 2 0x1 0x0 /* PB2 periph A */
  197. 1 3 0x1 0x0 /* PB3 periph A */
  198. 1 4 0x1 0x0 /* PB4 periph A */
  199. 1 5 0x1 0x0 /* PB5 periph A */
  200. 1 6 0x1 0x0 /* PB6 periph A */
  201. 1 7 0x1 0x0 /* PB7 periph A */
  202. 1 9 0x1 0x0 /* PB9 periph A */
  203. 1 10 0x1 0x0>; /* PB10 periph A */
  204. };
  205. pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
  206. atmel,pins =
  207. <1 8 0x1 0x0 /* PA8 periph A */
  208. 1 11 0x1 0x0 /* PA11 periph A */
  209. 1 12 0x1 0x0 /* PA12 periph A */
  210. 1 13 0x1 0x0 /* PA13 periph A */
  211. 1 14 0x1 0x0 /* PA14 periph A */
  212. 1 15 0x1 0x0 /* PA15 periph A */
  213. 1 16 0x1 0x0 /* PA16 periph A */
  214. 1 17 0x1 0x0>; /* PA17 periph A */
  215. };
  216. };
  217. pioA: gpio@fffff400 {
  218. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  219. reg = <0xfffff400 0x200>;
  220. interrupts = <2 4 1>;
  221. #gpio-cells = <2>;
  222. gpio-controller;
  223. interrupt-controller;
  224. #interrupt-cells = <2>;
  225. };
  226. pioB: gpio@fffff600 {
  227. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  228. reg = <0xfffff600 0x200>;
  229. interrupts = <2 4 1>;
  230. #gpio-cells = <2>;
  231. gpio-controller;
  232. #gpio-lines = <19>;
  233. interrupt-controller;
  234. #interrupt-cells = <2>;
  235. };
  236. pioC: gpio@fffff800 {
  237. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  238. reg = <0xfffff800 0x200>;
  239. interrupts = <3 4 1>;
  240. #gpio-cells = <2>;
  241. gpio-controller;
  242. interrupt-controller;
  243. #interrupt-cells = <2>;
  244. };
  245. pioD: gpio@fffffa00 {
  246. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  247. reg = <0xfffffa00 0x200>;
  248. interrupts = <3 4 1>;
  249. #gpio-cells = <2>;
  250. gpio-controller;
  251. #gpio-lines = <22>;
  252. interrupt-controller;
  253. #interrupt-cells = <2>;
  254. };
  255. };
  256. dbgu: serial@fffff200 {
  257. compatible = "atmel,at91sam9260-usart";
  258. reg = <0xfffff200 0x200>;
  259. interrupts = <1 4 7>;
  260. pinctrl-names = "default";
  261. pinctrl-0 = <&pinctrl_dbgu>;
  262. status = "disabled";
  263. };
  264. usart0: serial@f801c000 {
  265. compatible = "atmel,at91sam9260-usart";
  266. reg = <0xf801c000 0x200>;
  267. interrupts = <5 4 5>;
  268. atmel,use-dma-rx;
  269. atmel,use-dma-tx;
  270. pinctrl-names = "default";
  271. pinctrl-0 = <&pinctrl_usart0>;
  272. status = "disabled";
  273. };
  274. usart1: serial@f8020000 {
  275. compatible = "atmel,at91sam9260-usart";
  276. reg = <0xf8020000 0x200>;
  277. interrupts = <6 4 5>;
  278. atmel,use-dma-rx;
  279. atmel,use-dma-tx;
  280. pinctrl-names = "default";
  281. pinctrl-0 = <&pinctrl_usart1>;
  282. status = "disabled";
  283. };
  284. usart2: serial@f8024000 {
  285. compatible = "atmel,at91sam9260-usart";
  286. reg = <0xf8024000 0x200>;
  287. interrupts = <7 4 5>;
  288. atmel,use-dma-rx;
  289. atmel,use-dma-tx;
  290. pinctrl-names = "default";
  291. pinctrl-0 = <&pinctrl_usart2>;
  292. status = "disabled";
  293. };
  294. macb0: ethernet@f802c000 {
  295. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  296. reg = <0xf802c000 0x100>;
  297. interrupts = <24 4 3>;
  298. pinctrl-names = "default";
  299. pinctrl-0 = <&pinctrl_macb0_rmii>;
  300. status = "disabled";
  301. };
  302. macb1: ethernet@f8030000 {
  303. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  304. reg = <0xf8030000 0x100>;
  305. interrupts = <27 4 3>;
  306. status = "disabled";
  307. };
  308. i2c0: i2c@f8010000 {
  309. compatible = "atmel,at91sam9x5-i2c";
  310. reg = <0xf8010000 0x100>;
  311. interrupts = <9 4 6>;
  312. #address-cells = <1>;
  313. #size-cells = <0>;
  314. status = "disabled";
  315. };
  316. i2c1: i2c@f8014000 {
  317. compatible = "atmel,at91sam9x5-i2c";
  318. reg = <0xf8014000 0x100>;
  319. interrupts = <10 4 6>;
  320. #address-cells = <1>;
  321. #size-cells = <0>;
  322. status = "disabled";
  323. };
  324. i2c2: i2c@f8018000 {
  325. compatible = "atmel,at91sam9x5-i2c";
  326. reg = <0xf8018000 0x100>;
  327. interrupts = <11 4 6>;
  328. #address-cells = <1>;
  329. #size-cells = <0>;
  330. status = "disabled";
  331. };
  332. adc0: adc@f804c000 {
  333. compatible = "atmel,at91sam9260-adc";
  334. reg = <0xf804c000 0x100>;
  335. interrupts = <19 4 0>;
  336. atmel,adc-use-external;
  337. atmel,adc-channels-used = <0xffff>;
  338. atmel,adc-vref = <3300>;
  339. atmel,adc-num-channels = <12>;
  340. atmel,adc-startup-time = <40>;
  341. atmel,adc-channel-base = <0x50>;
  342. atmel,adc-drdy-mask = <0x1000000>;
  343. atmel,adc-status-register = <0x30>;
  344. atmel,adc-trigger-register = <0xc0>;
  345. trigger@0 {
  346. trigger-name = "external-rising";
  347. trigger-value = <0x1>;
  348. trigger-external;
  349. };
  350. trigger@1 {
  351. trigger-name = "external-falling";
  352. trigger-value = <0x2>;
  353. trigger-external;
  354. };
  355. trigger@2 {
  356. trigger-name = "external-any";
  357. trigger-value = <0x3>;
  358. trigger-external;
  359. };
  360. trigger@3 {
  361. trigger-name = "continuous";
  362. trigger-value = <0x6>;
  363. };
  364. };
  365. };
  366. nand0: nand@40000000 {
  367. compatible = "atmel,at91rm9200-nand";
  368. #address-cells = <1>;
  369. #size-cells = <1>;
  370. reg = <0x40000000 0x10000000
  371. >;
  372. atmel,nand-addr-offset = <21>;
  373. atmel,nand-cmd-offset = <22>;
  374. pinctrl-names = "default";
  375. pinctrl-0 = <&pinctrl_nand>;
  376. gpios = <&pioD 5 0
  377. &pioD 4 0
  378. 0
  379. >;
  380. status = "disabled";
  381. };
  382. usb0: ohci@00600000 {
  383. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  384. reg = <0x00600000 0x100000>;
  385. interrupts = <22 4 2>;
  386. status = "disabled";
  387. };
  388. usb1: ehci@00700000 {
  389. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  390. reg = <0x00700000 0x100000>;
  391. interrupts = <22 4 2>;
  392. status = "disabled";
  393. };
  394. };
  395. i2c@0 {
  396. compatible = "i2c-gpio";
  397. gpios = <&pioA 30 0 /* sda */
  398. &pioA 31 0 /* scl */
  399. >;
  400. i2c-gpio,sda-open-drain;
  401. i2c-gpio,scl-open-drain;
  402. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  403. #address-cells = <1>;
  404. #size-cells = <0>;
  405. status = "disabled";
  406. };
  407. i2c@1 {
  408. compatible = "i2c-gpio";
  409. gpios = <&pioC 0 0 /* sda */
  410. &pioC 1 0 /* scl */
  411. >;
  412. i2c-gpio,sda-open-drain;
  413. i2c-gpio,scl-open-drain;
  414. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  415. #address-cells = <1>;
  416. #size-cells = <0>;
  417. status = "disabled";
  418. };
  419. i2c@2 {
  420. compatible = "i2c-gpio";
  421. gpios = <&pioB 4 0 /* sda */
  422. &pioB 5 0 /* scl */
  423. >;
  424. i2c-gpio,sda-open-drain;
  425. i2c-gpio,scl-open-drain;
  426. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  427. #address-cells = <1>;
  428. #size-cells = <0>;
  429. status = "disabled";
  430. };
  431. };