at91sam9g45.dtsi 10 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x70000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe400 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe400 0x200
  60. 0xffffe600 0x200>;
  61. };
  62. pmc: pmc@fffffc00 {
  63. compatible = "atmel,at91rm9200-pmc";
  64. reg = <0xfffffc00 0x100>;
  65. };
  66. rstc@fffffd00 {
  67. compatible = "atmel,at91sam9g45-rstc";
  68. reg = <0xfffffd00 0x10>;
  69. };
  70. pit: timer@fffffd30 {
  71. compatible = "atmel,at91sam9260-pit";
  72. reg = <0xfffffd30 0xf>;
  73. interrupts = <1 4 7>;
  74. };
  75. shdwc@fffffd10 {
  76. compatible = "atmel,at91sam9rl-shdwc";
  77. reg = <0xfffffd10 0x10>;
  78. };
  79. tcb0: timer@fff7c000 {
  80. compatible = "atmel,at91rm9200-tcb";
  81. reg = <0xfff7c000 0x100>;
  82. interrupts = <18 4 0>;
  83. };
  84. tcb1: timer@fffd4000 {
  85. compatible = "atmel,at91rm9200-tcb";
  86. reg = <0xfffd4000 0x100>;
  87. interrupts = <18 4 0>;
  88. };
  89. dma: dma-controller@ffffec00 {
  90. compatible = "atmel,at91sam9g45-dma";
  91. reg = <0xffffec00 0x200>;
  92. interrupts = <21 4 0>;
  93. };
  94. pinctrl@fffff200 {
  95. #address-cells = <1>;
  96. #size-cells = <1>;
  97. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  98. ranges = <0xfffff200 0xfffff200 0xa00>;
  99. atmel,mux-mask = <
  100. /* A B */
  101. 0xffffffff 0xffc003ff /* pioA */
  102. 0xffffffff 0x800f8f00 /* pioB */
  103. 0xffffffff 0x00000e00 /* pioC */
  104. 0xffffffff 0xff0c1381 /* pioD */
  105. 0xffffffff 0x81ffff81 /* pioE */
  106. >;
  107. /* shared pinctrl settings */
  108. dbgu {
  109. pinctrl_dbgu: dbgu-0 {
  110. atmel,pins =
  111. <1 12 0x1 0x0 /* PB12 periph A */
  112. 1 13 0x1 0x0>; /* PB13 periph A */
  113. };
  114. };
  115. usart0 {
  116. pinctrl_usart0: usart0-0 {
  117. atmel,pins =
  118. <1 19 0x1 0x1 /* PB19 periph A with pullup */
  119. 1 18 0x1 0x0>; /* PB18 periph A */
  120. };
  121. pinctrl_usart0_rts: usart0_rts-0 {
  122. atmel,pins =
  123. <1 17 0x2 0x0>; /* PB17 periph B */
  124. };
  125. pinctrl_usart0_cts: usart0_cts-0 {
  126. atmel,pins =
  127. <1 15 0x2 0x0>; /* PB15 periph B */
  128. };
  129. };
  130. uart1 {
  131. pinctrl_usart1: usart1-0 {
  132. atmel,pins =
  133. <1 4 0x1 0x1 /* PB4 periph A with pullup */
  134. 1 5 0x1 0x0>; /* PB5 periph A */
  135. };
  136. pinctrl_usart1_rts: usart1_rts-0 {
  137. atmel,pins =
  138. <3 16 0x1 0x0>; /* PD16 periph A */
  139. };
  140. pinctrl_usart1_cts: usart1_cts-0 {
  141. atmel,pins =
  142. <3 17 0x1 0x0>; /* PD17 periph A */
  143. };
  144. };
  145. usart2 {
  146. pinctrl_usart2: usart2-0 {
  147. atmel,pins =
  148. <1 6 0x1 0x1 /* PB6 periph A with pullup */
  149. 1 7 0x1 0x0>; /* PB7 periph A */
  150. };
  151. pinctrl_usart2_rts: usart2_rts-0 {
  152. atmel,pins =
  153. <2 9 0x2 0x0>; /* PC9 periph B */
  154. };
  155. pinctrl_usart2_cts: usart2_cts-0 {
  156. atmel,pins =
  157. <2 11 0x2 0x0>; /* PC11 periph B */
  158. };
  159. };
  160. usart3 {
  161. pinctrl_usart3: usart3-0 {
  162. atmel,pins =
  163. <1 8 0x1 0x1 /* PB9 periph A with pullup */
  164. 1 9 0x1 0x0>; /* PB8 periph A */
  165. };
  166. pinctrl_usart3_rts: usart3_rts-0 {
  167. atmel,pins =
  168. <0 23 0x2 0x0>; /* PA23 periph B */
  169. };
  170. pinctrl_usart3_cts: usart3_cts-0 {
  171. atmel,pins =
  172. <0 24 0x2 0x0>; /* PA24 periph B */
  173. };
  174. };
  175. nand {
  176. pinctrl_nand: nand-0 {
  177. atmel,pins =
  178. <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
  179. 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
  180. };
  181. };
  182. macb {
  183. pinctrl_macb_rmii: macb_rmii-0 {
  184. atmel,pins =
  185. <0 10 0x1 0x0 /* PA10 periph A */
  186. 0 11 0x1 0x0 /* PA11 periph A */
  187. 0 12 0x1 0x0 /* PA12 periph A */
  188. 0 13 0x1 0x0 /* PA13 periph A */
  189. 0 14 0x1 0x0 /* PA14 periph A */
  190. 0 15 0x1 0x0 /* PA15 periph A */
  191. 0 16 0x1 0x0 /* PA16 periph A */
  192. 0 17 0x1 0x0 /* PA17 periph A */
  193. 0 18 0x1 0x0 /* PA18 periph A */
  194. 0 19 0x1 0x0>; /* PA19 periph A */
  195. };
  196. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  197. atmel,pins =
  198. <0 6 0x2 0x0 /* PA6 periph B */
  199. 0 7 0x2 0x0 /* PA7 periph B */
  200. 0 8 0x2 0x0 /* PA8 periph B */
  201. 0 9 0x2 0x0 /* PA9 periph B */
  202. 0 27 0x2 0x0 /* PA27 periph B */
  203. 0 28 0x2 0x0 /* PA28 periph B */
  204. 0 29 0x2 0x0 /* PA29 periph B */
  205. 0 30 0x2 0x0>; /* PA30 periph B */
  206. };
  207. };
  208. pioA: gpio@fffff200 {
  209. compatible = "atmel,at91rm9200-gpio";
  210. reg = <0xfffff200 0x200>;
  211. interrupts = <2 4 1>;
  212. #gpio-cells = <2>;
  213. gpio-controller;
  214. interrupt-controller;
  215. #interrupt-cells = <2>;
  216. };
  217. pioB: gpio@fffff400 {
  218. compatible = "atmel,at91rm9200-gpio";
  219. reg = <0xfffff400 0x200>;
  220. interrupts = <3 4 1>;
  221. #gpio-cells = <2>;
  222. gpio-controller;
  223. interrupt-controller;
  224. #interrupt-cells = <2>;
  225. };
  226. pioC: gpio@fffff600 {
  227. compatible = "atmel,at91rm9200-gpio";
  228. reg = <0xfffff600 0x200>;
  229. interrupts = <4 4 1>;
  230. #gpio-cells = <2>;
  231. gpio-controller;
  232. interrupt-controller;
  233. #interrupt-cells = <2>;
  234. };
  235. pioD: gpio@fffff800 {
  236. compatible = "atmel,at91rm9200-gpio";
  237. reg = <0xfffff800 0x200>;
  238. interrupts = <5 4 1>;
  239. #gpio-cells = <2>;
  240. gpio-controller;
  241. interrupt-controller;
  242. #interrupt-cells = <2>;
  243. };
  244. pioE: gpio@fffffa00 {
  245. compatible = "atmel,at91rm9200-gpio";
  246. reg = <0xfffffa00 0x200>;
  247. interrupts = <5 4 1>;
  248. #gpio-cells = <2>;
  249. gpio-controller;
  250. interrupt-controller;
  251. #interrupt-cells = <2>;
  252. };
  253. };
  254. dbgu: serial@ffffee00 {
  255. compatible = "atmel,at91sam9260-usart";
  256. reg = <0xffffee00 0x200>;
  257. interrupts = <1 4 7>;
  258. pinctrl-names = "default";
  259. pinctrl-0 = <&pinctrl_dbgu>;
  260. status = "disabled";
  261. };
  262. usart0: serial@fff8c000 {
  263. compatible = "atmel,at91sam9260-usart";
  264. reg = <0xfff8c000 0x200>;
  265. interrupts = <7 4 5>;
  266. atmel,use-dma-rx;
  267. atmel,use-dma-tx;
  268. pinctrl-names = "default";
  269. pinctrl-0 = <&pinctrl_usart0>;
  270. status = "disabled";
  271. };
  272. usart1: serial@fff90000 {
  273. compatible = "atmel,at91sam9260-usart";
  274. reg = <0xfff90000 0x200>;
  275. interrupts = <8 4 5>;
  276. atmel,use-dma-rx;
  277. atmel,use-dma-tx;
  278. pinctrl-names = "default";
  279. pinctrl-0 = <&pinctrl_usart1>;
  280. status = "disabled";
  281. };
  282. usart2: serial@fff94000 {
  283. compatible = "atmel,at91sam9260-usart";
  284. reg = <0xfff94000 0x200>;
  285. interrupts = <9 4 5>;
  286. atmel,use-dma-rx;
  287. atmel,use-dma-tx;
  288. pinctrl-names = "default";
  289. pinctrl-0 = <&pinctrl_usart2>;
  290. status = "disabled";
  291. };
  292. usart3: serial@fff98000 {
  293. compatible = "atmel,at91sam9260-usart";
  294. reg = <0xfff98000 0x200>;
  295. interrupts = <10 4 5>;
  296. atmel,use-dma-rx;
  297. atmel,use-dma-tx;
  298. pinctrl-names = "default";
  299. pinctrl-0 = <&pinctrl_usart3>;
  300. status = "disabled";
  301. };
  302. macb0: ethernet@fffbc000 {
  303. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  304. reg = <0xfffbc000 0x100>;
  305. interrupts = <25 4 3>;
  306. pinctrl-names = "default";
  307. pinctrl-0 = <&pinctrl_macb_rmii>;
  308. status = "disabled";
  309. };
  310. i2c0: i2c@fff84000 {
  311. compatible = "atmel,at91sam9g10-i2c";
  312. reg = <0xfff84000 0x100>;
  313. interrupts = <12 4 6>;
  314. #address-cells = <1>;
  315. #size-cells = <0>;
  316. status = "disabled";
  317. };
  318. i2c1: i2c@fff88000 {
  319. compatible = "atmel,at91sam9g10-i2c";
  320. reg = <0xfff88000 0x100>;
  321. interrupts = <13 4 6>;
  322. #address-cells = <1>;
  323. #size-cells = <0>;
  324. status = "disabled";
  325. };
  326. adc0: adc@fffb0000 {
  327. compatible = "atmel,at91sam9260-adc";
  328. reg = <0xfffb0000 0x100>;
  329. interrupts = <20 4 0>;
  330. atmel,adc-use-external-triggers;
  331. atmel,adc-channels-used = <0xff>;
  332. atmel,adc-vref = <3300>;
  333. atmel,adc-num-channels = <8>;
  334. atmel,adc-startup-time = <40>;
  335. atmel,adc-channel-base = <0x30>;
  336. atmel,adc-drdy-mask = <0x10000>;
  337. atmel,adc-status-register = <0x1c>;
  338. atmel,adc-trigger-register = <0x08>;
  339. trigger@0 {
  340. trigger-name = "external-rising";
  341. trigger-value = <0x1>;
  342. trigger-external;
  343. };
  344. trigger@1 {
  345. trigger-name = "external-falling";
  346. trigger-value = <0x2>;
  347. trigger-external;
  348. };
  349. trigger@2 {
  350. trigger-name = "external-any";
  351. trigger-value = <0x3>;
  352. trigger-external;
  353. };
  354. trigger@3 {
  355. trigger-name = "continuous";
  356. trigger-value = <0x6>;
  357. };
  358. };
  359. };
  360. nand0: nand@40000000 {
  361. compatible = "atmel,at91rm9200-nand";
  362. #address-cells = <1>;
  363. #size-cells = <1>;
  364. reg = <0x40000000 0x10000000
  365. 0xffffe200 0x200
  366. >;
  367. atmel,nand-addr-offset = <21>;
  368. atmel,nand-cmd-offset = <22>;
  369. pinctrl-names = "default";
  370. pinctrl-0 = <&pinctrl_nand>;
  371. gpios = <&pioC 8 0
  372. &pioC 14 0
  373. 0
  374. >;
  375. status = "disabled";
  376. };
  377. usb0: ohci@00700000 {
  378. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  379. reg = <0x00700000 0x100000>;
  380. interrupts = <22 4 2>;
  381. status = "disabled";
  382. };
  383. usb1: ehci@00800000 {
  384. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  385. reg = <0x00800000 0x100000>;
  386. interrupts = <22 4 2>;
  387. status = "disabled";
  388. };
  389. };
  390. i2c@0 {
  391. compatible = "i2c-gpio";
  392. gpios = <&pioA 20 0 /* sda */
  393. &pioA 21 0 /* scl */
  394. >;
  395. i2c-gpio,sda-open-drain;
  396. i2c-gpio,scl-open-drain;
  397. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  398. #address-cells = <1>;
  399. #size-cells = <0>;
  400. status = "disabled";
  401. };
  402. };