htc_drv_init.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834
  1. /*
  2. * Copyright (c) 2010 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "htc.h"
  17. MODULE_AUTHOR("Atheros Communications");
  18. MODULE_LICENSE("Dual BSD/GPL");
  19. MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
  20. static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  21. module_param_named(debug, ath9k_debug, uint, 0);
  22. MODULE_PARM_DESC(debug, "Debugging mask");
  23. int htc_modparam_nohwcrypt;
  24. module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
  25. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  26. #define CHAN2G(_freq, _idx) { \
  27. .center_freq = (_freq), \
  28. .hw_value = (_idx), \
  29. .max_power = 20, \
  30. }
  31. static struct ieee80211_channel ath9k_2ghz_channels[] = {
  32. CHAN2G(2412, 0), /* Channel 1 */
  33. CHAN2G(2417, 1), /* Channel 2 */
  34. CHAN2G(2422, 2), /* Channel 3 */
  35. CHAN2G(2427, 3), /* Channel 4 */
  36. CHAN2G(2432, 4), /* Channel 5 */
  37. CHAN2G(2437, 5), /* Channel 6 */
  38. CHAN2G(2442, 6), /* Channel 7 */
  39. CHAN2G(2447, 7), /* Channel 8 */
  40. CHAN2G(2452, 8), /* Channel 9 */
  41. CHAN2G(2457, 9), /* Channel 10 */
  42. CHAN2G(2462, 10), /* Channel 11 */
  43. CHAN2G(2467, 11), /* Channel 12 */
  44. CHAN2G(2472, 12), /* Channel 13 */
  45. CHAN2G(2484, 13), /* Channel 14 */
  46. };
  47. /* Atheros hardware rate code addition for short premble */
  48. #define SHPCHECK(__hw_rate, __flags) \
  49. ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
  50. #define RATE(_bitrate, _hw_rate, _flags) { \
  51. .bitrate = (_bitrate), \
  52. .flags = (_flags), \
  53. .hw_value = (_hw_rate), \
  54. .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
  55. }
  56. static struct ieee80211_rate ath9k_legacy_rates[] = {
  57. RATE(10, 0x1b, 0),
  58. RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
  59. RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
  60. RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
  61. RATE(60, 0x0b, 0),
  62. RATE(90, 0x0f, 0),
  63. RATE(120, 0x0a, 0),
  64. RATE(180, 0x0e, 0),
  65. RATE(240, 0x09, 0),
  66. RATE(360, 0x0d, 0),
  67. RATE(480, 0x08, 0),
  68. RATE(540, 0x0c, 0),
  69. };
  70. static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
  71. {
  72. int time_left;
  73. if (atomic_read(&priv->htc->tgt_ready) > 0) {
  74. atomic_dec(&priv->htc->tgt_ready);
  75. return 0;
  76. }
  77. /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
  78. time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
  79. if (!time_left) {
  80. dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
  81. return -ETIMEDOUT;
  82. }
  83. atomic_dec(&priv->htc->tgt_ready);
  84. return 0;
  85. }
  86. static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
  87. {
  88. ath9k_htc_exit_debug(priv->ah);
  89. ath9k_hw_deinit(priv->ah);
  90. tasklet_kill(&priv->wmi_tasklet);
  91. tasklet_kill(&priv->rx_tasklet);
  92. tasklet_kill(&priv->tx_tasklet);
  93. kfree(priv->ah);
  94. priv->ah = NULL;
  95. }
  96. static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
  97. {
  98. struct ieee80211_hw *hw = priv->hw;
  99. wiphy_rfkill_stop_polling(hw->wiphy);
  100. ath9k_deinit_leds(priv);
  101. ieee80211_unregister_hw(hw);
  102. ath9k_rx_cleanup(priv);
  103. ath9k_tx_cleanup(priv);
  104. ath9k_deinit_priv(priv);
  105. }
  106. static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
  107. u16 service_id,
  108. void (*tx) (void *,
  109. struct sk_buff *,
  110. enum htc_endpoint_id,
  111. bool txok),
  112. enum htc_endpoint_id *ep_id)
  113. {
  114. struct htc_service_connreq req;
  115. memset(&req, 0, sizeof(struct htc_service_connreq));
  116. req.service_id = service_id;
  117. req.ep_callbacks.priv = priv;
  118. req.ep_callbacks.rx = ath9k_htc_rxep;
  119. req.ep_callbacks.tx = tx;
  120. return htc_connect_service(priv->htc, &req, ep_id);
  121. }
  122. static int ath9k_init_htc_services(struct ath9k_htc_priv *priv)
  123. {
  124. int ret;
  125. /* WMI CMD*/
  126. ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
  127. if (ret)
  128. goto err;
  129. /* Beacon */
  130. ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
  131. &priv->beacon_ep);
  132. if (ret)
  133. goto err;
  134. /* CAB */
  135. ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
  136. &priv->cab_ep);
  137. if (ret)
  138. goto err;
  139. /* UAPSD */
  140. ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
  141. &priv->uapsd_ep);
  142. if (ret)
  143. goto err;
  144. /* MGMT */
  145. ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
  146. &priv->mgmt_ep);
  147. if (ret)
  148. goto err;
  149. /* DATA BE */
  150. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
  151. &priv->data_be_ep);
  152. if (ret)
  153. goto err;
  154. /* DATA BK */
  155. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
  156. &priv->data_bk_ep);
  157. if (ret)
  158. goto err;
  159. /* DATA VI */
  160. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
  161. &priv->data_vi_ep);
  162. if (ret)
  163. goto err;
  164. /* DATA VO */
  165. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
  166. &priv->data_vo_ep);
  167. if (ret)
  168. goto err;
  169. ret = htc_init(priv->htc);
  170. if (ret)
  171. goto err;
  172. return 0;
  173. err:
  174. dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
  175. return ret;
  176. }
  177. static int ath9k_reg_notifier(struct wiphy *wiphy,
  178. struct regulatory_request *request)
  179. {
  180. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  181. struct ath9k_htc_priv *priv = hw->priv;
  182. return ath_reg_notifier_apply(wiphy, request,
  183. ath9k_hw_regulatory(priv->ah));
  184. }
  185. static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
  186. {
  187. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  188. struct ath_common *common = ath9k_hw_common(ah);
  189. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  190. __be32 val, reg = cpu_to_be32(reg_offset);
  191. int r;
  192. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  193. (u8 *) &reg, sizeof(reg),
  194. (u8 *) &val, sizeof(val),
  195. 100);
  196. if (unlikely(r)) {
  197. ath_print(common, ATH_DBG_WMI,
  198. "REGISTER READ FAILED: (0x%04x, %d)\n",
  199. reg_offset, r);
  200. return -EIO;
  201. }
  202. return be32_to_cpu(val);
  203. }
  204. static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
  205. {
  206. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  207. struct ath_common *common = ath9k_hw_common(ah);
  208. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  209. __be32 buf[2] = {
  210. cpu_to_be32(reg_offset),
  211. cpu_to_be32(val),
  212. };
  213. int r;
  214. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  215. (u8 *) &buf, sizeof(buf),
  216. (u8 *) &val, sizeof(val),
  217. 100);
  218. if (unlikely(r)) {
  219. ath_print(common, ATH_DBG_WMI,
  220. "REGISTER WRITE FAILED:(0x%04x, %d)\n",
  221. reg_offset, r);
  222. }
  223. }
  224. static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
  225. {
  226. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  227. struct ath_common *common = ath9k_hw_common(ah);
  228. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  229. u32 rsp_status;
  230. int r;
  231. mutex_lock(&priv->wmi->multi_write_mutex);
  232. /* Store the register/value */
  233. priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
  234. cpu_to_be32(reg_offset);
  235. priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
  236. cpu_to_be32(val);
  237. priv->wmi->multi_write_idx++;
  238. /* If the buffer is full, send it out. */
  239. if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
  240. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  241. (u8 *) &priv->wmi->multi_write,
  242. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  243. (u8 *) &rsp_status, sizeof(rsp_status),
  244. 100);
  245. if (unlikely(r)) {
  246. ath_print(common, ATH_DBG_WMI,
  247. "REGISTER WRITE FAILED, multi len: %d\n",
  248. priv->wmi->multi_write_idx);
  249. }
  250. priv->wmi->multi_write_idx = 0;
  251. }
  252. mutex_unlock(&priv->wmi->multi_write_mutex);
  253. }
  254. static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
  255. {
  256. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  257. struct ath_common *common = ath9k_hw_common(ah);
  258. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  259. if (atomic_read(&priv->wmi->mwrite_cnt))
  260. ath9k_regwrite_buffer(hw_priv, val, reg_offset);
  261. else
  262. ath9k_regwrite_single(hw_priv, val, reg_offset);
  263. }
  264. static void ath9k_enable_regwrite_buffer(void *hw_priv)
  265. {
  266. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  267. struct ath_common *common = ath9k_hw_common(ah);
  268. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  269. atomic_inc(&priv->wmi->mwrite_cnt);
  270. }
  271. static void ath9k_disable_regwrite_buffer(void *hw_priv)
  272. {
  273. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  274. struct ath_common *common = ath9k_hw_common(ah);
  275. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  276. atomic_dec(&priv->wmi->mwrite_cnt);
  277. }
  278. static void ath9k_regwrite_flush(void *hw_priv)
  279. {
  280. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  281. struct ath_common *common = ath9k_hw_common(ah);
  282. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  283. u32 rsp_status;
  284. int r;
  285. mutex_lock(&priv->wmi->multi_write_mutex);
  286. if (priv->wmi->multi_write_idx) {
  287. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  288. (u8 *) &priv->wmi->multi_write,
  289. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  290. (u8 *) &rsp_status, sizeof(rsp_status),
  291. 100);
  292. if (unlikely(r)) {
  293. ath_print(common, ATH_DBG_WMI,
  294. "REGISTER WRITE FAILED, multi len: %d\n",
  295. priv->wmi->multi_write_idx);
  296. }
  297. priv->wmi->multi_write_idx = 0;
  298. }
  299. mutex_unlock(&priv->wmi->multi_write_mutex);
  300. }
  301. static const struct ath_ops ath9k_common_ops = {
  302. .read = ath9k_regread,
  303. .write = ath9k_regwrite,
  304. .enable_write_buffer = ath9k_enable_regwrite_buffer,
  305. .disable_write_buffer = ath9k_disable_regwrite_buffer,
  306. .write_flush = ath9k_regwrite_flush,
  307. };
  308. static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
  309. {
  310. *csz = L1_CACHE_BYTES >> 2;
  311. }
  312. static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
  313. {
  314. struct ath_hw *ah = (struct ath_hw *) common->ah;
  315. (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  316. if (!ath9k_hw_wait(ah,
  317. AR_EEPROM_STATUS_DATA,
  318. AR_EEPROM_STATUS_DATA_BUSY |
  319. AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  320. AH_WAIT_TIMEOUT))
  321. return false;
  322. *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  323. AR_EEPROM_STATUS_DATA_VAL);
  324. return true;
  325. }
  326. static const struct ath_bus_ops ath9k_usb_bus_ops = {
  327. .ath_bus_type = ATH_USB,
  328. .read_cachesize = ath_usb_read_cachesize,
  329. .eeprom_read = ath_usb_eeprom_read,
  330. };
  331. static void setup_ht_cap(struct ath9k_htc_priv *priv,
  332. struct ieee80211_sta_ht_cap *ht_info)
  333. {
  334. ht_info->ht_supported = true;
  335. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  336. IEEE80211_HT_CAP_SM_PS |
  337. IEEE80211_HT_CAP_SGI_40 |
  338. IEEE80211_HT_CAP_DSSSCCK40;
  339. ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  340. ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
  341. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  342. ht_info->mcs.rx_mask[0] = 0xff;
  343. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
  344. }
  345. static int ath9k_init_queues(struct ath9k_htc_priv *priv)
  346. {
  347. struct ath_common *common = ath9k_hw_common(priv->ah);
  348. int i;
  349. for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
  350. priv->hwq_map[i] = -1;
  351. if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_BE)) {
  352. ath_print(common, ATH_DBG_FATAL,
  353. "Unable to setup xmit queue for BE traffic\n");
  354. goto err;
  355. }
  356. if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_BK)) {
  357. ath_print(common, ATH_DBG_FATAL,
  358. "Unable to setup xmit queue for BK traffic\n");
  359. goto err;
  360. }
  361. if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_VI)) {
  362. ath_print(common, ATH_DBG_FATAL,
  363. "Unable to setup xmit queue for VI traffic\n");
  364. goto err;
  365. }
  366. if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_VO)) {
  367. ath_print(common, ATH_DBG_FATAL,
  368. "Unable to setup xmit queue for VO traffic\n");
  369. goto err;
  370. }
  371. return 0;
  372. err:
  373. return -EINVAL;
  374. }
  375. static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
  376. {
  377. struct ath_common *common = ath9k_hw_common(priv->ah);
  378. int i = 0;
  379. /* Get the hardware key cache size. */
  380. common->keymax = priv->ah->caps.keycache_size;
  381. if (common->keymax > ATH_KEYMAX) {
  382. ath_print(common, ATH_DBG_ANY,
  383. "Warning, using only %u entries in %u key cache\n",
  384. ATH_KEYMAX, common->keymax);
  385. common->keymax = ATH_KEYMAX;
  386. }
  387. /*
  388. * Reset the key cache since some parts do not
  389. * reset the contents on initial power up.
  390. */
  391. for (i = 0; i < common->keymax; i++)
  392. ath9k_hw_keyreset(priv->ah, (u16) i);
  393. if (ath9k_hw_getcapability(priv->ah, ATH9K_CAP_CIPHER,
  394. ATH9K_CIPHER_TKIP, NULL)) {
  395. /*
  396. * Whether we should enable h/w TKIP MIC.
  397. * XXX: if we don't support WME TKIP MIC, then we wouldn't
  398. * report WMM capable, so it's always safe to turn on
  399. * TKIP MIC in this case.
  400. */
  401. ath9k_hw_setcapability(priv->ah, ATH9K_CAP_TKIP_MIC, 0, 1, NULL);
  402. }
  403. /*
  404. * Check whether the separate key cache entries
  405. * are required to handle both tx+rx MIC keys.
  406. * With split mic keys the number of stations is limited
  407. * to 27 otherwise 59.
  408. */
  409. if (ath9k_hw_getcapability(priv->ah, ATH9K_CAP_CIPHER,
  410. ATH9K_CIPHER_TKIP, NULL)
  411. && ath9k_hw_getcapability(priv->ah, ATH9K_CAP_CIPHER,
  412. ATH9K_CIPHER_MIC, NULL)
  413. && ath9k_hw_getcapability(priv->ah, ATH9K_CAP_TKIP_SPLIT,
  414. 0, NULL))
  415. common->splitmic = 1;
  416. /* turn on mcast key search if possible */
  417. if (!ath9k_hw_getcapability(priv->ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
  418. (void)ath9k_hw_setcapability(priv->ah, ATH9K_CAP_MCAST_KEYSRCH,
  419. 1, 1, NULL);
  420. }
  421. static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
  422. {
  423. if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) {
  424. priv->sbands[IEEE80211_BAND_2GHZ].channels =
  425. ath9k_2ghz_channels;
  426. priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  427. priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
  428. ARRAY_SIZE(ath9k_2ghz_channels);
  429. priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
  430. priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
  431. ARRAY_SIZE(ath9k_legacy_rates);
  432. }
  433. }
  434. static void ath9k_init_misc(struct ath9k_htc_priv *priv)
  435. {
  436. struct ath_common *common = ath9k_hw_common(priv->ah);
  437. common->tx_chainmask = priv->ah->caps.tx_chainmask;
  438. common->rx_chainmask = priv->ah->caps.rx_chainmask;
  439. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  440. memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
  441. priv->op_flags |= OP_TXAGGR;
  442. priv->ah->opmode = NL80211_IFTYPE_STATION;
  443. }
  444. static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid)
  445. {
  446. struct ath_hw *ah = NULL;
  447. struct ath_common *common;
  448. int ret = 0, csz = 0;
  449. priv->op_flags |= OP_INVALID;
  450. ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
  451. if (!ah)
  452. return -ENOMEM;
  453. ah->hw_version.devid = devid;
  454. ah->hw_version.subsysid = 0; /* FIXME */
  455. priv->ah = ah;
  456. common = ath9k_hw_common(ah);
  457. common->ops = &ath9k_common_ops;
  458. common->bus_ops = &ath9k_usb_bus_ops;
  459. common->ah = ah;
  460. common->hw = priv->hw;
  461. common->priv = priv;
  462. common->debug_mask = ath9k_debug;
  463. spin_lock_init(&priv->wmi->wmi_lock);
  464. spin_lock_init(&priv->beacon_lock);
  465. spin_lock_init(&priv->tx_lock);
  466. mutex_init(&priv->mutex);
  467. mutex_init(&priv->aggr_work.mutex);
  468. mutex_init(&priv->htc_pm_lock);
  469. tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet,
  470. (unsigned long)priv);
  471. tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
  472. (unsigned long)priv);
  473. tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv);
  474. INIT_DELAYED_WORK(&priv->ath9k_aggr_work, ath9k_htc_aggr_work);
  475. INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work);
  476. INIT_WORK(&priv->ps_work, ath9k_ps_work);
  477. /*
  478. * Cache line size is used to size and align various
  479. * structures used to communicate with the hardware.
  480. */
  481. ath_read_cachesize(common, &csz);
  482. common->cachelsz = csz << 2; /* convert to bytes */
  483. ret = ath9k_hw_init(ah);
  484. if (ret) {
  485. ath_print(common, ATH_DBG_FATAL,
  486. "Unable to initialize hardware; "
  487. "initialization status: %d\n", ret);
  488. goto err_hw;
  489. }
  490. ret = ath9k_htc_init_debug(ah);
  491. if (ret) {
  492. ath_print(common, ATH_DBG_FATAL,
  493. "Unable to create debugfs files\n");
  494. goto err_debug;
  495. }
  496. ret = ath9k_init_queues(priv);
  497. if (ret)
  498. goto err_queues;
  499. ath9k_init_crypto(priv);
  500. ath9k_init_channels_rates(priv);
  501. ath9k_init_misc(priv);
  502. return 0;
  503. err_queues:
  504. ath9k_htc_exit_debug(ah);
  505. err_debug:
  506. ath9k_hw_deinit(ah);
  507. err_hw:
  508. kfree(ah);
  509. priv->ah = NULL;
  510. return ret;
  511. }
  512. static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
  513. struct ieee80211_hw *hw)
  514. {
  515. struct ath_common *common = ath9k_hw_common(priv->ah);
  516. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  517. IEEE80211_HW_AMPDU_AGGREGATION |
  518. IEEE80211_HW_SPECTRUM_MGMT |
  519. IEEE80211_HW_HAS_RATE_CONTROL |
  520. IEEE80211_HW_RX_INCLUDES_FCS |
  521. IEEE80211_HW_SUPPORTS_PS |
  522. IEEE80211_HW_PS_NULLFUNC_STACK;
  523. hw->wiphy->interface_modes =
  524. BIT(NL80211_IFTYPE_STATION) |
  525. BIT(NL80211_IFTYPE_ADHOC);
  526. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  527. hw->queues = 4;
  528. hw->channel_change_time = 5000;
  529. hw->max_listen_interval = 10;
  530. hw->vif_data_size = sizeof(struct ath9k_htc_vif);
  531. hw->sta_data_size = sizeof(struct ath9k_htc_sta);
  532. /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
  533. hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
  534. sizeof(struct htc_frame_hdr) + 4;
  535. if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
  536. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  537. &priv->sbands[IEEE80211_BAND_2GHZ];
  538. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  539. if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
  540. setup_ht_cap(priv,
  541. &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  542. }
  543. SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
  544. }
  545. static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
  546. {
  547. struct ieee80211_hw *hw = priv->hw;
  548. struct ath_common *common;
  549. struct ath_hw *ah;
  550. int error = 0;
  551. struct ath_regulatory *reg;
  552. /* Bring up device */
  553. error = ath9k_init_priv(priv, devid);
  554. if (error != 0)
  555. goto err_init;
  556. ah = priv->ah;
  557. common = ath9k_hw_common(ah);
  558. ath9k_set_hw_capab(priv, hw);
  559. /* Initialize regulatory */
  560. error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
  561. ath9k_reg_notifier);
  562. if (error)
  563. goto err_regd;
  564. reg = &common->regulatory;
  565. /* Setup TX */
  566. error = ath9k_tx_init(priv);
  567. if (error != 0)
  568. goto err_tx;
  569. /* Setup RX */
  570. error = ath9k_rx_init(priv);
  571. if (error != 0)
  572. goto err_rx;
  573. /* Register with mac80211 */
  574. error = ieee80211_register_hw(hw);
  575. if (error)
  576. goto err_register;
  577. /* Handle world regulatory */
  578. if (!ath_is_world_regd(reg)) {
  579. error = regulatory_hint(hw->wiphy, reg->alpha2);
  580. if (error)
  581. goto err_world;
  582. }
  583. ath9k_init_leds(priv);
  584. ath9k_start_rfkill_poll(priv);
  585. return 0;
  586. err_world:
  587. ieee80211_unregister_hw(hw);
  588. err_register:
  589. ath9k_rx_cleanup(priv);
  590. err_rx:
  591. ath9k_tx_cleanup(priv);
  592. err_tx:
  593. /* Nothing */
  594. err_regd:
  595. ath9k_deinit_priv(priv);
  596. err_init:
  597. return error;
  598. }
  599. int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
  600. u16 devid)
  601. {
  602. struct ieee80211_hw *hw;
  603. struct ath9k_htc_priv *priv;
  604. int ret;
  605. hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
  606. if (!hw)
  607. return -ENOMEM;
  608. priv = hw->priv;
  609. priv->hw = hw;
  610. priv->htc = htc_handle;
  611. priv->dev = dev;
  612. htc_handle->drv_priv = priv;
  613. SET_IEEE80211_DEV(hw, priv->dev);
  614. ret = ath9k_htc_wait_for_target(priv);
  615. if (ret)
  616. goto err_free;
  617. priv->wmi = ath9k_init_wmi(priv);
  618. if (!priv->wmi) {
  619. ret = -EINVAL;
  620. goto err_free;
  621. }
  622. ret = ath9k_init_htc_services(priv);
  623. if (ret)
  624. goto err_init;
  625. /* The device may have been unplugged earlier. */
  626. priv->op_flags &= ~OP_UNPLUGGED;
  627. ret = ath9k_init_device(priv, devid);
  628. if (ret)
  629. goto err_init;
  630. return 0;
  631. err_init:
  632. ath9k_deinit_wmi(priv);
  633. err_free:
  634. ieee80211_free_hw(hw);
  635. return ret;
  636. }
  637. void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
  638. {
  639. if (htc_handle->drv_priv) {
  640. /* Check if the device has been yanked out. */
  641. if (hotunplug)
  642. htc_handle->drv_priv->op_flags |= OP_UNPLUGGED;
  643. ath9k_deinit_device(htc_handle->drv_priv);
  644. ath9k_deinit_wmi(htc_handle->drv_priv);
  645. ieee80211_free_hw(htc_handle->drv_priv->hw);
  646. }
  647. }
  648. #ifdef CONFIG_PM
  649. int ath9k_htc_resume(struct htc_target *htc_handle)
  650. {
  651. int ret;
  652. ret = ath9k_htc_wait_for_target(htc_handle->drv_priv);
  653. if (ret)
  654. return ret;
  655. ret = ath9k_init_htc_services(htc_handle->drv_priv);
  656. return ret;
  657. }
  658. #endif
  659. static int __init ath9k_htc_init(void)
  660. {
  661. int error;
  662. error = ath9k_htc_debug_create_root();
  663. if (error < 0) {
  664. printk(KERN_ERR
  665. "ath9k_htc: Unable to create debugfs root: %d\n",
  666. error);
  667. goto err_dbg;
  668. }
  669. error = ath9k_hif_usb_init();
  670. if (error < 0) {
  671. printk(KERN_ERR
  672. "ath9k_htc: No USB devices found,"
  673. " driver not installed.\n");
  674. error = -ENODEV;
  675. goto err_usb;
  676. }
  677. return 0;
  678. err_usb:
  679. ath9k_htc_debug_remove_root();
  680. err_dbg:
  681. return error;
  682. }
  683. module_init(ath9k_htc_init);
  684. static void __exit ath9k_htc_exit(void)
  685. {
  686. ath9k_hif_usb_exit();
  687. ath9k_htc_debug_remove_root();
  688. printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
  689. }
  690. module_exit(ath9k_htc_exit);