eeprom.c 7.0 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
  18. {
  19. if (fbin == AR5416_BCHAN_UNUSED)
  20. return fbin;
  21. return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
  22. }
  23. void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
  24. u32 shift, u32 val)
  25. {
  26. u32 regVal;
  27. regVal = REG_READ(ah, reg) & ~mask;
  28. regVal |= (val << shift) & mask;
  29. REG_WRITE(ah, reg, regVal);
  30. if (ah->config.analog_shiftreg)
  31. udelay(100);
  32. }
  33. int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
  34. int16_t targetLeft, int16_t targetRight)
  35. {
  36. int16_t rv;
  37. if (srcRight == srcLeft) {
  38. rv = targetLeft;
  39. } else {
  40. rv = (int16_t) (((target - srcLeft) * targetRight +
  41. (srcRight - target) * targetLeft) /
  42. (srcRight - srcLeft));
  43. }
  44. return rv;
  45. }
  46. bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
  47. u16 *indexL, u16 *indexR)
  48. {
  49. u16 i;
  50. if (target <= pList[0]) {
  51. *indexL = *indexR = 0;
  52. return true;
  53. }
  54. if (target >= pList[listSize - 1]) {
  55. *indexL = *indexR = (u16) (listSize - 1);
  56. return true;
  57. }
  58. for (i = 0; i < listSize - 1; i++) {
  59. if (pList[i] == target) {
  60. *indexL = *indexR = i;
  61. return true;
  62. }
  63. if (target < pList[i + 1]) {
  64. *indexL = i;
  65. *indexR = (u16) (i + 1);
  66. return false;
  67. }
  68. }
  69. return false;
  70. }
  71. bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
  72. {
  73. return common->bus_ops->eeprom_read(common, off, data);
  74. }
  75. void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
  76. u8 *pVpdList, u16 numIntercepts,
  77. u8 *pRetVpdList)
  78. {
  79. u16 i, k;
  80. u8 currPwr = pwrMin;
  81. u16 idxL = 0, idxR = 0;
  82. for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
  83. ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
  84. numIntercepts, &(idxL),
  85. &(idxR));
  86. if (idxR < 1)
  87. idxR = 1;
  88. if (idxL == numIntercepts - 1)
  89. idxL = (u16) (numIntercepts - 2);
  90. if (pPwrList[idxL] == pPwrList[idxR])
  91. k = pVpdList[idxL];
  92. else
  93. k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
  94. (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
  95. (pPwrList[idxR] - pPwrList[idxL]));
  96. pRetVpdList[i] = (u8) k;
  97. currPwr += 2;
  98. }
  99. }
  100. void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
  101. struct ath9k_channel *chan,
  102. struct cal_target_power_leg *powInfo,
  103. u16 numChannels,
  104. struct cal_target_power_leg *pNewPower,
  105. u16 numRates, bool isExtTarget)
  106. {
  107. struct chan_centers centers;
  108. u16 clo, chi;
  109. int i;
  110. int matchIndex = -1, lowIndex = -1;
  111. u16 freq;
  112. ath9k_hw_get_channel_centers(ah, chan, &centers);
  113. freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
  114. if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
  115. IS_CHAN_2GHZ(chan))) {
  116. matchIndex = 0;
  117. } else {
  118. for (i = 0; (i < numChannels) &&
  119. (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  120. if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
  121. IS_CHAN_2GHZ(chan))) {
  122. matchIndex = i;
  123. break;
  124. } else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
  125. IS_CHAN_2GHZ(chan)) && i > 0 &&
  126. freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
  127. IS_CHAN_2GHZ(chan))) {
  128. lowIndex = i - 1;
  129. break;
  130. }
  131. }
  132. if ((matchIndex == -1) && (lowIndex == -1))
  133. matchIndex = i - 1;
  134. }
  135. if (matchIndex != -1) {
  136. *pNewPower = powInfo[matchIndex];
  137. } else {
  138. clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
  139. IS_CHAN_2GHZ(chan));
  140. chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
  141. IS_CHAN_2GHZ(chan));
  142. for (i = 0; i < numRates; i++) {
  143. pNewPower->tPow2x[i] =
  144. (u8)ath9k_hw_interpolate(freq, clo, chi,
  145. powInfo[lowIndex].tPow2x[i],
  146. powInfo[lowIndex + 1].tPow2x[i]);
  147. }
  148. }
  149. }
  150. void ath9k_hw_get_target_powers(struct ath_hw *ah,
  151. struct ath9k_channel *chan,
  152. struct cal_target_power_ht *powInfo,
  153. u16 numChannels,
  154. struct cal_target_power_ht *pNewPower,
  155. u16 numRates, bool isHt40Target)
  156. {
  157. struct chan_centers centers;
  158. u16 clo, chi;
  159. int i;
  160. int matchIndex = -1, lowIndex = -1;
  161. u16 freq;
  162. ath9k_hw_get_channel_centers(ah, chan, &centers);
  163. freq = isHt40Target ? centers.synth_center : centers.ctl_center;
  164. if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
  165. matchIndex = 0;
  166. } else {
  167. for (i = 0; (i < numChannels) &&
  168. (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  169. if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
  170. IS_CHAN_2GHZ(chan))) {
  171. matchIndex = i;
  172. break;
  173. } else
  174. if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
  175. IS_CHAN_2GHZ(chan)) && i > 0 &&
  176. freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
  177. IS_CHAN_2GHZ(chan))) {
  178. lowIndex = i - 1;
  179. break;
  180. }
  181. }
  182. if ((matchIndex == -1) && (lowIndex == -1))
  183. matchIndex = i - 1;
  184. }
  185. if (matchIndex != -1) {
  186. *pNewPower = powInfo[matchIndex];
  187. } else {
  188. clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
  189. IS_CHAN_2GHZ(chan));
  190. chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
  191. IS_CHAN_2GHZ(chan));
  192. for (i = 0; i < numRates; i++) {
  193. pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
  194. clo, chi,
  195. powInfo[lowIndex].tPow2x[i],
  196. powInfo[lowIndex + 1].tPow2x[i]);
  197. }
  198. }
  199. }
  200. u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
  201. bool is2GHz, int num_band_edges)
  202. {
  203. u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
  204. int i;
  205. for (i = 0; (i < num_band_edges) &&
  206. (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  207. if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
  208. twiceMaxEdgePower = pRdEdgesPower[i].tPower;
  209. break;
  210. } else if ((i > 0) &&
  211. (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
  212. is2GHz))) {
  213. if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
  214. is2GHz) < freq &&
  215. pRdEdgesPower[i - 1].flag) {
  216. twiceMaxEdgePower =
  217. pRdEdgesPower[i - 1].tPower;
  218. }
  219. break;
  220. }
  221. }
  222. return twiceMaxEdgePower;
  223. }
  224. int ath9k_hw_eeprom_init(struct ath_hw *ah)
  225. {
  226. int status;
  227. if (AR_SREV_9300_20_OR_LATER(ah))
  228. ah->eep_ops = &eep_ar9300_ops;
  229. else if (AR_SREV_9287(ah)) {
  230. ah->eep_ops = &eep_ar9287_ops;
  231. } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
  232. ah->eep_ops = &eep_4k_ops;
  233. } else {
  234. ah->eep_ops = &eep_def_ops;
  235. }
  236. if (!ah->eep_ops->fill_eeprom(ah))
  237. return -EIO;
  238. status = ah->eep_ops->check_eeprom(ah);
  239. return status;
  240. }