eeprom.c 49 KB

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  1. /*
  2. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
  4. * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
  5. *
  6. * Permission to use, copy, modify, and distribute this software for any
  7. * purpose with or without fee is hereby granted, provided that the above
  8. * copyright notice and this permission notice appear in all copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17. *
  18. */
  19. /*************************************\
  20. * EEPROM access functions and helpers *
  21. \*************************************/
  22. #include <linux/slab.h>
  23. #include "ath5k.h"
  24. #include "reg.h"
  25. #include "debug.h"
  26. #include "base.h"
  27. /*
  28. * Read from eeprom
  29. */
  30. static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
  31. {
  32. u32 status, timeout;
  33. ATH5K_TRACE(ah->ah_sc);
  34. /*
  35. * Initialize EEPROM access
  36. */
  37. if (ah->ah_version == AR5K_AR5210) {
  38. AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
  39. (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
  40. } else {
  41. ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
  42. AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
  43. AR5K_EEPROM_CMD_READ);
  44. }
  45. for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
  46. status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
  47. if (status & AR5K_EEPROM_STAT_RDDONE) {
  48. if (status & AR5K_EEPROM_STAT_RDERR)
  49. return -EIO;
  50. *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
  51. 0xffff);
  52. return 0;
  53. }
  54. udelay(15);
  55. }
  56. return -ETIMEDOUT;
  57. }
  58. /*
  59. * Translate binary channel representation in EEPROM to frequency
  60. */
  61. static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
  62. unsigned int mode)
  63. {
  64. u16 val;
  65. if (bin == AR5K_EEPROM_CHANNEL_DIS)
  66. return bin;
  67. if (mode == AR5K_EEPROM_MODE_11A) {
  68. if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
  69. val = (5 * bin) + 4800;
  70. else
  71. val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
  72. (bin * 10) + 5100;
  73. } else {
  74. if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
  75. val = bin + 2300;
  76. else
  77. val = bin + 2400;
  78. }
  79. return val;
  80. }
  81. /*
  82. * Initialize eeprom & capabilities structs
  83. */
  84. static int
  85. ath5k_eeprom_init_header(struct ath5k_hw *ah)
  86. {
  87. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  88. int ret;
  89. u16 val;
  90. u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
  91. /*
  92. * Read values from EEPROM and store them in the capability structure
  93. */
  94. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
  95. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
  96. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
  97. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
  98. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
  99. /* Return if we have an old EEPROM */
  100. if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
  101. return 0;
  102. /*
  103. * Validate the checksum of the EEPROM date. There are some
  104. * devices with invalid EEPROMs.
  105. */
  106. AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
  107. if (val) {
  108. eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) <<
  109. AR5K_EEPROM_SIZE_ENDLOC_SHIFT;
  110. AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val);
  111. eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE;
  112. /*
  113. * Fail safe check to prevent stupid loops due
  114. * to busted EEPROMs. XXX: This value is likely too
  115. * big still, waiting on a better value.
  116. */
  117. if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
  118. ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: "
  119. "%d (0x%04x) max expected: %d (0x%04x)\n",
  120. eep_max, eep_max,
  121. 3 * AR5K_EEPROM_INFO_MAX,
  122. 3 * AR5K_EEPROM_INFO_MAX);
  123. return -EIO;
  124. }
  125. }
  126. for (cksum = 0, offset = 0; offset < eep_max; offset++) {
  127. AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
  128. cksum ^= val;
  129. }
  130. if (cksum != AR5K_EEPROM_INFO_CKSUM) {
  131. ATH5K_ERR(ah->ah_sc, "Invalid EEPROM "
  132. "checksum: 0x%04x eep_max: 0x%04x (%s)\n",
  133. cksum, eep_max,
  134. eep_max == AR5K_EEPROM_INFO_MAX ?
  135. "default size" : "custom size");
  136. return -EIO;
  137. }
  138. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
  139. ee_ant_gain);
  140. if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
  141. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
  142. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
  143. /* XXX: Don't know which versions include these two */
  144. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
  145. if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
  146. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
  147. if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
  148. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
  149. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
  150. AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
  151. }
  152. }
  153. if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
  154. AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
  155. ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
  156. ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
  157. AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
  158. ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
  159. ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
  160. }
  161. AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
  162. if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
  163. ee->ee_is_hb63 = true;
  164. else
  165. ee->ee_is_hb63 = false;
  166. AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
  167. ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
  168. ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
  169. /* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION
  170. * and enable serdes programming if needed.
  171. *
  172. * XXX: Serdes values seem to be fixed so
  173. * no need to read them here, we write them
  174. * during ath5k_hw_attach */
  175. AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
  176. ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
  177. true : false;
  178. return 0;
  179. }
  180. /*
  181. * Read antenna infos from eeprom
  182. */
  183. static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
  184. unsigned int mode)
  185. {
  186. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  187. u32 o = *offset;
  188. u16 val;
  189. int ret, i = 0;
  190. AR5K_EEPROM_READ(o++, val);
  191. ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
  192. ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f;
  193. ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
  194. AR5K_EEPROM_READ(o++, val);
  195. ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
  196. ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
  197. ee->ee_ant_control[mode][i++] = val & 0x3f;
  198. AR5K_EEPROM_READ(o++, val);
  199. ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
  200. ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
  201. ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
  202. AR5K_EEPROM_READ(o++, val);
  203. ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
  204. ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
  205. ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
  206. ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
  207. AR5K_EEPROM_READ(o++, val);
  208. ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
  209. ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
  210. ee->ee_ant_control[mode][i++] = val & 0x3f;
  211. /* Get antenna switch tables */
  212. ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
  213. (ee->ee_ant_control[mode][0] << 4);
  214. ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
  215. ee->ee_ant_control[mode][1] |
  216. (ee->ee_ant_control[mode][2] << 6) |
  217. (ee->ee_ant_control[mode][3] << 12) |
  218. (ee->ee_ant_control[mode][4] << 18) |
  219. (ee->ee_ant_control[mode][5] << 24);
  220. ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
  221. ee->ee_ant_control[mode][6] |
  222. (ee->ee_ant_control[mode][7] << 6) |
  223. (ee->ee_ant_control[mode][8] << 12) |
  224. (ee->ee_ant_control[mode][9] << 18) |
  225. (ee->ee_ant_control[mode][10] << 24);
  226. /* return new offset */
  227. *offset = o;
  228. return 0;
  229. }
  230. /*
  231. * Read supported modes and some mode-specific calibration data
  232. * from eeprom
  233. */
  234. static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
  235. unsigned int mode)
  236. {
  237. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  238. u32 o = *offset;
  239. u16 val;
  240. int ret;
  241. ee->ee_n_piers[mode] = 0;
  242. AR5K_EEPROM_READ(o++, val);
  243. ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
  244. switch(mode) {
  245. case AR5K_EEPROM_MODE_11A:
  246. ee->ee_ob[mode][3] = (val >> 5) & 0x7;
  247. ee->ee_db[mode][3] = (val >> 2) & 0x7;
  248. ee->ee_ob[mode][2] = (val << 1) & 0x7;
  249. AR5K_EEPROM_READ(o++, val);
  250. ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
  251. ee->ee_db[mode][2] = (val >> 12) & 0x7;
  252. ee->ee_ob[mode][1] = (val >> 9) & 0x7;
  253. ee->ee_db[mode][1] = (val >> 6) & 0x7;
  254. ee->ee_ob[mode][0] = (val >> 3) & 0x7;
  255. ee->ee_db[mode][0] = val & 0x7;
  256. break;
  257. case AR5K_EEPROM_MODE_11G:
  258. case AR5K_EEPROM_MODE_11B:
  259. ee->ee_ob[mode][1] = (val >> 4) & 0x7;
  260. ee->ee_db[mode][1] = val & 0x7;
  261. break;
  262. }
  263. AR5K_EEPROM_READ(o++, val);
  264. ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
  265. ee->ee_thr_62[mode] = val & 0xff;
  266. if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
  267. ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
  268. AR5K_EEPROM_READ(o++, val);
  269. ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
  270. ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
  271. AR5K_EEPROM_READ(o++, val);
  272. ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
  273. if ((val & 0xff) & 0x80)
  274. ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
  275. else
  276. ee->ee_noise_floor_thr[mode] = val & 0xff;
  277. if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
  278. ee->ee_noise_floor_thr[mode] =
  279. mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
  280. AR5K_EEPROM_READ(o++, val);
  281. ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
  282. ee->ee_x_gain[mode] = (val >> 1) & 0xf;
  283. ee->ee_xpd[mode] = val & 0x1;
  284. if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
  285. mode != AR5K_EEPROM_MODE_11B)
  286. ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
  287. if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
  288. AR5K_EEPROM_READ(o++, val);
  289. ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
  290. if (mode == AR5K_EEPROM_MODE_11A)
  291. ee->ee_xr_power[mode] = val & 0x3f;
  292. else {
  293. /* b_DB_11[bg] and b_OB_11[bg] */
  294. ee->ee_ob[mode][0] = val & 0x7;
  295. ee->ee_db[mode][0] = (val >> 3) & 0x7;
  296. }
  297. }
  298. if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
  299. ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
  300. ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
  301. } else {
  302. ee->ee_i_gain[mode] = (val >> 13) & 0x7;
  303. AR5K_EEPROM_READ(o++, val);
  304. ee->ee_i_gain[mode] |= (val << 3) & 0x38;
  305. if (mode == AR5K_EEPROM_MODE_11G) {
  306. ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
  307. if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
  308. ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
  309. }
  310. }
  311. if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
  312. mode == AR5K_EEPROM_MODE_11A) {
  313. ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
  314. ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
  315. }
  316. if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
  317. goto done;
  318. /* Note: >= v5 have bg freq piers on another location
  319. * so these freq piers are ignored for >= v5 (should be 0xff
  320. * anyway) */
  321. switch(mode) {
  322. case AR5K_EEPROM_MODE_11A:
  323. if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
  324. break;
  325. AR5K_EEPROM_READ(o++, val);
  326. ee->ee_margin_tx_rx[mode] = val & 0x3f;
  327. break;
  328. case AR5K_EEPROM_MODE_11B:
  329. AR5K_EEPROM_READ(o++, val);
  330. ee->ee_pwr_cal_b[0].freq =
  331. ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
  332. if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
  333. ee->ee_n_piers[mode]++;
  334. ee->ee_pwr_cal_b[1].freq =
  335. ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
  336. if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
  337. ee->ee_n_piers[mode]++;
  338. AR5K_EEPROM_READ(o++, val);
  339. ee->ee_pwr_cal_b[2].freq =
  340. ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
  341. if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
  342. ee->ee_n_piers[mode]++;
  343. if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
  344. ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
  345. break;
  346. case AR5K_EEPROM_MODE_11G:
  347. AR5K_EEPROM_READ(o++, val);
  348. ee->ee_pwr_cal_g[0].freq =
  349. ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
  350. if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
  351. ee->ee_n_piers[mode]++;
  352. ee->ee_pwr_cal_g[1].freq =
  353. ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
  354. if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
  355. ee->ee_n_piers[mode]++;
  356. AR5K_EEPROM_READ(o++, val);
  357. ee->ee_turbo_max_power[mode] = val & 0x7f;
  358. ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
  359. AR5K_EEPROM_READ(o++, val);
  360. ee->ee_pwr_cal_g[2].freq =
  361. ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
  362. if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
  363. ee->ee_n_piers[mode]++;
  364. if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
  365. ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
  366. AR5K_EEPROM_READ(o++, val);
  367. ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
  368. ee->ee_q_cal[mode] = val & 0x1f;
  369. if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
  370. AR5K_EEPROM_READ(o++, val);
  371. ee->ee_cck_ofdm_gain_delta = val & 0xff;
  372. }
  373. break;
  374. }
  375. /*
  376. * Read turbo mode information on newer EEPROM versions
  377. */
  378. if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
  379. goto done;
  380. switch (mode){
  381. case AR5K_EEPROM_MODE_11A:
  382. ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
  383. ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
  384. AR5K_EEPROM_READ(o++, val);
  385. ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
  386. ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
  387. ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
  388. AR5K_EEPROM_READ(o++, val);
  389. ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
  390. ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
  391. if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
  392. ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
  393. break;
  394. case AR5K_EEPROM_MODE_11G:
  395. ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
  396. ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
  397. AR5K_EEPROM_READ(o++, val);
  398. ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
  399. ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
  400. ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
  401. AR5K_EEPROM_READ(o++, val);
  402. ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
  403. ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
  404. break;
  405. }
  406. done:
  407. /* return new offset */
  408. *offset = o;
  409. return 0;
  410. }
  411. /* Read mode-specific data (except power calibration data) */
  412. static int
  413. ath5k_eeprom_init_modes(struct ath5k_hw *ah)
  414. {
  415. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  416. u32 mode_offset[3];
  417. unsigned int mode;
  418. u32 offset;
  419. int ret;
  420. /*
  421. * Get values for all modes
  422. */
  423. mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
  424. mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
  425. mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
  426. ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
  427. AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
  428. for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
  429. offset = mode_offset[mode];
  430. ret = ath5k_eeprom_read_ants(ah, &offset, mode);
  431. if (ret)
  432. return ret;
  433. ret = ath5k_eeprom_read_modes(ah, &offset, mode);
  434. if (ret)
  435. return ret;
  436. }
  437. /* override for older eeprom versions for better performance */
  438. if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
  439. ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
  440. ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
  441. ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
  442. }
  443. return 0;
  444. }
  445. /* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
  446. * frequency mask) */
  447. static inline int
  448. ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
  449. struct ath5k_chan_pcal_info *pc, unsigned int mode)
  450. {
  451. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  452. int o = *offset;
  453. int i = 0;
  454. u8 freq1, freq2;
  455. int ret;
  456. u16 val;
  457. ee->ee_n_piers[mode] = 0;
  458. while(i < max) {
  459. AR5K_EEPROM_READ(o++, val);
  460. freq1 = val & 0xff;
  461. if (!freq1)
  462. break;
  463. pc[i++].freq = ath5k_eeprom_bin2freq(ee,
  464. freq1, mode);
  465. ee->ee_n_piers[mode]++;
  466. freq2 = (val >> 8) & 0xff;
  467. if (!freq2)
  468. break;
  469. pc[i++].freq = ath5k_eeprom_bin2freq(ee,
  470. freq2, mode);
  471. ee->ee_n_piers[mode]++;
  472. }
  473. /* return new offset */
  474. *offset = o;
  475. return 0;
  476. }
  477. /* Read frequency piers for 802.11a */
  478. static int
  479. ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
  480. {
  481. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  482. struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
  483. int i, ret;
  484. u16 val;
  485. u8 mask;
  486. if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
  487. ath5k_eeprom_read_freq_list(ah, &offset,
  488. AR5K_EEPROM_N_5GHZ_CHAN, pcal,
  489. AR5K_EEPROM_MODE_11A);
  490. } else {
  491. mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
  492. AR5K_EEPROM_READ(offset++, val);
  493. pcal[0].freq = (val >> 9) & mask;
  494. pcal[1].freq = (val >> 2) & mask;
  495. pcal[2].freq = (val << 5) & mask;
  496. AR5K_EEPROM_READ(offset++, val);
  497. pcal[2].freq |= (val >> 11) & 0x1f;
  498. pcal[3].freq = (val >> 4) & mask;
  499. pcal[4].freq = (val << 3) & mask;
  500. AR5K_EEPROM_READ(offset++, val);
  501. pcal[4].freq |= (val >> 13) & 0x7;
  502. pcal[5].freq = (val >> 6) & mask;
  503. pcal[6].freq = (val << 1) & mask;
  504. AR5K_EEPROM_READ(offset++, val);
  505. pcal[6].freq |= (val >> 15) & 0x1;
  506. pcal[7].freq = (val >> 8) & mask;
  507. pcal[8].freq = (val >> 1) & mask;
  508. pcal[9].freq = (val << 6) & mask;
  509. AR5K_EEPROM_READ(offset++, val);
  510. pcal[9].freq |= (val >> 10) & 0x3f;
  511. /* Fixed number of piers */
  512. ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
  513. for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
  514. pcal[i].freq = ath5k_eeprom_bin2freq(ee,
  515. pcal[i].freq, AR5K_EEPROM_MODE_11A);
  516. }
  517. }
  518. return 0;
  519. }
  520. /* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
  521. static inline int
  522. ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
  523. {
  524. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  525. struct ath5k_chan_pcal_info *pcal;
  526. switch(mode) {
  527. case AR5K_EEPROM_MODE_11B:
  528. pcal = ee->ee_pwr_cal_b;
  529. break;
  530. case AR5K_EEPROM_MODE_11G:
  531. pcal = ee->ee_pwr_cal_g;
  532. break;
  533. default:
  534. return -EINVAL;
  535. }
  536. ath5k_eeprom_read_freq_list(ah, &offset,
  537. AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
  538. mode);
  539. return 0;
  540. }
  541. /*
  542. * Read power calibration for RF5111 chips
  543. *
  544. * For RF5111 we have an XPD -eXternal Power Detector- curve
  545. * for each calibrated channel. Each curve has 0,5dB Power steps
  546. * on x axis and PCDAC steps (offsets) on y axis and looks like an
  547. * exponential function. To recreate the curve we read 11 points
  548. * here and interpolate later.
  549. */
  550. /* Used to match PCDAC steps with power values on RF5111 chips
  551. * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
  552. * steps that match with the power values we read from eeprom. On
  553. * older eeprom versions (< 3.2) these steps are equaly spaced at
  554. * 10% of the pcdac curve -until the curve reaches it's maximum-
  555. * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
  556. * these 11 steps are spaced in a different way. This function returns
  557. * the pcdac steps based on eeprom version and curve min/max so that we
  558. * can have pcdac/pwr points.
  559. */
  560. static inline void
  561. ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
  562. {
  563. static const u16 intercepts3[] =
  564. { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
  565. static const u16 intercepts3_2[] =
  566. { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
  567. const u16 *ip;
  568. int i;
  569. if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
  570. ip = intercepts3_2;
  571. else
  572. ip = intercepts3;
  573. for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
  574. vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
  575. }
  576. /* Convert RF5111 specific data to generic raw data
  577. * used by interpolation code */
  578. static int
  579. ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
  580. struct ath5k_chan_pcal_info *chinfo)
  581. {
  582. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  583. struct ath5k_chan_pcal_info_rf5111 *pcinfo;
  584. struct ath5k_pdgain_info *pd;
  585. u8 pier, point, idx;
  586. u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
  587. /* Fill raw data for each calibration pier */
  588. for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
  589. pcinfo = &chinfo[pier].rf5111_info;
  590. /* Allocate pd_curves for this cal pier */
  591. chinfo[pier].pd_curves =
  592. kcalloc(AR5K_EEPROM_N_PD_CURVES,
  593. sizeof(struct ath5k_pdgain_info),
  594. GFP_KERNEL);
  595. if (!chinfo[pier].pd_curves)
  596. return -ENOMEM;
  597. /* Only one curve for RF5111
  598. * find out which one and place
  599. * in in pd_curves.
  600. * Note: ee_x_gain is reversed here */
  601. for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) {
  602. if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
  603. pdgain_idx[0] = idx;
  604. break;
  605. }
  606. }
  607. ee->ee_pd_gains[mode] = 1;
  608. pd = &chinfo[pier].pd_curves[idx];
  609. pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111;
  610. /* Allocate pd points for this curve */
  611. pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
  612. sizeof(u8), GFP_KERNEL);
  613. if (!pd->pd_step)
  614. return -ENOMEM;
  615. pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
  616. sizeof(s16), GFP_KERNEL);
  617. if (!pd->pd_pwr)
  618. return -ENOMEM;
  619. /* Fill raw dataset
  620. * (convert power to 0.25dB units
  621. * for RF5112 combatibility) */
  622. for (point = 0; point < pd->pd_points; point++) {
  623. /* Absolute values */
  624. pd->pd_pwr[point] = 2 * pcinfo->pwr[point];
  625. /* Already sorted */
  626. pd->pd_step[point] = pcinfo->pcdac[point];
  627. }
  628. /* Set min/max pwr */
  629. chinfo[pier].min_pwr = pd->pd_pwr[0];
  630. chinfo[pier].max_pwr = pd->pd_pwr[10];
  631. }
  632. return 0;
  633. }
  634. /* Parse EEPROM data */
  635. static int
  636. ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
  637. {
  638. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  639. struct ath5k_chan_pcal_info *pcal;
  640. int offset, ret;
  641. int i;
  642. u16 val;
  643. offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
  644. switch(mode) {
  645. case AR5K_EEPROM_MODE_11A:
  646. if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
  647. return 0;
  648. ret = ath5k_eeprom_init_11a_pcal_freq(ah,
  649. offset + AR5K_EEPROM_GROUP1_OFFSET);
  650. if (ret < 0)
  651. return ret;
  652. offset += AR5K_EEPROM_GROUP2_OFFSET;
  653. pcal = ee->ee_pwr_cal_a;
  654. break;
  655. case AR5K_EEPROM_MODE_11B:
  656. if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
  657. !AR5K_EEPROM_HDR_11G(ee->ee_header))
  658. return 0;
  659. pcal = ee->ee_pwr_cal_b;
  660. offset += AR5K_EEPROM_GROUP3_OFFSET;
  661. /* fixed piers */
  662. pcal[0].freq = 2412;
  663. pcal[1].freq = 2447;
  664. pcal[2].freq = 2484;
  665. ee->ee_n_piers[mode] = 3;
  666. break;
  667. case AR5K_EEPROM_MODE_11G:
  668. if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
  669. return 0;
  670. pcal = ee->ee_pwr_cal_g;
  671. offset += AR5K_EEPROM_GROUP4_OFFSET;
  672. /* fixed piers */
  673. pcal[0].freq = 2312;
  674. pcal[1].freq = 2412;
  675. pcal[2].freq = 2484;
  676. ee->ee_n_piers[mode] = 3;
  677. break;
  678. default:
  679. return -EINVAL;
  680. }
  681. for (i = 0; i < ee->ee_n_piers[mode]; i++) {
  682. struct ath5k_chan_pcal_info_rf5111 *cdata =
  683. &pcal[i].rf5111_info;
  684. AR5K_EEPROM_READ(offset++, val);
  685. cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
  686. cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
  687. cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
  688. AR5K_EEPROM_READ(offset++, val);
  689. cdata->pwr[0] |= ((val >> 14) & 0x3);
  690. cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
  691. cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
  692. cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
  693. AR5K_EEPROM_READ(offset++, val);
  694. cdata->pwr[3] |= ((val >> 12) & 0xf);
  695. cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
  696. cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M);
  697. AR5K_EEPROM_READ(offset++, val);
  698. cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
  699. cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
  700. cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
  701. AR5K_EEPROM_READ(offset++, val);
  702. cdata->pwr[8] |= ((val >> 14) & 0x3);
  703. cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
  704. cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
  705. ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
  706. cdata->pcdac_max, cdata->pcdac);
  707. }
  708. return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
  709. }
  710. /*
  711. * Read power calibration for RF5112 chips
  712. *
  713. * For RF5112 we have 4 XPD -eXternal Power Detector- curves
  714. * for each calibrated channel on 0, -6, -12 and -18dbm but we only
  715. * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
  716. * power steps on x axis and PCDAC steps on y axis and looks like a
  717. * linear function. To recreate the curve and pass the power values
  718. * on hw, we read 4 points for xpd 0 (lower gain -> max power)
  719. * and 3 points for xpd 3 (higher gain -> lower power) here and
  720. * interpolate later.
  721. *
  722. * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
  723. */
  724. /* Convert RF5112 specific data to generic raw data
  725. * used by interpolation code */
  726. static int
  727. ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
  728. struct ath5k_chan_pcal_info *chinfo)
  729. {
  730. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  731. struct ath5k_chan_pcal_info_rf5112 *pcinfo;
  732. u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
  733. unsigned int pier, pdg, point;
  734. /* Fill raw data for each calibration pier */
  735. for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
  736. pcinfo = &chinfo[pier].rf5112_info;
  737. /* Allocate pd_curves for this cal pier */
  738. chinfo[pier].pd_curves =
  739. kcalloc(AR5K_EEPROM_N_PD_CURVES,
  740. sizeof(struct ath5k_pdgain_info),
  741. GFP_KERNEL);
  742. if (!chinfo[pier].pd_curves)
  743. return -ENOMEM;
  744. /* Fill pd_curves */
  745. for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
  746. u8 idx = pdgain_idx[pdg];
  747. struct ath5k_pdgain_info *pd =
  748. &chinfo[pier].pd_curves[idx];
  749. /* Lowest gain curve (max power) */
  750. if (pdg == 0) {
  751. /* One more point for better accuracy */
  752. pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS;
  753. /* Allocate pd points for this curve */
  754. pd->pd_step = kcalloc(pd->pd_points,
  755. sizeof(u8), GFP_KERNEL);
  756. if (!pd->pd_step)
  757. return -ENOMEM;
  758. pd->pd_pwr = kcalloc(pd->pd_points,
  759. sizeof(s16), GFP_KERNEL);
  760. if (!pd->pd_pwr)
  761. return -ENOMEM;
  762. /* Fill raw dataset
  763. * (all power levels are in 0.25dB units) */
  764. pd->pd_step[0] = pcinfo->pcdac_x0[0];
  765. pd->pd_pwr[0] = pcinfo->pwr_x0[0];
  766. for (point = 1; point < pd->pd_points;
  767. point++) {
  768. /* Absolute values */
  769. pd->pd_pwr[point] =
  770. pcinfo->pwr_x0[point];
  771. /* Deltas */
  772. pd->pd_step[point] =
  773. pd->pd_step[point - 1] +
  774. pcinfo->pcdac_x0[point];
  775. }
  776. /* Set min power for this frequency */
  777. chinfo[pier].min_pwr = pd->pd_pwr[0];
  778. /* Highest gain curve (min power) */
  779. } else if (pdg == 1) {
  780. pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS;
  781. /* Allocate pd points for this curve */
  782. pd->pd_step = kcalloc(pd->pd_points,
  783. sizeof(u8), GFP_KERNEL);
  784. if (!pd->pd_step)
  785. return -ENOMEM;
  786. pd->pd_pwr = kcalloc(pd->pd_points,
  787. sizeof(s16), GFP_KERNEL);
  788. if (!pd->pd_pwr)
  789. return -ENOMEM;
  790. /* Fill raw dataset
  791. * (all power levels are in 0.25dB units) */
  792. for (point = 0; point < pd->pd_points;
  793. point++) {
  794. /* Absolute values */
  795. pd->pd_pwr[point] =
  796. pcinfo->pwr_x3[point];
  797. /* Fixed points */
  798. pd->pd_step[point] =
  799. pcinfo->pcdac_x3[point];
  800. }
  801. /* Since we have a higher gain curve
  802. * override min power */
  803. chinfo[pier].min_pwr = pd->pd_pwr[0];
  804. }
  805. }
  806. }
  807. return 0;
  808. }
  809. /* Parse EEPROM data */
  810. static int
  811. ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
  812. {
  813. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  814. struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
  815. struct ath5k_chan_pcal_info *gen_chan_info;
  816. u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
  817. u32 offset;
  818. u8 i, c;
  819. u16 val;
  820. int ret;
  821. u8 pd_gains = 0;
  822. /* Count how many curves we have and
  823. * identify them (which one of the 4
  824. * available curves we have on each count).
  825. * Curves are stored from lower (x0) to
  826. * higher (x3) gain */
  827. for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) {
  828. /* ee_x_gain[mode] is x gain mask */
  829. if ((ee->ee_x_gain[mode] >> i) & 0x1)
  830. pdgain_idx[pd_gains++] = i;
  831. }
  832. ee->ee_pd_gains[mode] = pd_gains;
  833. if (pd_gains == 0 || pd_gains > 2)
  834. return -EINVAL;
  835. switch (mode) {
  836. case AR5K_EEPROM_MODE_11A:
  837. /*
  838. * Read 5GHz EEPROM channels
  839. */
  840. offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
  841. ath5k_eeprom_init_11a_pcal_freq(ah, offset);
  842. offset += AR5K_EEPROM_GROUP2_OFFSET;
  843. gen_chan_info = ee->ee_pwr_cal_a;
  844. break;
  845. case AR5K_EEPROM_MODE_11B:
  846. offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
  847. if (AR5K_EEPROM_HDR_11A(ee->ee_header))
  848. offset += AR5K_EEPROM_GROUP3_OFFSET;
  849. /* NB: frequency piers parsed during mode init */
  850. gen_chan_info = ee->ee_pwr_cal_b;
  851. break;
  852. case AR5K_EEPROM_MODE_11G:
  853. offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
  854. if (AR5K_EEPROM_HDR_11A(ee->ee_header))
  855. offset += AR5K_EEPROM_GROUP4_OFFSET;
  856. else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
  857. offset += AR5K_EEPROM_GROUP2_OFFSET;
  858. /* NB: frequency piers parsed during mode init */
  859. gen_chan_info = ee->ee_pwr_cal_g;
  860. break;
  861. default:
  862. return -EINVAL;
  863. }
  864. for (i = 0; i < ee->ee_n_piers[mode]; i++) {
  865. chan_pcal_info = &gen_chan_info[i].rf5112_info;
  866. /* Power values in quarter dB
  867. * for the lower xpd gain curve
  868. * (0 dBm -> higher output power) */
  869. for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
  870. AR5K_EEPROM_READ(offset++, val);
  871. chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff);
  872. chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff);
  873. }
  874. /* PCDAC steps
  875. * corresponding to the above power
  876. * measurements */
  877. AR5K_EEPROM_READ(offset++, val);
  878. chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
  879. chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
  880. chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
  881. /* Power values in quarter dB
  882. * for the higher xpd gain curve
  883. * (18 dBm -> lower output power) */
  884. AR5K_EEPROM_READ(offset++, val);
  885. chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff);
  886. chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff);
  887. AR5K_EEPROM_READ(offset++, val);
  888. chan_pcal_info->pwr_x3[2] = (val & 0xff);
  889. /* PCDAC steps
  890. * corresponding to the above power
  891. * measurements (fixed) */
  892. chan_pcal_info->pcdac_x3[0] = 20;
  893. chan_pcal_info->pcdac_x3[1] = 35;
  894. chan_pcal_info->pcdac_x3[2] = 63;
  895. if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
  896. chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f);
  897. /* Last xpd0 power level is also channel maximum */
  898. gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
  899. } else {
  900. chan_pcal_info->pcdac_x0[0] = 1;
  901. gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff);
  902. }
  903. }
  904. return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
  905. }
  906. /*
  907. * Read power calibration for RF2413 chips
  908. *
  909. * For RF2413 we have a Power to PDDAC table (Power Detector)
  910. * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
  911. * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y
  912. * axis and looks like an exponential function like the RF5111 curve.
  913. *
  914. * To recreate the curves we read here the points and interpolate
  915. * later. Note that in most cases only 2 (higher and lower) curves are
  916. * used (like RF5112) but vendors have the oportunity to include all
  917. * 4 curves on eeprom. The final curve (higher power) has an extra
  918. * point for better accuracy like RF5112.
  919. */
  920. /* For RF2413 power calibration data doesn't start on a fixed location and
  921. * if a mode is not supported, it's section is missing -not zeroed-.
  922. * So we need to calculate the starting offset for each section by using
  923. * these two functions */
  924. /* Return the size of each section based on the mode and the number of pd
  925. * gains available (maximum 4). */
  926. static inline unsigned int
  927. ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
  928. {
  929. static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
  930. unsigned int sz;
  931. sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
  932. sz *= ee->ee_n_piers[mode];
  933. return sz;
  934. }
  935. /* Return the starting offset for a section based on the modes supported
  936. * and each section's size. */
  937. static unsigned int
  938. ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
  939. {
  940. u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
  941. switch(mode) {
  942. case AR5K_EEPROM_MODE_11G:
  943. if (AR5K_EEPROM_HDR_11B(ee->ee_header))
  944. offset += ath5k_pdgains_size_2413(ee,
  945. AR5K_EEPROM_MODE_11B) +
  946. AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
  947. /* fall through */
  948. case AR5K_EEPROM_MODE_11B:
  949. if (AR5K_EEPROM_HDR_11A(ee->ee_header))
  950. offset += ath5k_pdgains_size_2413(ee,
  951. AR5K_EEPROM_MODE_11A) +
  952. AR5K_EEPROM_N_5GHZ_CHAN / 2;
  953. /* fall through */
  954. case AR5K_EEPROM_MODE_11A:
  955. break;
  956. default:
  957. break;
  958. }
  959. return offset;
  960. }
  961. /* Convert RF2413 specific data to generic raw data
  962. * used by interpolation code */
  963. static int
  964. ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
  965. struct ath5k_chan_pcal_info *chinfo)
  966. {
  967. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  968. struct ath5k_chan_pcal_info_rf2413 *pcinfo;
  969. u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
  970. unsigned int pier, pdg, point;
  971. /* Fill raw data for each calibration pier */
  972. for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
  973. pcinfo = &chinfo[pier].rf2413_info;
  974. /* Allocate pd_curves for this cal pier */
  975. chinfo[pier].pd_curves =
  976. kcalloc(AR5K_EEPROM_N_PD_CURVES,
  977. sizeof(struct ath5k_pdgain_info),
  978. GFP_KERNEL);
  979. if (!chinfo[pier].pd_curves)
  980. return -ENOMEM;
  981. /* Fill pd_curves */
  982. for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
  983. u8 idx = pdgain_idx[pdg];
  984. struct ath5k_pdgain_info *pd =
  985. &chinfo[pier].pd_curves[idx];
  986. /* One more point for the highest power
  987. * curve (lowest gain) */
  988. if (pdg == ee->ee_pd_gains[mode] - 1)
  989. pd->pd_points = AR5K_EEPROM_N_PD_POINTS;
  990. else
  991. pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1;
  992. /* Allocate pd points for this curve */
  993. pd->pd_step = kcalloc(pd->pd_points,
  994. sizeof(u8), GFP_KERNEL);
  995. if (!pd->pd_step)
  996. return -ENOMEM;
  997. pd->pd_pwr = kcalloc(pd->pd_points,
  998. sizeof(s16), GFP_KERNEL);
  999. if (!pd->pd_pwr)
  1000. return -ENOMEM;
  1001. /* Fill raw dataset
  1002. * convert all pwr levels to
  1003. * quarter dB for RF5112 combatibility */
  1004. pd->pd_step[0] = pcinfo->pddac_i[pdg];
  1005. pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
  1006. for (point = 1; point < pd->pd_points; point++) {
  1007. pd->pd_pwr[point] = pd->pd_pwr[point - 1] +
  1008. 2 * pcinfo->pwr[pdg][point - 1];
  1009. pd->pd_step[point] = pd->pd_step[point - 1] +
  1010. pcinfo->pddac[pdg][point - 1];
  1011. }
  1012. /* Highest gain curve -> min power */
  1013. if (pdg == 0)
  1014. chinfo[pier].min_pwr = pd->pd_pwr[0];
  1015. /* Lowest gain curve -> max power */
  1016. if (pdg == ee->ee_pd_gains[mode] - 1)
  1017. chinfo[pier].max_pwr =
  1018. pd->pd_pwr[pd->pd_points - 1];
  1019. }
  1020. }
  1021. return 0;
  1022. }
  1023. /* Parse EEPROM data */
  1024. static int
  1025. ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
  1026. {
  1027. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1028. struct ath5k_chan_pcal_info_rf2413 *pcinfo;
  1029. struct ath5k_chan_pcal_info *chinfo;
  1030. u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
  1031. u32 offset;
  1032. int idx, i, ret;
  1033. u16 val;
  1034. u8 pd_gains = 0;
  1035. /* Count how many curves we have and
  1036. * identify them (which one of the 4
  1037. * available curves we have on each count).
  1038. * Curves are stored from higher to
  1039. * lower gain so we go backwards */
  1040. for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) {
  1041. /* ee_x_gain[mode] is x gain mask */
  1042. if ((ee->ee_x_gain[mode] >> idx) & 0x1)
  1043. pdgain_idx[pd_gains++] = idx;
  1044. }
  1045. ee->ee_pd_gains[mode] = pd_gains;
  1046. if (pd_gains == 0)
  1047. return -EINVAL;
  1048. offset = ath5k_cal_data_offset_2413(ee, mode);
  1049. switch (mode) {
  1050. case AR5K_EEPROM_MODE_11A:
  1051. if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
  1052. return 0;
  1053. ath5k_eeprom_init_11a_pcal_freq(ah, offset);
  1054. offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
  1055. chinfo = ee->ee_pwr_cal_a;
  1056. break;
  1057. case AR5K_EEPROM_MODE_11B:
  1058. if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
  1059. return 0;
  1060. ath5k_eeprom_init_11bg_2413(ah, mode, offset);
  1061. offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
  1062. chinfo = ee->ee_pwr_cal_b;
  1063. break;
  1064. case AR5K_EEPROM_MODE_11G:
  1065. if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
  1066. return 0;
  1067. ath5k_eeprom_init_11bg_2413(ah, mode, offset);
  1068. offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
  1069. chinfo = ee->ee_pwr_cal_g;
  1070. break;
  1071. default:
  1072. return -EINVAL;
  1073. }
  1074. for (i = 0; i < ee->ee_n_piers[mode]; i++) {
  1075. pcinfo = &chinfo[i].rf2413_info;
  1076. /*
  1077. * Read pwr_i, pddac_i and the first
  1078. * 2 pd points (pwr, pddac)
  1079. */
  1080. AR5K_EEPROM_READ(offset++, val);
  1081. pcinfo->pwr_i[0] = val & 0x1f;
  1082. pcinfo->pddac_i[0] = (val >> 5) & 0x7f;
  1083. pcinfo->pwr[0][0] = (val >> 12) & 0xf;
  1084. AR5K_EEPROM_READ(offset++, val);
  1085. pcinfo->pddac[0][0] = val & 0x3f;
  1086. pcinfo->pwr[0][1] = (val >> 6) & 0xf;
  1087. pcinfo->pddac[0][1] = (val >> 10) & 0x3f;
  1088. AR5K_EEPROM_READ(offset++, val);
  1089. pcinfo->pwr[0][2] = val & 0xf;
  1090. pcinfo->pddac[0][2] = (val >> 4) & 0x3f;
  1091. pcinfo->pwr[0][3] = 0;
  1092. pcinfo->pddac[0][3] = 0;
  1093. if (pd_gains > 1) {
  1094. /*
  1095. * Pd gain 0 is not the last pd gain
  1096. * so it only has 2 pd points.
  1097. * Continue wih pd gain 1.
  1098. */
  1099. pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
  1100. pcinfo->pddac_i[1] = (val >> 15) & 0x1;
  1101. AR5K_EEPROM_READ(offset++, val);
  1102. pcinfo->pddac_i[1] |= (val & 0x3F) << 1;
  1103. pcinfo->pwr[1][0] = (val >> 6) & 0xf;
  1104. pcinfo->pddac[1][0] = (val >> 10) & 0x3f;
  1105. AR5K_EEPROM_READ(offset++, val);
  1106. pcinfo->pwr[1][1] = val & 0xf;
  1107. pcinfo->pddac[1][1] = (val >> 4) & 0x3f;
  1108. pcinfo->pwr[1][2] = (val >> 10) & 0xf;
  1109. pcinfo->pddac[1][2] = (val >> 14) & 0x3;
  1110. AR5K_EEPROM_READ(offset++, val);
  1111. pcinfo->pddac[1][2] |= (val & 0xF) << 2;
  1112. pcinfo->pwr[1][3] = 0;
  1113. pcinfo->pddac[1][3] = 0;
  1114. } else if (pd_gains == 1) {
  1115. /*
  1116. * Pd gain 0 is the last one so
  1117. * read the extra point.
  1118. */
  1119. pcinfo->pwr[0][3] = (val >> 10) & 0xf;
  1120. pcinfo->pddac[0][3] = (val >> 14) & 0x3;
  1121. AR5K_EEPROM_READ(offset++, val);
  1122. pcinfo->pddac[0][3] |= (val & 0xF) << 2;
  1123. }
  1124. /*
  1125. * Proceed with the other pd_gains
  1126. * as above.
  1127. */
  1128. if (pd_gains > 2) {
  1129. pcinfo->pwr_i[2] = (val >> 4) & 0x1f;
  1130. pcinfo->pddac_i[2] = (val >> 9) & 0x7f;
  1131. AR5K_EEPROM_READ(offset++, val);
  1132. pcinfo->pwr[2][0] = (val >> 0) & 0xf;
  1133. pcinfo->pddac[2][0] = (val >> 4) & 0x3f;
  1134. pcinfo->pwr[2][1] = (val >> 10) & 0xf;
  1135. pcinfo->pddac[2][1] = (val >> 14) & 0x3;
  1136. AR5K_EEPROM_READ(offset++, val);
  1137. pcinfo->pddac[2][1] |= (val & 0xF) << 2;
  1138. pcinfo->pwr[2][2] = (val >> 4) & 0xf;
  1139. pcinfo->pddac[2][2] = (val >> 8) & 0x3f;
  1140. pcinfo->pwr[2][3] = 0;
  1141. pcinfo->pddac[2][3] = 0;
  1142. } else if (pd_gains == 2) {
  1143. pcinfo->pwr[1][3] = (val >> 4) & 0xf;
  1144. pcinfo->pddac[1][3] = (val >> 8) & 0x3f;
  1145. }
  1146. if (pd_gains > 3) {
  1147. pcinfo->pwr_i[3] = (val >> 14) & 0x3;
  1148. AR5K_EEPROM_READ(offset++, val);
  1149. pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
  1150. pcinfo->pddac_i[3] = (val >> 3) & 0x7f;
  1151. pcinfo->pwr[3][0] = (val >> 10) & 0xf;
  1152. pcinfo->pddac[3][0] = (val >> 14) & 0x3;
  1153. AR5K_EEPROM_READ(offset++, val);
  1154. pcinfo->pddac[3][0] |= (val & 0xF) << 2;
  1155. pcinfo->pwr[3][1] = (val >> 4) & 0xf;
  1156. pcinfo->pddac[3][1] = (val >> 8) & 0x3f;
  1157. pcinfo->pwr[3][2] = (val >> 14) & 0x3;
  1158. AR5K_EEPROM_READ(offset++, val);
  1159. pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2;
  1160. pcinfo->pddac[3][2] = (val >> 2) & 0x3f;
  1161. pcinfo->pwr[3][3] = (val >> 8) & 0xf;
  1162. pcinfo->pddac[3][3] = (val >> 12) & 0xF;
  1163. AR5K_EEPROM_READ(offset++, val);
  1164. pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4;
  1165. } else if (pd_gains == 3) {
  1166. pcinfo->pwr[2][3] = (val >> 14) & 0x3;
  1167. AR5K_EEPROM_READ(offset++, val);
  1168. pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2;
  1169. pcinfo->pddac[2][3] = (val >> 2) & 0x3f;
  1170. }
  1171. }
  1172. return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
  1173. }
  1174. /*
  1175. * Read per rate target power (this is the maximum tx power
  1176. * supported by the card). This info is used when setting
  1177. * tx power, no matter the channel.
  1178. *
  1179. * This also works for v5 EEPROMs.
  1180. */
  1181. static int
  1182. ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
  1183. {
  1184. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1185. struct ath5k_rate_pcal_info *rate_pcal_info;
  1186. u8 *rate_target_pwr_num;
  1187. u32 offset;
  1188. u16 val;
  1189. int ret, i;
  1190. offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
  1191. rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
  1192. switch (mode) {
  1193. case AR5K_EEPROM_MODE_11A:
  1194. offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
  1195. rate_pcal_info = ee->ee_rate_tpwr_a;
  1196. ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
  1197. break;
  1198. case AR5K_EEPROM_MODE_11B:
  1199. offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
  1200. rate_pcal_info = ee->ee_rate_tpwr_b;
  1201. ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
  1202. break;
  1203. case AR5K_EEPROM_MODE_11G:
  1204. offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
  1205. rate_pcal_info = ee->ee_rate_tpwr_g;
  1206. ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
  1207. break;
  1208. default:
  1209. return -EINVAL;
  1210. }
  1211. /* Different freq mask for older eeproms (<= v3.2) */
  1212. if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
  1213. for (i = 0; i < (*rate_target_pwr_num); i++) {
  1214. AR5K_EEPROM_READ(offset++, val);
  1215. rate_pcal_info[i].freq =
  1216. ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
  1217. rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
  1218. rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
  1219. AR5K_EEPROM_READ(offset++, val);
  1220. if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
  1221. val == 0) {
  1222. (*rate_target_pwr_num) = i;
  1223. break;
  1224. }
  1225. rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
  1226. rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
  1227. rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
  1228. }
  1229. } else {
  1230. for (i = 0; i < (*rate_target_pwr_num); i++) {
  1231. AR5K_EEPROM_READ(offset++, val);
  1232. rate_pcal_info[i].freq =
  1233. ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
  1234. rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
  1235. rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
  1236. AR5K_EEPROM_READ(offset++, val);
  1237. if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
  1238. val == 0) {
  1239. (*rate_target_pwr_num) = i;
  1240. break;
  1241. }
  1242. rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
  1243. rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
  1244. rate_pcal_info[i].target_power_54 = (val & 0x3f);
  1245. }
  1246. }
  1247. return 0;
  1248. }
  1249. /*
  1250. * Read per channel calibration info from EEPROM
  1251. *
  1252. * This info is used to calibrate the baseband power table. Imagine
  1253. * that for each channel there is a power curve that's hw specific
  1254. * (depends on amplifier etc) and we try to "correct" this curve using
  1255. * offsets we pass on to phy chip (baseband -> before amplifier) so that
  1256. * it can use accurate power values when setting tx power (takes amplifier's
  1257. * performance on each channel into account).
  1258. *
  1259. * EEPROM provides us with the offsets for some pre-calibrated channels
  1260. * and we have to interpolate to create the full table for these channels and
  1261. * also the table for any channel.
  1262. */
  1263. static int
  1264. ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
  1265. {
  1266. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1267. int (*read_pcal)(struct ath5k_hw *hw, int mode);
  1268. int mode;
  1269. int err;
  1270. if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
  1271. (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
  1272. read_pcal = ath5k_eeprom_read_pcal_info_5112;
  1273. else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
  1274. (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
  1275. read_pcal = ath5k_eeprom_read_pcal_info_2413;
  1276. else
  1277. read_pcal = ath5k_eeprom_read_pcal_info_5111;
  1278. for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
  1279. mode++) {
  1280. err = read_pcal(ah, mode);
  1281. if (err)
  1282. return err;
  1283. err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
  1284. if (err < 0)
  1285. return err;
  1286. }
  1287. return 0;
  1288. }
  1289. static int
  1290. ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
  1291. {
  1292. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1293. struct ath5k_chan_pcal_info *chinfo;
  1294. u8 pier, pdg;
  1295. switch (mode) {
  1296. case AR5K_EEPROM_MODE_11A:
  1297. if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
  1298. return 0;
  1299. chinfo = ee->ee_pwr_cal_a;
  1300. break;
  1301. case AR5K_EEPROM_MODE_11B:
  1302. if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
  1303. return 0;
  1304. chinfo = ee->ee_pwr_cal_b;
  1305. break;
  1306. case AR5K_EEPROM_MODE_11G:
  1307. if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
  1308. return 0;
  1309. chinfo = ee->ee_pwr_cal_g;
  1310. break;
  1311. default:
  1312. return -EINVAL;
  1313. }
  1314. for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
  1315. if (!chinfo[pier].pd_curves)
  1316. continue;
  1317. for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
  1318. struct ath5k_pdgain_info *pd =
  1319. &chinfo[pier].pd_curves[pdg];
  1320. if (pd != NULL) {
  1321. kfree(pd->pd_step);
  1322. kfree(pd->pd_pwr);
  1323. }
  1324. }
  1325. kfree(chinfo[pier].pd_curves);
  1326. }
  1327. return 0;
  1328. }
  1329. void
  1330. ath5k_eeprom_detach(struct ath5k_hw *ah)
  1331. {
  1332. u8 mode;
  1333. for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
  1334. ath5k_eeprom_free_pcal_info(ah, mode);
  1335. }
  1336. /* Read conformance test limits used for regulatory control */
  1337. static int
  1338. ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
  1339. {
  1340. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1341. struct ath5k_edge_power *rep;
  1342. unsigned int fmask, pmask;
  1343. unsigned int ctl_mode;
  1344. int ret, i, j;
  1345. u32 offset;
  1346. u16 val;
  1347. pmask = AR5K_EEPROM_POWER_M;
  1348. fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
  1349. offset = AR5K_EEPROM_CTL(ee->ee_version);
  1350. ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
  1351. for (i = 0; i < ee->ee_ctls; i += 2) {
  1352. AR5K_EEPROM_READ(offset++, val);
  1353. ee->ee_ctl[i] = (val >> 8) & 0xff;
  1354. ee->ee_ctl[i + 1] = val & 0xff;
  1355. }
  1356. offset = AR5K_EEPROM_GROUP8_OFFSET;
  1357. if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
  1358. offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
  1359. AR5K_EEPROM_GROUP5_OFFSET;
  1360. else
  1361. offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
  1362. rep = ee->ee_ctl_pwr;
  1363. for(i = 0; i < ee->ee_ctls; i++) {
  1364. switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
  1365. case AR5K_CTL_11A:
  1366. case AR5K_CTL_TURBO:
  1367. ctl_mode = AR5K_EEPROM_MODE_11A;
  1368. break;
  1369. default:
  1370. ctl_mode = AR5K_EEPROM_MODE_11G;
  1371. break;
  1372. }
  1373. if (ee->ee_ctl[i] == 0) {
  1374. if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
  1375. offset += 8;
  1376. else
  1377. offset += 7;
  1378. rep += AR5K_EEPROM_N_EDGES;
  1379. continue;
  1380. }
  1381. if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
  1382. for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
  1383. AR5K_EEPROM_READ(offset++, val);
  1384. rep[j].freq = (val >> 8) & fmask;
  1385. rep[j + 1].freq = val & fmask;
  1386. }
  1387. for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
  1388. AR5K_EEPROM_READ(offset++, val);
  1389. rep[j].edge = (val >> 8) & pmask;
  1390. rep[j].flag = (val >> 14) & 1;
  1391. rep[j + 1].edge = val & pmask;
  1392. rep[j + 1].flag = (val >> 6) & 1;
  1393. }
  1394. } else {
  1395. AR5K_EEPROM_READ(offset++, val);
  1396. rep[0].freq = (val >> 9) & fmask;
  1397. rep[1].freq = (val >> 2) & fmask;
  1398. rep[2].freq = (val << 5) & fmask;
  1399. AR5K_EEPROM_READ(offset++, val);
  1400. rep[2].freq |= (val >> 11) & 0x1f;
  1401. rep[3].freq = (val >> 4) & fmask;
  1402. rep[4].freq = (val << 3) & fmask;
  1403. AR5K_EEPROM_READ(offset++, val);
  1404. rep[4].freq |= (val >> 13) & 0x7;
  1405. rep[5].freq = (val >> 6) & fmask;
  1406. rep[6].freq = (val << 1) & fmask;
  1407. AR5K_EEPROM_READ(offset++, val);
  1408. rep[6].freq |= (val >> 15) & 0x1;
  1409. rep[7].freq = (val >> 8) & fmask;
  1410. rep[0].edge = (val >> 2) & pmask;
  1411. rep[1].edge = (val << 4) & pmask;
  1412. AR5K_EEPROM_READ(offset++, val);
  1413. rep[1].edge |= (val >> 12) & 0xf;
  1414. rep[2].edge = (val >> 6) & pmask;
  1415. rep[3].edge = val & pmask;
  1416. AR5K_EEPROM_READ(offset++, val);
  1417. rep[4].edge = (val >> 10) & pmask;
  1418. rep[5].edge = (val >> 4) & pmask;
  1419. rep[6].edge = (val << 2) & pmask;
  1420. AR5K_EEPROM_READ(offset++, val);
  1421. rep[6].edge |= (val >> 14) & 0x3;
  1422. rep[7].edge = (val >> 8) & pmask;
  1423. }
  1424. for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
  1425. rep[j].freq = ath5k_eeprom_bin2freq(ee,
  1426. rep[j].freq, ctl_mode);
  1427. }
  1428. rep += AR5K_EEPROM_N_EDGES;
  1429. }
  1430. return 0;
  1431. }
  1432. static int
  1433. ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
  1434. {
  1435. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1436. u32 offset;
  1437. u16 val;
  1438. int ret = 0, i;
  1439. offset = AR5K_EEPROM_CTL(ee->ee_version) +
  1440. AR5K_EEPROM_N_CTLS(ee->ee_version);
  1441. if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
  1442. /* No spur info for 5GHz */
  1443. ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
  1444. /* 2 channels for 2GHz (2464/2420) */
  1445. ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
  1446. ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
  1447. ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
  1448. } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
  1449. for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
  1450. AR5K_EEPROM_READ(offset, val);
  1451. ee->ee_spur_chans[i][0] = val;
  1452. AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS,
  1453. val);
  1454. ee->ee_spur_chans[i][1] = val;
  1455. offset++;
  1456. }
  1457. }
  1458. return ret;
  1459. }
  1460. /*
  1461. * Initialize eeprom data structure
  1462. */
  1463. int
  1464. ath5k_eeprom_init(struct ath5k_hw *ah)
  1465. {
  1466. int err;
  1467. err = ath5k_eeprom_init_header(ah);
  1468. if (err < 0)
  1469. return err;
  1470. err = ath5k_eeprom_init_modes(ah);
  1471. if (err < 0)
  1472. return err;
  1473. err = ath5k_eeprom_read_pcal_info(ah);
  1474. if (err < 0)
  1475. return err;
  1476. err = ath5k_eeprom_read_ctl_info(ah);
  1477. if (err < 0)
  1478. return err;
  1479. err = ath5k_eeprom_read_spur_chans(ah);
  1480. if (err < 0)
  1481. return err;
  1482. return 0;
  1483. }
  1484. /*
  1485. * Read the MAC address from eeprom
  1486. */
  1487. int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
  1488. {
  1489. u8 mac_d[ETH_ALEN] = {};
  1490. u32 total, offset;
  1491. u16 data;
  1492. int octet, ret;
  1493. ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
  1494. if (ret)
  1495. return ret;
  1496. for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
  1497. ret = ath5k_hw_eeprom_read(ah, offset, &data);
  1498. if (ret)
  1499. return ret;
  1500. total += data;
  1501. mac_d[octet + 1] = data & 0xff;
  1502. mac_d[octet] = data >> 8;
  1503. octet += 2;
  1504. }
  1505. if (!total || total == 3 * 0xffff)
  1506. return -EINVAL;
  1507. memcpy(mac, mac_d, ETH_ALEN);
  1508. return 0;
  1509. }