cnic.c 120 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x_reg.h"
  40. #include "bnx2x_fw_defs.h"
  41. #include "bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. static LIST_HEAD(cnic_dev_list);
  55. static DEFINE_RWLOCK(cnic_dev_lock);
  56. static DEFINE_MUTEX(cnic_lock);
  57. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  58. static int cnic_service_bnx2(void *, void *);
  59. static int cnic_service_bnx2x(void *, void *);
  60. static int cnic_ctl(void *, struct cnic_ctl_info *);
  61. static struct cnic_ops cnic_bnx2_ops = {
  62. .cnic_owner = THIS_MODULE,
  63. .cnic_handler = cnic_service_bnx2,
  64. .cnic_ctl = cnic_ctl,
  65. };
  66. static struct cnic_ops cnic_bnx2x_ops = {
  67. .cnic_owner = THIS_MODULE,
  68. .cnic_handler = cnic_service_bnx2x,
  69. .cnic_ctl = cnic_ctl,
  70. };
  71. static void cnic_shutdown_rings(struct cnic_dev *);
  72. static void cnic_init_rings(struct cnic_dev *);
  73. static int cnic_cm_set_pg(struct cnic_sock *);
  74. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  75. {
  76. struct cnic_dev *dev = uinfo->priv;
  77. struct cnic_local *cp = dev->cnic_priv;
  78. if (!capable(CAP_NET_ADMIN))
  79. return -EPERM;
  80. if (cp->uio_dev != -1)
  81. return -EBUSY;
  82. rtnl_lock();
  83. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  84. rtnl_unlock();
  85. return -ENODEV;
  86. }
  87. cp->uio_dev = iminor(inode);
  88. cnic_init_rings(dev);
  89. rtnl_unlock();
  90. return 0;
  91. }
  92. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  93. {
  94. struct cnic_dev *dev = uinfo->priv;
  95. struct cnic_local *cp = dev->cnic_priv;
  96. cnic_shutdown_rings(dev);
  97. cp->uio_dev = -1;
  98. return 0;
  99. }
  100. static inline void cnic_hold(struct cnic_dev *dev)
  101. {
  102. atomic_inc(&dev->ref_count);
  103. }
  104. static inline void cnic_put(struct cnic_dev *dev)
  105. {
  106. atomic_dec(&dev->ref_count);
  107. }
  108. static inline void csk_hold(struct cnic_sock *csk)
  109. {
  110. atomic_inc(&csk->ref_count);
  111. }
  112. static inline void csk_put(struct cnic_sock *csk)
  113. {
  114. atomic_dec(&csk->ref_count);
  115. }
  116. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  117. {
  118. struct cnic_dev *cdev;
  119. read_lock(&cnic_dev_lock);
  120. list_for_each_entry(cdev, &cnic_dev_list, list) {
  121. if (netdev == cdev->netdev) {
  122. cnic_hold(cdev);
  123. read_unlock(&cnic_dev_lock);
  124. return cdev;
  125. }
  126. }
  127. read_unlock(&cnic_dev_lock);
  128. return NULL;
  129. }
  130. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  131. {
  132. atomic_inc(&ulp_ops->ref_count);
  133. }
  134. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  135. {
  136. atomic_dec(&ulp_ops->ref_count);
  137. }
  138. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  139. {
  140. struct cnic_local *cp = dev->cnic_priv;
  141. struct cnic_eth_dev *ethdev = cp->ethdev;
  142. struct drv_ctl_info info;
  143. struct drv_ctl_io *io = &info.data.io;
  144. info.cmd = DRV_CTL_CTX_WR_CMD;
  145. io->cid_addr = cid_addr;
  146. io->offset = off;
  147. io->data = val;
  148. ethdev->drv_ctl(dev->netdev, &info);
  149. }
  150. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  157. io->offset = off;
  158. io->dma_addr = addr;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  162. {
  163. struct cnic_local *cp = dev->cnic_priv;
  164. struct cnic_eth_dev *ethdev = cp->ethdev;
  165. struct drv_ctl_info info;
  166. struct drv_ctl_l2_ring *ring = &info.data.ring;
  167. if (start)
  168. info.cmd = DRV_CTL_START_L2_CMD;
  169. else
  170. info.cmd = DRV_CTL_STOP_L2_CMD;
  171. ring->cid = cid;
  172. ring->client_id = cl_id;
  173. ethdev->drv_ctl(dev->netdev, &info);
  174. }
  175. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  176. {
  177. struct cnic_local *cp = dev->cnic_priv;
  178. struct cnic_eth_dev *ethdev = cp->ethdev;
  179. struct drv_ctl_info info;
  180. struct drv_ctl_io *io = &info.data.io;
  181. info.cmd = DRV_CTL_IO_WR_CMD;
  182. io->offset = off;
  183. io->data = val;
  184. ethdev->drv_ctl(dev->netdev, &info);
  185. }
  186. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  187. {
  188. struct cnic_local *cp = dev->cnic_priv;
  189. struct cnic_eth_dev *ethdev = cp->ethdev;
  190. struct drv_ctl_info info;
  191. struct drv_ctl_io *io = &info.data.io;
  192. info.cmd = DRV_CTL_IO_RD_CMD;
  193. io->offset = off;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. return io->data;
  196. }
  197. static int cnic_in_use(struct cnic_sock *csk)
  198. {
  199. return test_bit(SK_F_INUSE, &csk->flags);
  200. }
  201. static void cnic_kwq_completion(struct cnic_dev *dev, u32 count)
  202. {
  203. struct cnic_local *cp = dev->cnic_priv;
  204. struct cnic_eth_dev *ethdev = cp->ethdev;
  205. struct drv_ctl_info info;
  206. info.cmd = DRV_CTL_COMPLETION_CMD;
  207. info.data.comp.comp_count = count;
  208. ethdev->drv_ctl(dev->netdev, &info);
  209. }
  210. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  211. {
  212. u32 i;
  213. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  214. if (cp->ctx_tbl[i].cid == cid) {
  215. *l5_cid = i;
  216. return 0;
  217. }
  218. }
  219. return -EINVAL;
  220. }
  221. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  222. struct cnic_sock *csk)
  223. {
  224. struct iscsi_path path_req;
  225. char *buf = NULL;
  226. u16 len = 0;
  227. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  228. struct cnic_ulp_ops *ulp_ops;
  229. if (cp->uio_dev == -1)
  230. return -ENODEV;
  231. if (csk) {
  232. len = sizeof(path_req);
  233. buf = (char *) &path_req;
  234. memset(&path_req, 0, len);
  235. msg_type = ISCSI_KEVENT_PATH_REQ;
  236. path_req.handle = (u64) csk->l5_cid;
  237. if (test_bit(SK_F_IPV6, &csk->flags)) {
  238. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  239. sizeof(struct in6_addr));
  240. path_req.ip_addr_len = 16;
  241. } else {
  242. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  243. sizeof(struct in_addr));
  244. path_req.ip_addr_len = 4;
  245. }
  246. path_req.vlan_id = csk->vlan_id;
  247. path_req.pmtu = csk->mtu;
  248. }
  249. rcu_read_lock();
  250. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  251. if (ulp_ops)
  252. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  253. rcu_read_unlock();
  254. return 0;
  255. }
  256. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  257. char *buf, u16 len)
  258. {
  259. int rc = -EINVAL;
  260. switch (msg_type) {
  261. case ISCSI_UEVENT_PATH_UPDATE: {
  262. struct cnic_local *cp;
  263. u32 l5_cid;
  264. struct cnic_sock *csk;
  265. struct iscsi_path *path_resp;
  266. if (len < sizeof(*path_resp))
  267. break;
  268. path_resp = (struct iscsi_path *) buf;
  269. cp = dev->cnic_priv;
  270. l5_cid = (u32) path_resp->handle;
  271. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  272. break;
  273. rcu_read_lock();
  274. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  275. rc = -ENODEV;
  276. rcu_read_unlock();
  277. break;
  278. }
  279. csk = &cp->csk_tbl[l5_cid];
  280. csk_hold(csk);
  281. if (cnic_in_use(csk)) {
  282. memcpy(csk->ha, path_resp->mac_addr, 6);
  283. if (test_bit(SK_F_IPV6, &csk->flags))
  284. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  285. sizeof(struct in6_addr));
  286. else
  287. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  288. sizeof(struct in_addr));
  289. if (is_valid_ether_addr(csk->ha))
  290. cnic_cm_set_pg(csk);
  291. }
  292. csk_put(csk);
  293. rcu_read_unlock();
  294. rc = 0;
  295. }
  296. }
  297. return rc;
  298. }
  299. static int cnic_offld_prep(struct cnic_sock *csk)
  300. {
  301. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  302. return 0;
  303. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  304. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  305. return 0;
  306. }
  307. return 1;
  308. }
  309. static int cnic_close_prep(struct cnic_sock *csk)
  310. {
  311. clear_bit(SK_F_CONNECT_START, &csk->flags);
  312. smp_mb__after_clear_bit();
  313. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  314. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  315. msleep(1);
  316. return 1;
  317. }
  318. return 0;
  319. }
  320. static int cnic_abort_prep(struct cnic_sock *csk)
  321. {
  322. clear_bit(SK_F_CONNECT_START, &csk->flags);
  323. smp_mb__after_clear_bit();
  324. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  325. msleep(1);
  326. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  327. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  328. return 1;
  329. }
  330. return 0;
  331. }
  332. static void cnic_uio_stop(void)
  333. {
  334. struct cnic_dev *dev;
  335. read_lock(&cnic_dev_lock);
  336. list_for_each_entry(dev, &cnic_dev_list, list) {
  337. struct cnic_local *cp = dev->cnic_priv;
  338. if (cp->cnic_uinfo)
  339. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  340. }
  341. read_unlock(&cnic_dev_lock);
  342. }
  343. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  344. {
  345. struct cnic_dev *dev;
  346. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  347. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  348. return -EINVAL;
  349. }
  350. mutex_lock(&cnic_lock);
  351. if (cnic_ulp_tbl[ulp_type]) {
  352. pr_err("%s: Type %d has already been registered\n",
  353. __func__, ulp_type);
  354. mutex_unlock(&cnic_lock);
  355. return -EBUSY;
  356. }
  357. read_lock(&cnic_dev_lock);
  358. list_for_each_entry(dev, &cnic_dev_list, list) {
  359. struct cnic_local *cp = dev->cnic_priv;
  360. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  361. }
  362. read_unlock(&cnic_dev_lock);
  363. atomic_set(&ulp_ops->ref_count, 0);
  364. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  365. mutex_unlock(&cnic_lock);
  366. /* Prevent race conditions with netdev_event */
  367. rtnl_lock();
  368. read_lock(&cnic_dev_lock);
  369. list_for_each_entry(dev, &cnic_dev_list, list) {
  370. struct cnic_local *cp = dev->cnic_priv;
  371. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  372. ulp_ops->cnic_init(dev);
  373. }
  374. read_unlock(&cnic_dev_lock);
  375. rtnl_unlock();
  376. return 0;
  377. }
  378. int cnic_unregister_driver(int ulp_type)
  379. {
  380. struct cnic_dev *dev;
  381. struct cnic_ulp_ops *ulp_ops;
  382. int i = 0;
  383. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  384. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  385. return -EINVAL;
  386. }
  387. mutex_lock(&cnic_lock);
  388. ulp_ops = cnic_ulp_tbl[ulp_type];
  389. if (!ulp_ops) {
  390. pr_err("%s: Type %d has not been registered\n",
  391. __func__, ulp_type);
  392. goto out_unlock;
  393. }
  394. read_lock(&cnic_dev_lock);
  395. list_for_each_entry(dev, &cnic_dev_list, list) {
  396. struct cnic_local *cp = dev->cnic_priv;
  397. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  398. pr_err("%s: Type %d still has devices registered\n",
  399. __func__, ulp_type);
  400. read_unlock(&cnic_dev_lock);
  401. goto out_unlock;
  402. }
  403. }
  404. read_unlock(&cnic_dev_lock);
  405. if (ulp_type == CNIC_ULP_ISCSI)
  406. cnic_uio_stop();
  407. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  408. mutex_unlock(&cnic_lock);
  409. synchronize_rcu();
  410. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  411. msleep(100);
  412. i++;
  413. }
  414. if (atomic_read(&ulp_ops->ref_count) != 0)
  415. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  416. return 0;
  417. out_unlock:
  418. mutex_unlock(&cnic_lock);
  419. return -EINVAL;
  420. }
  421. static int cnic_start_hw(struct cnic_dev *);
  422. static void cnic_stop_hw(struct cnic_dev *);
  423. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  424. void *ulp_ctx)
  425. {
  426. struct cnic_local *cp = dev->cnic_priv;
  427. struct cnic_ulp_ops *ulp_ops;
  428. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  429. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  430. return -EINVAL;
  431. }
  432. mutex_lock(&cnic_lock);
  433. if (cnic_ulp_tbl[ulp_type] == NULL) {
  434. pr_err("%s: Driver with type %d has not been registered\n",
  435. __func__, ulp_type);
  436. mutex_unlock(&cnic_lock);
  437. return -EAGAIN;
  438. }
  439. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  440. pr_err("%s: Type %d has already been registered to this device\n",
  441. __func__, ulp_type);
  442. mutex_unlock(&cnic_lock);
  443. return -EBUSY;
  444. }
  445. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  446. cp->ulp_handle[ulp_type] = ulp_ctx;
  447. ulp_ops = cnic_ulp_tbl[ulp_type];
  448. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  449. cnic_hold(dev);
  450. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  451. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  452. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  453. mutex_unlock(&cnic_lock);
  454. return 0;
  455. }
  456. EXPORT_SYMBOL(cnic_register_driver);
  457. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  458. {
  459. struct cnic_local *cp = dev->cnic_priv;
  460. int i = 0;
  461. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  462. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  463. return -EINVAL;
  464. }
  465. mutex_lock(&cnic_lock);
  466. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  467. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  468. cnic_put(dev);
  469. } else {
  470. pr_err("%s: device not registered to this ulp type %d\n",
  471. __func__, ulp_type);
  472. mutex_unlock(&cnic_lock);
  473. return -EINVAL;
  474. }
  475. mutex_unlock(&cnic_lock);
  476. synchronize_rcu();
  477. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  478. i < 20) {
  479. msleep(100);
  480. i++;
  481. }
  482. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  483. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  484. return 0;
  485. }
  486. EXPORT_SYMBOL(cnic_unregister_driver);
  487. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  488. {
  489. id_tbl->start = start_id;
  490. id_tbl->max = size;
  491. id_tbl->next = 0;
  492. spin_lock_init(&id_tbl->lock);
  493. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  494. if (!id_tbl->table)
  495. return -ENOMEM;
  496. return 0;
  497. }
  498. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  499. {
  500. kfree(id_tbl->table);
  501. id_tbl->table = NULL;
  502. }
  503. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  504. {
  505. int ret = -1;
  506. id -= id_tbl->start;
  507. if (id >= id_tbl->max)
  508. return ret;
  509. spin_lock(&id_tbl->lock);
  510. if (!test_bit(id, id_tbl->table)) {
  511. set_bit(id, id_tbl->table);
  512. ret = 0;
  513. }
  514. spin_unlock(&id_tbl->lock);
  515. return ret;
  516. }
  517. /* Returns -1 if not successful */
  518. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  519. {
  520. u32 id;
  521. spin_lock(&id_tbl->lock);
  522. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  523. if (id >= id_tbl->max) {
  524. id = -1;
  525. if (id_tbl->next != 0) {
  526. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  527. if (id >= id_tbl->next)
  528. id = -1;
  529. }
  530. }
  531. if (id < id_tbl->max) {
  532. set_bit(id, id_tbl->table);
  533. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  534. id += id_tbl->start;
  535. }
  536. spin_unlock(&id_tbl->lock);
  537. return id;
  538. }
  539. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  540. {
  541. if (id == -1)
  542. return;
  543. id -= id_tbl->start;
  544. if (id >= id_tbl->max)
  545. return;
  546. clear_bit(id, id_tbl->table);
  547. }
  548. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  549. {
  550. int i;
  551. if (!dma->pg_arr)
  552. return;
  553. for (i = 0; i < dma->num_pages; i++) {
  554. if (dma->pg_arr[i]) {
  555. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  556. dma->pg_arr[i], dma->pg_map_arr[i]);
  557. dma->pg_arr[i] = NULL;
  558. }
  559. }
  560. if (dma->pgtbl) {
  561. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  562. dma->pgtbl, dma->pgtbl_map);
  563. dma->pgtbl = NULL;
  564. }
  565. kfree(dma->pg_arr);
  566. dma->pg_arr = NULL;
  567. dma->num_pages = 0;
  568. }
  569. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  570. {
  571. int i;
  572. u32 *page_table = dma->pgtbl;
  573. for (i = 0; i < dma->num_pages; i++) {
  574. /* Each entry needs to be in big endian format. */
  575. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  576. page_table++;
  577. *page_table = (u32) dma->pg_map_arr[i];
  578. page_table++;
  579. }
  580. }
  581. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  582. {
  583. int i;
  584. u32 *page_table = dma->pgtbl;
  585. for (i = 0; i < dma->num_pages; i++) {
  586. /* Each entry needs to be in little endian format. */
  587. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  588. page_table++;
  589. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  590. page_table++;
  591. }
  592. }
  593. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  594. int pages, int use_pg_tbl)
  595. {
  596. int i, size;
  597. struct cnic_local *cp = dev->cnic_priv;
  598. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  599. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  600. if (dma->pg_arr == NULL)
  601. return -ENOMEM;
  602. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  603. dma->num_pages = pages;
  604. for (i = 0; i < pages; i++) {
  605. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  606. BCM_PAGE_SIZE,
  607. &dma->pg_map_arr[i],
  608. GFP_ATOMIC);
  609. if (dma->pg_arr[i] == NULL)
  610. goto error;
  611. }
  612. if (!use_pg_tbl)
  613. return 0;
  614. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  615. ~(BCM_PAGE_SIZE - 1);
  616. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  617. &dma->pgtbl_map, GFP_ATOMIC);
  618. if (dma->pgtbl == NULL)
  619. goto error;
  620. cp->setup_pgtbl(dev, dma);
  621. return 0;
  622. error:
  623. cnic_free_dma(dev, dma);
  624. return -ENOMEM;
  625. }
  626. static void cnic_free_context(struct cnic_dev *dev)
  627. {
  628. struct cnic_local *cp = dev->cnic_priv;
  629. int i;
  630. for (i = 0; i < cp->ctx_blks; i++) {
  631. if (cp->ctx_arr[i].ctx) {
  632. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  633. cp->ctx_arr[i].ctx,
  634. cp->ctx_arr[i].mapping);
  635. cp->ctx_arr[i].ctx = NULL;
  636. }
  637. }
  638. }
  639. static void cnic_free_resc(struct cnic_dev *dev)
  640. {
  641. struct cnic_local *cp = dev->cnic_priv;
  642. int i = 0;
  643. if (cp->cnic_uinfo) {
  644. while (cp->uio_dev != -1 && i < 15) {
  645. msleep(100);
  646. i++;
  647. }
  648. uio_unregister_device(cp->cnic_uinfo);
  649. kfree(cp->cnic_uinfo);
  650. cp->cnic_uinfo = NULL;
  651. }
  652. if (cp->l2_buf) {
  653. dma_free_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  654. cp->l2_buf, cp->l2_buf_map);
  655. cp->l2_buf = NULL;
  656. }
  657. if (cp->l2_ring) {
  658. dma_free_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  659. cp->l2_ring, cp->l2_ring_map);
  660. cp->l2_ring = NULL;
  661. }
  662. cnic_free_context(dev);
  663. kfree(cp->ctx_arr);
  664. cp->ctx_arr = NULL;
  665. cp->ctx_blks = 0;
  666. cnic_free_dma(dev, &cp->gbl_buf_info);
  667. cnic_free_dma(dev, &cp->conn_buf_info);
  668. cnic_free_dma(dev, &cp->kwq_info);
  669. cnic_free_dma(dev, &cp->kwq_16_data_info);
  670. cnic_free_dma(dev, &cp->kcq_info);
  671. kfree(cp->iscsi_tbl);
  672. cp->iscsi_tbl = NULL;
  673. kfree(cp->ctx_tbl);
  674. cp->ctx_tbl = NULL;
  675. cnic_free_id_tbl(&cp->cid_tbl);
  676. }
  677. static int cnic_alloc_context(struct cnic_dev *dev)
  678. {
  679. struct cnic_local *cp = dev->cnic_priv;
  680. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  681. int i, k, arr_size;
  682. cp->ctx_blk_size = BCM_PAGE_SIZE;
  683. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  684. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  685. sizeof(struct cnic_ctx);
  686. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  687. if (cp->ctx_arr == NULL)
  688. return -ENOMEM;
  689. k = 0;
  690. for (i = 0; i < 2; i++) {
  691. u32 j, reg, off, lo, hi;
  692. if (i == 0)
  693. off = BNX2_PG_CTX_MAP;
  694. else
  695. off = BNX2_ISCSI_CTX_MAP;
  696. reg = cnic_reg_rd_ind(dev, off);
  697. lo = reg >> 16;
  698. hi = reg & 0xffff;
  699. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  700. cp->ctx_arr[k].cid = j;
  701. }
  702. cp->ctx_blks = k;
  703. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  704. cp->ctx_blks = 0;
  705. return -ENOMEM;
  706. }
  707. for (i = 0; i < cp->ctx_blks; i++) {
  708. cp->ctx_arr[i].ctx =
  709. dma_alloc_coherent(&dev->pcidev->dev,
  710. BCM_PAGE_SIZE,
  711. &cp->ctx_arr[i].mapping,
  712. GFP_KERNEL);
  713. if (cp->ctx_arr[i].ctx == NULL)
  714. return -ENOMEM;
  715. }
  716. }
  717. return 0;
  718. }
  719. static int cnic_alloc_l2_rings(struct cnic_dev *dev, int pages)
  720. {
  721. struct cnic_local *cp = dev->cnic_priv;
  722. cp->l2_ring_size = pages * BCM_PAGE_SIZE;
  723. cp->l2_ring = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  724. &cp->l2_ring_map,
  725. GFP_KERNEL | __GFP_COMP);
  726. if (!cp->l2_ring)
  727. return -ENOMEM;
  728. cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  729. cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
  730. cp->l2_buf = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  731. &cp->l2_buf_map,
  732. GFP_KERNEL | __GFP_COMP);
  733. if (!cp->l2_buf)
  734. return -ENOMEM;
  735. return 0;
  736. }
  737. static int cnic_alloc_uio(struct cnic_dev *dev) {
  738. struct cnic_local *cp = dev->cnic_priv;
  739. struct uio_info *uinfo;
  740. int ret;
  741. uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
  742. if (!uinfo)
  743. return -ENOMEM;
  744. uinfo->mem[0].addr = dev->netdev->base_addr;
  745. uinfo->mem[0].internal_addr = dev->regview;
  746. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  747. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  748. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  749. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  750. PAGE_MASK;
  751. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  752. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  753. else
  754. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  755. uinfo->name = "bnx2_cnic";
  756. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  757. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  758. PAGE_MASK;
  759. uinfo->mem[1].size = sizeof(struct host_def_status_block);
  760. uinfo->name = "bnx2x_cnic";
  761. }
  762. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  763. uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
  764. uinfo->mem[2].size = cp->l2_ring_size;
  765. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  766. uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
  767. uinfo->mem[3].size = cp->l2_buf_size;
  768. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  769. uinfo->version = CNIC_MODULE_VERSION;
  770. uinfo->irq = UIO_IRQ_CUSTOM;
  771. uinfo->open = cnic_uio_open;
  772. uinfo->release = cnic_uio_close;
  773. uinfo->priv = dev;
  774. ret = uio_register_device(&dev->pcidev->dev, uinfo);
  775. if (ret) {
  776. kfree(uinfo);
  777. return ret;
  778. }
  779. cp->cnic_uinfo = uinfo;
  780. return 0;
  781. }
  782. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  783. {
  784. struct cnic_local *cp = dev->cnic_priv;
  785. int ret;
  786. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  787. if (ret)
  788. goto error;
  789. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  790. ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 1);
  791. if (ret)
  792. goto error;
  793. cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
  794. ret = cnic_alloc_context(dev);
  795. if (ret)
  796. goto error;
  797. ret = cnic_alloc_l2_rings(dev, 2);
  798. if (ret)
  799. goto error;
  800. ret = cnic_alloc_uio(dev);
  801. if (ret)
  802. goto error;
  803. return 0;
  804. error:
  805. cnic_free_resc(dev);
  806. return ret;
  807. }
  808. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  809. {
  810. struct cnic_local *cp = dev->cnic_priv;
  811. struct cnic_eth_dev *ethdev = cp->ethdev;
  812. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  813. int total_mem, blks, i, cid_space;
  814. if (BNX2X_ISCSI_START_CID < ethdev->starting_cid)
  815. return -EINVAL;
  816. cid_space = MAX_ISCSI_TBL_SZ +
  817. (BNX2X_ISCSI_START_CID - ethdev->starting_cid);
  818. total_mem = BNX2X_CONTEXT_MEM_SIZE * cid_space;
  819. blks = total_mem / ctx_blk_size;
  820. if (total_mem % ctx_blk_size)
  821. blks++;
  822. if (blks > cp->ethdev->ctx_tbl_len)
  823. return -ENOMEM;
  824. cp->ctx_arr = kzalloc(blks * sizeof(struct cnic_ctx), GFP_KERNEL);
  825. if (cp->ctx_arr == NULL)
  826. return -ENOMEM;
  827. cp->ctx_blks = blks;
  828. cp->ctx_blk_size = ctx_blk_size;
  829. if (BNX2X_CHIP_IS_E1H(cp->chip_id))
  830. cp->ctx_align = 0;
  831. else
  832. cp->ctx_align = ctx_blk_size;
  833. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  834. for (i = 0; i < blks; i++) {
  835. cp->ctx_arr[i].ctx =
  836. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  837. &cp->ctx_arr[i].mapping,
  838. GFP_KERNEL);
  839. if (cp->ctx_arr[i].ctx == NULL)
  840. return -ENOMEM;
  841. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  842. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  843. cnic_free_context(dev);
  844. cp->ctx_blk_size += cp->ctx_align;
  845. i = -1;
  846. continue;
  847. }
  848. }
  849. }
  850. return 0;
  851. }
  852. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  853. {
  854. struct cnic_local *cp = dev->cnic_priv;
  855. int i, j, n, ret, pages;
  856. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  857. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  858. GFP_KERNEL);
  859. if (!cp->iscsi_tbl)
  860. goto error;
  861. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  862. MAX_CNIC_L5_CONTEXT, GFP_KERNEL);
  863. if (!cp->ctx_tbl)
  864. goto error;
  865. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  866. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  867. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  868. }
  869. pages = PAGE_ALIGN(MAX_CNIC_L5_CONTEXT * CNIC_KWQ16_DATA_SIZE) /
  870. PAGE_SIZE;
  871. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  872. if (ret)
  873. return -ENOMEM;
  874. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  875. for (i = 0, j = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  876. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  877. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  878. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  879. off;
  880. if ((i % n) == (n - 1))
  881. j++;
  882. }
  883. ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 0);
  884. if (ret)
  885. goto error;
  886. cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
  887. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  888. struct bnx2x_bd_chain_next *next =
  889. (struct bnx2x_bd_chain_next *)
  890. &cp->kcq[i][MAX_KCQE_CNT];
  891. int j = i + 1;
  892. if (j >= KCQ_PAGE_CNT)
  893. j = 0;
  894. next->addr_hi = (u64) cp->kcq_info.pg_map_arr[j] >> 32;
  895. next->addr_lo = cp->kcq_info.pg_map_arr[j] & 0xffffffff;
  896. }
  897. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  898. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  899. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  900. if (ret)
  901. goto error;
  902. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  903. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  904. if (ret)
  905. goto error;
  906. ret = cnic_alloc_bnx2x_context(dev);
  907. if (ret)
  908. goto error;
  909. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  910. memset(cp->status_blk.bnx2x, 0, sizeof(*cp->status_blk.bnx2x));
  911. cp->l2_rx_ring_size = 15;
  912. ret = cnic_alloc_l2_rings(dev, 4);
  913. if (ret)
  914. goto error;
  915. ret = cnic_alloc_uio(dev);
  916. if (ret)
  917. goto error;
  918. return 0;
  919. error:
  920. cnic_free_resc(dev);
  921. return -ENOMEM;
  922. }
  923. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  924. {
  925. return cp->max_kwq_idx -
  926. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  927. }
  928. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  929. u32 num_wqes)
  930. {
  931. struct cnic_local *cp = dev->cnic_priv;
  932. struct kwqe *prod_qe;
  933. u16 prod, sw_prod, i;
  934. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  935. return -EAGAIN; /* bnx2 is down */
  936. spin_lock_bh(&cp->cnic_ulp_lock);
  937. if (num_wqes > cnic_kwq_avail(cp) &&
  938. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  939. spin_unlock_bh(&cp->cnic_ulp_lock);
  940. return -EAGAIN;
  941. }
  942. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  943. prod = cp->kwq_prod_idx;
  944. sw_prod = prod & MAX_KWQ_IDX;
  945. for (i = 0; i < num_wqes; i++) {
  946. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  947. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  948. prod++;
  949. sw_prod = prod & MAX_KWQ_IDX;
  950. }
  951. cp->kwq_prod_idx = prod;
  952. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  953. spin_unlock_bh(&cp->cnic_ulp_lock);
  954. return 0;
  955. }
  956. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  957. union l5cm_specific_data *l5_data)
  958. {
  959. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  960. dma_addr_t map;
  961. map = ctx->kwqe_data_mapping;
  962. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  963. l5_data->phy_address.hi = (u64) map >> 32;
  964. return ctx->kwqe_data;
  965. }
  966. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  967. u32 type, union l5cm_specific_data *l5_data)
  968. {
  969. struct cnic_local *cp = dev->cnic_priv;
  970. struct l5cm_spe kwqe;
  971. struct kwqe_16 *kwq[1];
  972. int ret;
  973. kwqe.hdr.conn_and_cmd_data =
  974. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  975. BNX2X_HW_CID(cid, cp->func)));
  976. kwqe.hdr.type = cpu_to_le16(type);
  977. kwqe.hdr.reserved = 0;
  978. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  979. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  980. kwq[0] = (struct kwqe_16 *) &kwqe;
  981. spin_lock_bh(&cp->cnic_ulp_lock);
  982. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  983. spin_unlock_bh(&cp->cnic_ulp_lock);
  984. if (ret == 1)
  985. return 0;
  986. return -EBUSY;
  987. }
  988. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  989. struct kcqe *cqes[], u32 num_cqes)
  990. {
  991. struct cnic_local *cp = dev->cnic_priv;
  992. struct cnic_ulp_ops *ulp_ops;
  993. rcu_read_lock();
  994. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  995. if (likely(ulp_ops)) {
  996. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  997. cqes, num_cqes);
  998. }
  999. rcu_read_unlock();
  1000. }
  1001. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1002. {
  1003. struct cnic_local *cp = dev->cnic_priv;
  1004. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1005. int func = cp->func, pages;
  1006. int hq_bds;
  1007. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1008. cp->num_ccells = req1->num_ccells_per_conn;
  1009. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1010. cp->num_iscsi_tasks;
  1011. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1012. BNX2X_ISCSI_R2TQE_SIZE;
  1013. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1014. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1015. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1016. cp->num_cqs = req1->num_cqs;
  1017. if (!dev->max_iscsi_conn)
  1018. return 0;
  1019. /* init Tstorm RAM */
  1020. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(func),
  1021. req1->rq_num_wqes);
  1022. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1023. PAGE_SIZE);
  1024. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1025. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1026. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1027. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1028. req1->num_tasks_per_conn);
  1029. /* init Ustorm RAM */
  1030. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1031. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(func),
  1032. req1->rq_buffer_size);
  1033. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1034. PAGE_SIZE);
  1035. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1036. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1037. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1038. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1039. req1->num_tasks_per_conn);
  1040. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(func),
  1041. req1->rq_num_wqes);
  1042. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(func),
  1043. req1->cq_num_wqes);
  1044. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
  1045. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1046. /* init Xstorm RAM */
  1047. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1048. PAGE_SIZE);
  1049. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1050. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1051. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1052. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1053. req1->num_tasks_per_conn);
  1054. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(func),
  1055. hq_bds);
  1056. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(func),
  1057. req1->num_tasks_per_conn);
  1058. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
  1059. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1060. /* init Cstorm RAM */
  1061. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1062. PAGE_SIZE);
  1063. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1064. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1065. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1066. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1067. req1->num_tasks_per_conn);
  1068. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(func),
  1069. req1->cq_num_wqes);
  1070. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(func),
  1071. hq_bds);
  1072. return 0;
  1073. }
  1074. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1075. {
  1076. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1077. struct cnic_local *cp = dev->cnic_priv;
  1078. int func = cp->func;
  1079. struct iscsi_kcqe kcqe;
  1080. struct kcqe *cqes[1];
  1081. memset(&kcqe, 0, sizeof(kcqe));
  1082. if (!dev->max_iscsi_conn) {
  1083. kcqe.completion_status =
  1084. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1085. goto done;
  1086. }
  1087. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1088. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
  1089. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1090. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
  1091. req2->error_bit_map[1]);
  1092. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1093. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
  1094. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1095. USTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
  1096. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1097. USTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
  1098. req2->error_bit_map[1]);
  1099. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1100. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
  1101. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1102. done:
  1103. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1104. cqes[0] = (struct kcqe *) &kcqe;
  1105. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1106. return 0;
  1107. }
  1108. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1109. {
  1110. struct cnic_local *cp = dev->cnic_priv;
  1111. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1112. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1113. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1114. cnic_free_dma(dev, &iscsi->hq_info);
  1115. cnic_free_dma(dev, &iscsi->r2tq_info);
  1116. cnic_free_dma(dev, &iscsi->task_array_info);
  1117. }
  1118. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1119. ctx->cid = 0;
  1120. }
  1121. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1122. {
  1123. u32 cid;
  1124. int ret, pages;
  1125. struct cnic_local *cp = dev->cnic_priv;
  1126. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1127. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1128. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1129. if (cid == -1) {
  1130. ret = -ENOMEM;
  1131. goto error;
  1132. }
  1133. ctx->cid = cid;
  1134. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1135. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1136. if (ret)
  1137. goto error;
  1138. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1139. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1140. if (ret)
  1141. goto error;
  1142. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1143. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1144. if (ret)
  1145. goto error;
  1146. return 0;
  1147. error:
  1148. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1149. return ret;
  1150. }
  1151. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1152. struct regpair *ctx_addr)
  1153. {
  1154. struct cnic_local *cp = dev->cnic_priv;
  1155. struct cnic_eth_dev *ethdev = cp->ethdev;
  1156. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1157. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1158. unsigned long align_off = 0;
  1159. dma_addr_t ctx_map;
  1160. void *ctx;
  1161. if (cp->ctx_align) {
  1162. unsigned long mask = cp->ctx_align - 1;
  1163. if (cp->ctx_arr[blk].mapping & mask)
  1164. align_off = cp->ctx_align -
  1165. (cp->ctx_arr[blk].mapping & mask);
  1166. }
  1167. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1168. (off * BNX2X_CONTEXT_MEM_SIZE);
  1169. ctx = cp->ctx_arr[blk].ctx + align_off +
  1170. (off * BNX2X_CONTEXT_MEM_SIZE);
  1171. if (init)
  1172. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1173. ctx_addr->lo = ctx_map & 0xffffffff;
  1174. ctx_addr->hi = (u64) ctx_map >> 32;
  1175. return ctx;
  1176. }
  1177. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1178. u32 num)
  1179. {
  1180. struct cnic_local *cp = dev->cnic_priv;
  1181. struct iscsi_kwqe_conn_offload1 *req1 =
  1182. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1183. struct iscsi_kwqe_conn_offload2 *req2 =
  1184. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1185. struct iscsi_kwqe_conn_offload3 *req3;
  1186. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1187. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1188. u32 cid = ctx->cid;
  1189. u32 hw_cid = BNX2X_HW_CID(cid, cp->func);
  1190. struct iscsi_context *ictx;
  1191. struct regpair context_addr;
  1192. int i, j, n = 2, n_max;
  1193. ctx->ctx_flags = 0;
  1194. if (!req2->num_additional_wqes)
  1195. return -EINVAL;
  1196. n_max = req2->num_additional_wqes + 2;
  1197. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1198. if (ictx == NULL)
  1199. return -ENOMEM;
  1200. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1201. ictx->xstorm_ag_context.hq_prod = 1;
  1202. ictx->xstorm_st_context.iscsi.first_burst_length =
  1203. ISCSI_DEF_FIRST_BURST_LEN;
  1204. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1205. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1206. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1207. req1->sq_page_table_addr_lo;
  1208. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1209. req1->sq_page_table_addr_hi;
  1210. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1211. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1212. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1213. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1214. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1215. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1216. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1217. iscsi->hq_info.pgtbl[0];
  1218. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1219. iscsi->hq_info.pgtbl[1];
  1220. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1221. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1222. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1223. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1224. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1225. iscsi->r2tq_info.pgtbl[0];
  1226. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1227. iscsi->r2tq_info.pgtbl[1];
  1228. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1229. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1230. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1231. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1232. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1233. BNX2X_ISCSI_PBL_NOT_CACHED;
  1234. ictx->xstorm_st_context.iscsi.flags.flags |=
  1235. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1236. ictx->xstorm_st_context.iscsi.flags.flags |=
  1237. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1238. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1239. /* TSTORM requires the base address of RQ DB & not PTE */
  1240. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1241. req2->rq_page_table_addr_lo & PAGE_MASK;
  1242. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1243. req2->rq_page_table_addr_hi;
  1244. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1245. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1246. ictx->tstorm_st_context.tcp.flags2 |=
  1247. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1248. ictx->timers_context.flags |= ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1249. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1250. req2->rq_page_table_addr_lo;
  1251. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1252. req2->rq_page_table_addr_hi;
  1253. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1254. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1255. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1256. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1257. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1258. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1259. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1260. iscsi->r2tq_info.pgtbl[0];
  1261. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1262. iscsi->r2tq_info.pgtbl[1];
  1263. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1264. req1->cq_page_table_addr_lo;
  1265. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1266. req1->cq_page_table_addr_hi;
  1267. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1268. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1269. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1270. ictx->ustorm_st_context.task_pbe_cache_index =
  1271. BNX2X_ISCSI_PBL_NOT_CACHED;
  1272. ictx->ustorm_st_context.task_pdu_cache_index =
  1273. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1274. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1275. if (j == 3) {
  1276. if (n >= n_max)
  1277. break;
  1278. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1279. j = 0;
  1280. }
  1281. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1282. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1283. req3->qp_first_pte[j].hi;
  1284. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1285. req3->qp_first_pte[j].lo;
  1286. }
  1287. ictx->ustorm_st_context.task_pbl_base.lo =
  1288. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1289. ictx->ustorm_st_context.task_pbl_base.hi =
  1290. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1291. ictx->ustorm_st_context.tce_phy_addr.lo =
  1292. iscsi->task_array_info.pgtbl[0];
  1293. ictx->ustorm_st_context.tce_phy_addr.hi =
  1294. iscsi->task_array_info.pgtbl[1];
  1295. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1296. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1297. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1298. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1299. ISCSI_DEF_MAX_BURST_LEN;
  1300. ictx->ustorm_st_context.negotiated_rx |=
  1301. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1302. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1303. ictx->cstorm_st_context.hq_pbl_base.lo =
  1304. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1305. ictx->cstorm_st_context.hq_pbl_base.hi =
  1306. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1307. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1308. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1309. ictx->cstorm_st_context.task_pbl_base.lo =
  1310. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1311. ictx->cstorm_st_context.task_pbl_base.hi =
  1312. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1313. /* CSTORM and USTORM initialization is different, CSTORM requires
  1314. * CQ DB base & not PTE addr */
  1315. ictx->cstorm_st_context.cq_db_base.lo =
  1316. req1->cq_page_table_addr_lo & PAGE_MASK;
  1317. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1318. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1319. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1320. for (i = 0; i < cp->num_cqs; i++) {
  1321. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1322. ISCSI_INITIAL_SN;
  1323. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1324. ISCSI_INITIAL_SN;
  1325. }
  1326. ictx->xstorm_ag_context.cdu_reserved =
  1327. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1328. ISCSI_CONNECTION_TYPE);
  1329. ictx->ustorm_ag_context.cdu_usage =
  1330. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1331. ISCSI_CONNECTION_TYPE);
  1332. return 0;
  1333. }
  1334. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1335. u32 num, int *work)
  1336. {
  1337. struct iscsi_kwqe_conn_offload1 *req1;
  1338. struct iscsi_kwqe_conn_offload2 *req2;
  1339. struct cnic_local *cp = dev->cnic_priv;
  1340. struct iscsi_kcqe kcqe;
  1341. struct kcqe *cqes[1];
  1342. u32 l5_cid;
  1343. int ret;
  1344. if (num < 2) {
  1345. *work = num;
  1346. return -EINVAL;
  1347. }
  1348. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1349. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1350. if ((num - 2) < req2->num_additional_wqes) {
  1351. *work = num;
  1352. return -EINVAL;
  1353. }
  1354. *work = 2 + req2->num_additional_wqes;;
  1355. l5_cid = req1->iscsi_conn_id;
  1356. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1357. return -EINVAL;
  1358. memset(&kcqe, 0, sizeof(kcqe));
  1359. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1360. kcqe.iscsi_conn_id = l5_cid;
  1361. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1362. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1363. atomic_dec(&cp->iscsi_conn);
  1364. ret = 0;
  1365. goto done;
  1366. }
  1367. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1368. if (ret) {
  1369. atomic_dec(&cp->iscsi_conn);
  1370. ret = 0;
  1371. goto done;
  1372. }
  1373. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1374. if (ret < 0) {
  1375. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1376. atomic_dec(&cp->iscsi_conn);
  1377. goto done;
  1378. }
  1379. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1380. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp->ctx_tbl[l5_cid].cid,
  1381. cp->func);
  1382. done:
  1383. cqes[0] = (struct kcqe *) &kcqe;
  1384. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1385. return ret;
  1386. }
  1387. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1388. {
  1389. struct cnic_local *cp = dev->cnic_priv;
  1390. struct iscsi_kwqe_conn_update *req =
  1391. (struct iscsi_kwqe_conn_update *) kwqe;
  1392. void *data;
  1393. union l5cm_specific_data l5_data;
  1394. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1395. int ret;
  1396. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1397. return -EINVAL;
  1398. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1399. if (!data)
  1400. return -ENOMEM;
  1401. memcpy(data, kwqe, sizeof(struct kwqe));
  1402. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1403. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1404. return ret;
  1405. }
  1406. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1407. {
  1408. struct cnic_local *cp = dev->cnic_priv;
  1409. struct iscsi_kwqe_conn_destroy *req =
  1410. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1411. union l5cm_specific_data l5_data;
  1412. u32 l5_cid = req->reserved0;
  1413. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1414. int ret = 0;
  1415. struct iscsi_kcqe kcqe;
  1416. struct kcqe *cqes[1];
  1417. if (!(ctx->ctx_flags & CTX_FL_OFFLD_START))
  1418. goto skip_cfc_delete;
  1419. while (!time_after(jiffies, ctx->timestamp + (2 * HZ)))
  1420. msleep(250);
  1421. init_waitqueue_head(&ctx->waitq);
  1422. ctx->wait_cond = 0;
  1423. memset(&l5_data, 0, sizeof(l5_data));
  1424. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
  1425. req->context_id,
  1426. ETH_CONNECTION_TYPE |
  1427. (1 << SPE_HDR_COMMON_RAMROD_SHIFT),
  1428. &l5_data);
  1429. if (ret == 0)
  1430. wait_event(ctx->waitq, ctx->wait_cond);
  1431. skip_cfc_delete:
  1432. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1433. atomic_dec(&cp->iscsi_conn);
  1434. memset(&kcqe, 0, sizeof(kcqe));
  1435. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1436. kcqe.iscsi_conn_id = l5_cid;
  1437. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1438. kcqe.iscsi_conn_context_id = req->context_id;
  1439. cqes[0] = (struct kcqe *) &kcqe;
  1440. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1441. return ret;
  1442. }
  1443. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1444. struct l4_kwq_connect_req1 *kwqe1,
  1445. struct l4_kwq_connect_req3 *kwqe3,
  1446. struct l5cm_active_conn_buffer *conn_buf)
  1447. {
  1448. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1449. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1450. &conn_buf->xstorm_conn_buffer;
  1451. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1452. &conn_buf->tstorm_conn_buffer;
  1453. struct regpair context_addr;
  1454. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1455. struct in6_addr src_ip, dst_ip;
  1456. int i;
  1457. u32 *addrp;
  1458. addrp = (u32 *) &conn_addr->local_ip_addr;
  1459. for (i = 0; i < 4; i++, addrp++)
  1460. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1461. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1462. for (i = 0; i < 4; i++, addrp++)
  1463. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1464. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1465. xstorm_buf->context_addr.hi = context_addr.hi;
  1466. xstorm_buf->context_addr.lo = context_addr.lo;
  1467. xstorm_buf->mss = 0xffff;
  1468. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1469. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1470. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1471. xstorm_buf->pseudo_header_checksum =
  1472. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1473. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1474. tstorm_buf->params |=
  1475. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1476. if (kwqe3->ka_timeout) {
  1477. tstorm_buf->ka_enable = 1;
  1478. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1479. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1480. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1481. }
  1482. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1483. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1484. tstorm_buf->max_rt_time = 0xffffffff;
  1485. }
  1486. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1487. {
  1488. struct cnic_local *cp = dev->cnic_priv;
  1489. int func = CNIC_FUNC(cp);
  1490. u8 *mac = dev->mac_addr;
  1491. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1492. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(func), mac[0]);
  1493. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1494. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(func), mac[1]);
  1495. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1496. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(func), mac[2]);
  1497. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1498. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(func), mac[3]);
  1499. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1500. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(func), mac[4]);
  1501. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1502. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(func), mac[5]);
  1503. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1504. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func), mac[5]);
  1505. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1506. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
  1507. mac[4]);
  1508. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1509. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func), mac[3]);
  1510. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1511. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
  1512. mac[2]);
  1513. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1514. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 2,
  1515. mac[1]);
  1516. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1517. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 3,
  1518. mac[0]);
  1519. }
  1520. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1521. {
  1522. struct cnic_local *cp = dev->cnic_priv;
  1523. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1524. u16 tstorm_flags = 0;
  1525. if (tcp_ts) {
  1526. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1527. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1528. }
  1529. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1530. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), xstorm_flags);
  1531. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1532. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), tstorm_flags);
  1533. }
  1534. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1535. u32 num, int *work)
  1536. {
  1537. struct cnic_local *cp = dev->cnic_priv;
  1538. struct l4_kwq_connect_req1 *kwqe1 =
  1539. (struct l4_kwq_connect_req1 *) wqes[0];
  1540. struct l4_kwq_connect_req3 *kwqe3;
  1541. struct l5cm_active_conn_buffer *conn_buf;
  1542. struct l5cm_conn_addr_params *conn_addr;
  1543. union l5cm_specific_data l5_data;
  1544. u32 l5_cid = kwqe1->pg_cid;
  1545. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1546. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1547. int ret;
  1548. if (num < 2) {
  1549. *work = num;
  1550. return -EINVAL;
  1551. }
  1552. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1553. *work = 3;
  1554. else
  1555. *work = 2;
  1556. if (num < *work) {
  1557. *work = num;
  1558. return -EINVAL;
  1559. }
  1560. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1561. netdev_err(dev->netdev, "conn_buf size too big\n");
  1562. return -ENOMEM;
  1563. }
  1564. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1565. if (!conn_buf)
  1566. return -ENOMEM;
  1567. memset(conn_buf, 0, sizeof(*conn_buf));
  1568. conn_addr = &conn_buf->conn_addr_buf;
  1569. conn_addr->remote_addr_0 = csk->ha[0];
  1570. conn_addr->remote_addr_1 = csk->ha[1];
  1571. conn_addr->remote_addr_2 = csk->ha[2];
  1572. conn_addr->remote_addr_3 = csk->ha[3];
  1573. conn_addr->remote_addr_4 = csk->ha[4];
  1574. conn_addr->remote_addr_5 = csk->ha[5];
  1575. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1576. struct l4_kwq_connect_req2 *kwqe2 =
  1577. (struct l4_kwq_connect_req2 *) wqes[1];
  1578. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1579. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1580. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1581. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1582. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1583. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1584. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1585. }
  1586. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1587. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1588. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1589. conn_addr->local_tcp_port = kwqe1->src_port;
  1590. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1591. conn_addr->pmtu = kwqe3->pmtu;
  1592. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1593. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1594. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->func), csk->vlan_id);
  1595. cnic_bnx2x_set_tcp_timestamp(dev,
  1596. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1597. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1598. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1599. if (!ret)
  1600. ctx->ctx_flags |= CTX_FL_OFFLD_START;
  1601. return ret;
  1602. }
  1603. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1604. {
  1605. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1606. union l5cm_specific_data l5_data;
  1607. int ret;
  1608. memset(&l5_data, 0, sizeof(l5_data));
  1609. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1610. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1611. return ret;
  1612. }
  1613. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1614. {
  1615. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1616. union l5cm_specific_data l5_data;
  1617. int ret;
  1618. memset(&l5_data, 0, sizeof(l5_data));
  1619. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1620. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1621. return ret;
  1622. }
  1623. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1624. {
  1625. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1626. struct l4_kcq kcqe;
  1627. struct kcqe *cqes[1];
  1628. memset(&kcqe, 0, sizeof(kcqe));
  1629. kcqe.pg_host_opaque = req->host_opaque;
  1630. kcqe.pg_cid = req->host_opaque;
  1631. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1632. cqes[0] = (struct kcqe *) &kcqe;
  1633. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1634. return 0;
  1635. }
  1636. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1637. {
  1638. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1639. struct l4_kcq kcqe;
  1640. struct kcqe *cqes[1];
  1641. memset(&kcqe, 0, sizeof(kcqe));
  1642. kcqe.pg_host_opaque = req->pg_host_opaque;
  1643. kcqe.pg_cid = req->pg_cid;
  1644. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1645. cqes[0] = (struct kcqe *) &kcqe;
  1646. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1647. return 0;
  1648. }
  1649. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1650. u32 num_wqes)
  1651. {
  1652. int i, work, ret;
  1653. u32 opcode;
  1654. struct kwqe *kwqe;
  1655. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1656. return -EAGAIN; /* bnx2 is down */
  1657. for (i = 0; i < num_wqes; ) {
  1658. kwqe = wqes[i];
  1659. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1660. work = 1;
  1661. switch (opcode) {
  1662. case ISCSI_KWQE_OPCODE_INIT1:
  1663. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1664. break;
  1665. case ISCSI_KWQE_OPCODE_INIT2:
  1666. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1667. break;
  1668. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1669. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1670. num_wqes - i, &work);
  1671. break;
  1672. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1673. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1674. break;
  1675. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1676. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1677. break;
  1678. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1679. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1680. &work);
  1681. break;
  1682. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1683. ret = cnic_bnx2x_close(dev, kwqe);
  1684. break;
  1685. case L4_KWQE_OPCODE_VALUE_RESET:
  1686. ret = cnic_bnx2x_reset(dev, kwqe);
  1687. break;
  1688. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1689. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1690. break;
  1691. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1692. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1693. break;
  1694. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1695. ret = 0;
  1696. break;
  1697. default:
  1698. ret = 0;
  1699. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  1700. opcode);
  1701. break;
  1702. }
  1703. if (ret < 0)
  1704. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  1705. opcode);
  1706. i += work;
  1707. }
  1708. return 0;
  1709. }
  1710. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1711. {
  1712. struct cnic_local *cp = dev->cnic_priv;
  1713. int i, j;
  1714. i = 0;
  1715. j = 1;
  1716. while (num_cqes) {
  1717. struct cnic_ulp_ops *ulp_ops;
  1718. int ulp_type;
  1719. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1720. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1721. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1722. cnic_kwq_completion(dev, 1);
  1723. while (j < num_cqes) {
  1724. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1725. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1726. break;
  1727. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1728. cnic_kwq_completion(dev, 1);
  1729. j++;
  1730. }
  1731. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1732. ulp_type = CNIC_ULP_RDMA;
  1733. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1734. ulp_type = CNIC_ULP_ISCSI;
  1735. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1736. ulp_type = CNIC_ULP_L4;
  1737. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1738. goto end;
  1739. else {
  1740. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  1741. kcqe_op_flag);
  1742. goto end;
  1743. }
  1744. rcu_read_lock();
  1745. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1746. if (likely(ulp_ops)) {
  1747. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1748. cp->completed_kcq + i, j);
  1749. }
  1750. rcu_read_unlock();
  1751. end:
  1752. num_cqes -= j;
  1753. i += j;
  1754. j = 1;
  1755. }
  1756. }
  1757. static u16 cnic_bnx2_next_idx(u16 idx)
  1758. {
  1759. return idx + 1;
  1760. }
  1761. static u16 cnic_bnx2_hw_idx(u16 idx)
  1762. {
  1763. return idx;
  1764. }
  1765. static u16 cnic_bnx2x_next_idx(u16 idx)
  1766. {
  1767. idx++;
  1768. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1769. idx++;
  1770. return idx;
  1771. }
  1772. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1773. {
  1774. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1775. idx++;
  1776. return idx;
  1777. }
  1778. static int cnic_get_kcqes(struct cnic_dev *dev, u16 hw_prod, u16 *sw_prod)
  1779. {
  1780. struct cnic_local *cp = dev->cnic_priv;
  1781. u16 i, ri, last;
  1782. struct kcqe *kcqe;
  1783. int kcqe_cnt = 0, last_cnt = 0;
  1784. i = ri = last = *sw_prod;
  1785. ri &= MAX_KCQ_IDX;
  1786. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1787. kcqe = &cp->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1788. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1789. i = cp->next_idx(i);
  1790. ri = i & MAX_KCQ_IDX;
  1791. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1792. last_cnt = kcqe_cnt;
  1793. last = i;
  1794. }
  1795. }
  1796. *sw_prod = last;
  1797. return last_cnt;
  1798. }
  1799. static int cnic_l2_completion(struct cnic_local *cp)
  1800. {
  1801. u16 hw_cons, sw_cons;
  1802. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  1803. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  1804. u32 cmd;
  1805. int comp = 0;
  1806. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  1807. return 0;
  1808. hw_cons = *cp->rx_cons_ptr;
  1809. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  1810. hw_cons++;
  1811. sw_cons = cp->rx_cons;
  1812. while (sw_cons != hw_cons) {
  1813. u8 cqe_fp_flags;
  1814. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  1815. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  1816. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  1817. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  1818. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  1819. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  1820. cmd == RAMROD_CMD_ID_ETH_HALT)
  1821. comp++;
  1822. }
  1823. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  1824. }
  1825. return comp;
  1826. }
  1827. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1828. {
  1829. u16 rx_cons = *cp->rx_cons_ptr;
  1830. u16 tx_cons = *cp->tx_cons_ptr;
  1831. int comp = 0;
  1832. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1833. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  1834. comp = cnic_l2_completion(cp);
  1835. cp->tx_cons = tx_cons;
  1836. cp->rx_cons = rx_cons;
  1837. uio_event_notify(cp->cnic_uinfo);
  1838. }
  1839. if (comp)
  1840. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  1841. }
  1842. static int cnic_service_bnx2(void *data, void *status_blk)
  1843. {
  1844. struct cnic_dev *dev = data;
  1845. struct status_block *sblk = status_blk;
  1846. struct cnic_local *cp = dev->cnic_priv;
  1847. u32 status_idx = sblk->status_idx;
  1848. u16 hw_prod, sw_prod;
  1849. int kcqe_cnt;
  1850. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1851. return status_idx;
  1852. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1853. hw_prod = sblk->status_completion_producer_index;
  1854. sw_prod = cp->kcq_prod_idx;
  1855. while (sw_prod != hw_prod) {
  1856. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1857. if (kcqe_cnt == 0)
  1858. goto done;
  1859. service_kcqes(dev, kcqe_cnt);
  1860. /* Tell compiler that status_blk fields can change. */
  1861. barrier();
  1862. if (status_idx != sblk->status_idx) {
  1863. status_idx = sblk->status_idx;
  1864. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1865. hw_prod = sblk->status_completion_producer_index;
  1866. } else
  1867. break;
  1868. }
  1869. done:
  1870. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
  1871. cp->kcq_prod_idx = sw_prod;
  1872. cnic_chk_pkt_rings(cp);
  1873. return status_idx;
  1874. }
  1875. static void cnic_service_bnx2_msix(unsigned long data)
  1876. {
  1877. struct cnic_dev *dev = (struct cnic_dev *) data;
  1878. struct cnic_local *cp = dev->cnic_priv;
  1879. struct status_block_msix *status_blk = cp->status_blk.bnx2;
  1880. u32 status_idx = status_blk->status_idx;
  1881. u16 hw_prod, sw_prod;
  1882. int kcqe_cnt;
  1883. cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
  1884. hw_prod = status_blk->status_completion_producer_index;
  1885. sw_prod = cp->kcq_prod_idx;
  1886. while (sw_prod != hw_prod) {
  1887. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1888. if (kcqe_cnt == 0)
  1889. goto done;
  1890. service_kcqes(dev, kcqe_cnt);
  1891. /* Tell compiler that status_blk fields can change. */
  1892. barrier();
  1893. if (status_idx != status_blk->status_idx) {
  1894. status_idx = status_blk->status_idx;
  1895. cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
  1896. hw_prod = status_blk->status_completion_producer_index;
  1897. } else
  1898. break;
  1899. }
  1900. done:
  1901. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
  1902. cp->kcq_prod_idx = sw_prod;
  1903. cnic_chk_pkt_rings(cp);
  1904. cp->last_status_idx = status_idx;
  1905. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1906. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1907. }
  1908. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1909. {
  1910. struct cnic_dev *dev = dev_instance;
  1911. struct cnic_local *cp = dev->cnic_priv;
  1912. u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
  1913. if (cp->ack_int)
  1914. cp->ack_int(dev);
  1915. prefetch(cp->status_blk.gen);
  1916. prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1917. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1918. tasklet_schedule(&cp->cnic_irq_task);
  1919. return IRQ_HANDLED;
  1920. }
  1921. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1922. u16 index, u8 op, u8 update)
  1923. {
  1924. struct cnic_local *cp = dev->cnic_priv;
  1925. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1926. COMMAND_REG_INT_ACK);
  1927. struct igu_ack_register igu_ack;
  1928. igu_ack.status_block_index = index;
  1929. igu_ack.sb_id_and_flags =
  1930. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  1931. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  1932. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  1933. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  1934. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  1935. }
  1936. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  1937. {
  1938. struct cnic_local *cp = dev->cnic_priv;
  1939. cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID, 0,
  1940. IGU_INT_DISABLE, 0);
  1941. }
  1942. static void cnic_service_bnx2x_bh(unsigned long data)
  1943. {
  1944. struct cnic_dev *dev = (struct cnic_dev *) data;
  1945. struct cnic_local *cp = dev->cnic_priv;
  1946. u16 hw_prod, sw_prod;
  1947. struct cstorm_status_block_c *sblk =
  1948. &cp->status_blk.bnx2x->c_status_block;
  1949. u32 status_idx = sblk->status_block_index;
  1950. int kcqe_cnt;
  1951. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1952. return;
  1953. hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
  1954. hw_prod = cp->hw_idx(hw_prod);
  1955. sw_prod = cp->kcq_prod_idx;
  1956. while (sw_prod != hw_prod) {
  1957. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1958. if (kcqe_cnt == 0)
  1959. goto done;
  1960. service_kcqes(dev, kcqe_cnt);
  1961. /* Tell compiler that sblk fields can change. */
  1962. barrier();
  1963. if (status_idx == sblk->status_block_index)
  1964. break;
  1965. status_idx = sblk->status_block_index;
  1966. hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
  1967. hw_prod = cp->hw_idx(hw_prod);
  1968. }
  1969. done:
  1970. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod + MAX_KCQ_IDX);
  1971. cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID,
  1972. status_idx, IGU_INT_ENABLE, 1);
  1973. cp->kcq_prod_idx = sw_prod;
  1974. }
  1975. static int cnic_service_bnx2x(void *data, void *status_blk)
  1976. {
  1977. struct cnic_dev *dev = data;
  1978. struct cnic_local *cp = dev->cnic_priv;
  1979. u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
  1980. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  1981. prefetch(cp->status_blk.bnx2x);
  1982. prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1983. tasklet_schedule(&cp->cnic_irq_task);
  1984. cnic_chk_pkt_rings(cp);
  1985. }
  1986. return 0;
  1987. }
  1988. static void cnic_ulp_stop(struct cnic_dev *dev)
  1989. {
  1990. struct cnic_local *cp = dev->cnic_priv;
  1991. int if_type;
  1992. if (cp->cnic_uinfo)
  1993. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  1994. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  1995. struct cnic_ulp_ops *ulp_ops;
  1996. mutex_lock(&cnic_lock);
  1997. ulp_ops = cp->ulp_ops[if_type];
  1998. if (!ulp_ops) {
  1999. mutex_unlock(&cnic_lock);
  2000. continue;
  2001. }
  2002. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2003. mutex_unlock(&cnic_lock);
  2004. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2005. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2006. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2007. }
  2008. }
  2009. static void cnic_ulp_start(struct cnic_dev *dev)
  2010. {
  2011. struct cnic_local *cp = dev->cnic_priv;
  2012. int if_type;
  2013. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2014. struct cnic_ulp_ops *ulp_ops;
  2015. mutex_lock(&cnic_lock);
  2016. ulp_ops = cp->ulp_ops[if_type];
  2017. if (!ulp_ops || !ulp_ops->cnic_start) {
  2018. mutex_unlock(&cnic_lock);
  2019. continue;
  2020. }
  2021. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2022. mutex_unlock(&cnic_lock);
  2023. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2024. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2025. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2026. }
  2027. }
  2028. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2029. {
  2030. struct cnic_dev *dev = data;
  2031. switch (info->cmd) {
  2032. case CNIC_CTL_STOP_CMD:
  2033. cnic_hold(dev);
  2034. cnic_ulp_stop(dev);
  2035. cnic_stop_hw(dev);
  2036. cnic_put(dev);
  2037. break;
  2038. case CNIC_CTL_START_CMD:
  2039. cnic_hold(dev);
  2040. if (!cnic_start_hw(dev))
  2041. cnic_ulp_start(dev);
  2042. cnic_put(dev);
  2043. break;
  2044. case CNIC_CTL_COMPLETION_CMD: {
  2045. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2046. u32 l5_cid;
  2047. struct cnic_local *cp = dev->cnic_priv;
  2048. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2049. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2050. ctx->wait_cond = 1;
  2051. wake_up(&ctx->waitq);
  2052. }
  2053. break;
  2054. }
  2055. default:
  2056. return -EINVAL;
  2057. }
  2058. return 0;
  2059. }
  2060. static void cnic_ulp_init(struct cnic_dev *dev)
  2061. {
  2062. int i;
  2063. struct cnic_local *cp = dev->cnic_priv;
  2064. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2065. struct cnic_ulp_ops *ulp_ops;
  2066. mutex_lock(&cnic_lock);
  2067. ulp_ops = cnic_ulp_tbl[i];
  2068. if (!ulp_ops || !ulp_ops->cnic_init) {
  2069. mutex_unlock(&cnic_lock);
  2070. continue;
  2071. }
  2072. ulp_get(ulp_ops);
  2073. mutex_unlock(&cnic_lock);
  2074. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2075. ulp_ops->cnic_init(dev);
  2076. ulp_put(ulp_ops);
  2077. }
  2078. }
  2079. static void cnic_ulp_exit(struct cnic_dev *dev)
  2080. {
  2081. int i;
  2082. struct cnic_local *cp = dev->cnic_priv;
  2083. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2084. struct cnic_ulp_ops *ulp_ops;
  2085. mutex_lock(&cnic_lock);
  2086. ulp_ops = cnic_ulp_tbl[i];
  2087. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2088. mutex_unlock(&cnic_lock);
  2089. continue;
  2090. }
  2091. ulp_get(ulp_ops);
  2092. mutex_unlock(&cnic_lock);
  2093. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2094. ulp_ops->cnic_exit(dev);
  2095. ulp_put(ulp_ops);
  2096. }
  2097. }
  2098. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2099. {
  2100. struct cnic_dev *dev = csk->dev;
  2101. struct l4_kwq_offload_pg *l4kwqe;
  2102. struct kwqe *wqes[1];
  2103. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2104. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2105. wqes[0] = (struct kwqe *) l4kwqe;
  2106. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2107. l4kwqe->flags =
  2108. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2109. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2110. l4kwqe->da0 = csk->ha[0];
  2111. l4kwqe->da1 = csk->ha[1];
  2112. l4kwqe->da2 = csk->ha[2];
  2113. l4kwqe->da3 = csk->ha[3];
  2114. l4kwqe->da4 = csk->ha[4];
  2115. l4kwqe->da5 = csk->ha[5];
  2116. l4kwqe->sa0 = dev->mac_addr[0];
  2117. l4kwqe->sa1 = dev->mac_addr[1];
  2118. l4kwqe->sa2 = dev->mac_addr[2];
  2119. l4kwqe->sa3 = dev->mac_addr[3];
  2120. l4kwqe->sa4 = dev->mac_addr[4];
  2121. l4kwqe->sa5 = dev->mac_addr[5];
  2122. l4kwqe->etype = ETH_P_IP;
  2123. l4kwqe->ipid_start = DEF_IPID_START;
  2124. l4kwqe->host_opaque = csk->l5_cid;
  2125. if (csk->vlan_id) {
  2126. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2127. l4kwqe->vlan_tag = csk->vlan_id;
  2128. l4kwqe->l2hdr_nbytes += 4;
  2129. }
  2130. return dev->submit_kwqes(dev, wqes, 1);
  2131. }
  2132. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2133. {
  2134. struct cnic_dev *dev = csk->dev;
  2135. struct l4_kwq_update_pg *l4kwqe;
  2136. struct kwqe *wqes[1];
  2137. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2138. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2139. wqes[0] = (struct kwqe *) l4kwqe;
  2140. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2141. l4kwqe->flags =
  2142. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2143. l4kwqe->pg_cid = csk->pg_cid;
  2144. l4kwqe->da0 = csk->ha[0];
  2145. l4kwqe->da1 = csk->ha[1];
  2146. l4kwqe->da2 = csk->ha[2];
  2147. l4kwqe->da3 = csk->ha[3];
  2148. l4kwqe->da4 = csk->ha[4];
  2149. l4kwqe->da5 = csk->ha[5];
  2150. l4kwqe->pg_host_opaque = csk->l5_cid;
  2151. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2152. return dev->submit_kwqes(dev, wqes, 1);
  2153. }
  2154. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2155. {
  2156. struct cnic_dev *dev = csk->dev;
  2157. struct l4_kwq_upload *l4kwqe;
  2158. struct kwqe *wqes[1];
  2159. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2160. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2161. wqes[0] = (struct kwqe *) l4kwqe;
  2162. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2163. l4kwqe->flags =
  2164. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2165. l4kwqe->cid = csk->pg_cid;
  2166. return dev->submit_kwqes(dev, wqes, 1);
  2167. }
  2168. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2169. {
  2170. struct cnic_dev *dev = csk->dev;
  2171. struct l4_kwq_connect_req1 *l4kwqe1;
  2172. struct l4_kwq_connect_req2 *l4kwqe2;
  2173. struct l4_kwq_connect_req3 *l4kwqe3;
  2174. struct kwqe *wqes[3];
  2175. u8 tcp_flags = 0;
  2176. int num_wqes = 2;
  2177. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2178. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2179. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2180. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2181. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2182. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2183. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2184. l4kwqe3->flags =
  2185. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2186. l4kwqe3->ka_timeout = csk->ka_timeout;
  2187. l4kwqe3->ka_interval = csk->ka_interval;
  2188. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2189. l4kwqe3->tos = csk->tos;
  2190. l4kwqe3->ttl = csk->ttl;
  2191. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2192. l4kwqe3->pmtu = csk->mtu;
  2193. l4kwqe3->rcv_buf = csk->rcv_buf;
  2194. l4kwqe3->snd_buf = csk->snd_buf;
  2195. l4kwqe3->seed = csk->seed;
  2196. wqes[0] = (struct kwqe *) l4kwqe1;
  2197. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2198. wqes[1] = (struct kwqe *) l4kwqe2;
  2199. wqes[2] = (struct kwqe *) l4kwqe3;
  2200. num_wqes = 3;
  2201. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2202. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2203. l4kwqe2->flags =
  2204. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2205. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2206. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2207. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2208. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2209. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2210. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2211. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2212. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2213. sizeof(struct tcphdr);
  2214. } else {
  2215. wqes[1] = (struct kwqe *) l4kwqe3;
  2216. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2217. sizeof(struct tcphdr);
  2218. }
  2219. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2220. l4kwqe1->flags =
  2221. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2222. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2223. l4kwqe1->cid = csk->cid;
  2224. l4kwqe1->pg_cid = csk->pg_cid;
  2225. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2226. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2227. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2228. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2229. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2230. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2231. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2232. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2233. if (csk->tcp_flags & SK_TCP_NAGLE)
  2234. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2235. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2236. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2237. if (csk->tcp_flags & SK_TCP_SACK)
  2238. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2239. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2240. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2241. l4kwqe1->tcp_flags = tcp_flags;
  2242. return dev->submit_kwqes(dev, wqes, num_wqes);
  2243. }
  2244. static int cnic_cm_close_req(struct cnic_sock *csk)
  2245. {
  2246. struct cnic_dev *dev = csk->dev;
  2247. struct l4_kwq_close_req *l4kwqe;
  2248. struct kwqe *wqes[1];
  2249. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2250. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2251. wqes[0] = (struct kwqe *) l4kwqe;
  2252. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2253. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2254. l4kwqe->cid = csk->cid;
  2255. return dev->submit_kwqes(dev, wqes, 1);
  2256. }
  2257. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2258. {
  2259. struct cnic_dev *dev = csk->dev;
  2260. struct l4_kwq_reset_req *l4kwqe;
  2261. struct kwqe *wqes[1];
  2262. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2263. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2264. wqes[0] = (struct kwqe *) l4kwqe;
  2265. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2266. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2267. l4kwqe->cid = csk->cid;
  2268. return dev->submit_kwqes(dev, wqes, 1);
  2269. }
  2270. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2271. u32 l5_cid, struct cnic_sock **csk, void *context)
  2272. {
  2273. struct cnic_local *cp = dev->cnic_priv;
  2274. struct cnic_sock *csk1;
  2275. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2276. return -EINVAL;
  2277. csk1 = &cp->csk_tbl[l5_cid];
  2278. if (atomic_read(&csk1->ref_count))
  2279. return -EAGAIN;
  2280. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2281. return -EBUSY;
  2282. csk1->dev = dev;
  2283. csk1->cid = cid;
  2284. csk1->l5_cid = l5_cid;
  2285. csk1->ulp_type = ulp_type;
  2286. csk1->context = context;
  2287. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2288. csk1->ka_interval = DEF_KA_INTERVAL;
  2289. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2290. csk1->tos = DEF_TOS;
  2291. csk1->ttl = DEF_TTL;
  2292. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2293. csk1->rcv_buf = DEF_RCV_BUF;
  2294. csk1->snd_buf = DEF_SND_BUF;
  2295. csk1->seed = DEF_SEED;
  2296. *csk = csk1;
  2297. return 0;
  2298. }
  2299. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2300. {
  2301. if (csk->src_port) {
  2302. struct cnic_dev *dev = csk->dev;
  2303. struct cnic_local *cp = dev->cnic_priv;
  2304. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  2305. csk->src_port = 0;
  2306. }
  2307. }
  2308. static void cnic_close_conn(struct cnic_sock *csk)
  2309. {
  2310. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2311. cnic_cm_upload_pg(csk);
  2312. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2313. }
  2314. cnic_cm_cleanup(csk);
  2315. }
  2316. static int cnic_cm_destroy(struct cnic_sock *csk)
  2317. {
  2318. if (!cnic_in_use(csk))
  2319. return -EINVAL;
  2320. csk_hold(csk);
  2321. clear_bit(SK_F_INUSE, &csk->flags);
  2322. smp_mb__after_clear_bit();
  2323. while (atomic_read(&csk->ref_count) != 1)
  2324. msleep(1);
  2325. cnic_cm_cleanup(csk);
  2326. csk->flags = 0;
  2327. csk_put(csk);
  2328. return 0;
  2329. }
  2330. static inline u16 cnic_get_vlan(struct net_device *dev,
  2331. struct net_device **vlan_dev)
  2332. {
  2333. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2334. *vlan_dev = vlan_dev_real_dev(dev);
  2335. return vlan_dev_vlan_id(dev);
  2336. }
  2337. *vlan_dev = dev;
  2338. return 0;
  2339. }
  2340. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2341. struct dst_entry **dst)
  2342. {
  2343. #if defined(CONFIG_INET)
  2344. struct flowi fl;
  2345. int err;
  2346. struct rtable *rt;
  2347. memset(&fl, 0, sizeof(fl));
  2348. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2349. err = ip_route_output_key(&init_net, &rt, &fl);
  2350. if (!err)
  2351. *dst = &rt->u.dst;
  2352. return err;
  2353. #else
  2354. return -ENETUNREACH;
  2355. #endif
  2356. }
  2357. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2358. struct dst_entry **dst)
  2359. {
  2360. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2361. struct flowi fl;
  2362. memset(&fl, 0, sizeof(fl));
  2363. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2364. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2365. fl.oif = dst_addr->sin6_scope_id;
  2366. *dst = ip6_route_output(&init_net, NULL, &fl);
  2367. if (*dst)
  2368. return 0;
  2369. #endif
  2370. return -ENETUNREACH;
  2371. }
  2372. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2373. int ulp_type)
  2374. {
  2375. struct cnic_dev *dev = NULL;
  2376. struct dst_entry *dst;
  2377. struct net_device *netdev = NULL;
  2378. int err = -ENETUNREACH;
  2379. if (dst_addr->sin_family == AF_INET)
  2380. err = cnic_get_v4_route(dst_addr, &dst);
  2381. else if (dst_addr->sin_family == AF_INET6) {
  2382. struct sockaddr_in6 *dst_addr6 =
  2383. (struct sockaddr_in6 *) dst_addr;
  2384. err = cnic_get_v6_route(dst_addr6, &dst);
  2385. } else
  2386. return NULL;
  2387. if (err)
  2388. return NULL;
  2389. if (!dst->dev)
  2390. goto done;
  2391. cnic_get_vlan(dst->dev, &netdev);
  2392. dev = cnic_from_netdev(netdev);
  2393. done:
  2394. dst_release(dst);
  2395. if (dev)
  2396. cnic_put(dev);
  2397. return dev;
  2398. }
  2399. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2400. {
  2401. struct cnic_dev *dev = csk->dev;
  2402. struct cnic_local *cp = dev->cnic_priv;
  2403. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2404. }
  2405. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2406. {
  2407. struct cnic_dev *dev = csk->dev;
  2408. struct cnic_local *cp = dev->cnic_priv;
  2409. int is_v6, rc = 0;
  2410. struct dst_entry *dst = NULL;
  2411. struct net_device *realdev;
  2412. u32 local_port;
  2413. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2414. saddr->remote.v6.sin6_family == AF_INET6)
  2415. is_v6 = 1;
  2416. else if (saddr->local.v4.sin_family == AF_INET &&
  2417. saddr->remote.v4.sin_family == AF_INET)
  2418. is_v6 = 0;
  2419. else
  2420. return -EINVAL;
  2421. clear_bit(SK_F_IPV6, &csk->flags);
  2422. if (is_v6) {
  2423. set_bit(SK_F_IPV6, &csk->flags);
  2424. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2425. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2426. sizeof(struct in6_addr));
  2427. csk->dst_port = saddr->remote.v6.sin6_port;
  2428. local_port = saddr->local.v6.sin6_port;
  2429. } else {
  2430. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2431. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2432. csk->dst_port = saddr->remote.v4.sin_port;
  2433. local_port = saddr->local.v4.sin_port;
  2434. }
  2435. csk->vlan_id = 0;
  2436. csk->mtu = dev->netdev->mtu;
  2437. if (dst && dst->dev) {
  2438. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2439. if (realdev == dev->netdev) {
  2440. csk->vlan_id = vlan;
  2441. csk->mtu = dst_mtu(dst);
  2442. }
  2443. }
  2444. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  2445. local_port < CNIC_LOCAL_PORT_MAX) {
  2446. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  2447. local_port = 0;
  2448. } else
  2449. local_port = 0;
  2450. if (!local_port) {
  2451. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  2452. if (local_port == -1) {
  2453. rc = -ENOMEM;
  2454. goto err_out;
  2455. }
  2456. }
  2457. csk->src_port = local_port;
  2458. err_out:
  2459. dst_release(dst);
  2460. return rc;
  2461. }
  2462. static void cnic_init_csk_state(struct cnic_sock *csk)
  2463. {
  2464. csk->state = 0;
  2465. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2466. clear_bit(SK_F_CLOSING, &csk->flags);
  2467. }
  2468. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2469. {
  2470. int err = 0;
  2471. if (!cnic_in_use(csk))
  2472. return -EINVAL;
  2473. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2474. return -EINVAL;
  2475. cnic_init_csk_state(csk);
  2476. err = cnic_get_route(csk, saddr);
  2477. if (err)
  2478. goto err_out;
  2479. err = cnic_resolve_addr(csk, saddr);
  2480. if (!err)
  2481. return 0;
  2482. err_out:
  2483. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2484. return err;
  2485. }
  2486. static int cnic_cm_abort(struct cnic_sock *csk)
  2487. {
  2488. struct cnic_local *cp = csk->dev->cnic_priv;
  2489. u32 opcode;
  2490. if (!cnic_in_use(csk))
  2491. return -EINVAL;
  2492. if (cnic_abort_prep(csk))
  2493. return cnic_cm_abort_req(csk);
  2494. /* Getting here means that we haven't started connect, or
  2495. * connect was not successful.
  2496. */
  2497. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2498. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2499. opcode = csk->state;
  2500. else
  2501. opcode = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2502. cp->close_conn(csk, opcode);
  2503. return 0;
  2504. }
  2505. static int cnic_cm_close(struct cnic_sock *csk)
  2506. {
  2507. if (!cnic_in_use(csk))
  2508. return -EINVAL;
  2509. if (cnic_close_prep(csk)) {
  2510. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2511. return cnic_cm_close_req(csk);
  2512. }
  2513. return 0;
  2514. }
  2515. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2516. u8 opcode)
  2517. {
  2518. struct cnic_ulp_ops *ulp_ops;
  2519. int ulp_type = csk->ulp_type;
  2520. rcu_read_lock();
  2521. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2522. if (ulp_ops) {
  2523. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2524. ulp_ops->cm_connect_complete(csk);
  2525. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2526. ulp_ops->cm_close_complete(csk);
  2527. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2528. ulp_ops->cm_remote_abort(csk);
  2529. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2530. ulp_ops->cm_abort_complete(csk);
  2531. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2532. ulp_ops->cm_remote_close(csk);
  2533. }
  2534. rcu_read_unlock();
  2535. }
  2536. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2537. {
  2538. if (cnic_offld_prep(csk)) {
  2539. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2540. cnic_cm_update_pg(csk);
  2541. else
  2542. cnic_cm_offload_pg(csk);
  2543. }
  2544. return 0;
  2545. }
  2546. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2547. {
  2548. struct cnic_local *cp = dev->cnic_priv;
  2549. u32 l5_cid = kcqe->pg_host_opaque;
  2550. u8 opcode = kcqe->op_code;
  2551. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2552. csk_hold(csk);
  2553. if (!cnic_in_use(csk))
  2554. goto done;
  2555. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2556. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2557. goto done;
  2558. }
  2559. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  2560. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  2561. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2562. cnic_cm_upcall(cp, csk,
  2563. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2564. goto done;
  2565. }
  2566. csk->pg_cid = kcqe->pg_cid;
  2567. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2568. cnic_cm_conn_req(csk);
  2569. done:
  2570. csk_put(csk);
  2571. }
  2572. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2573. {
  2574. struct cnic_local *cp = dev->cnic_priv;
  2575. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2576. u8 opcode = l4kcqe->op_code;
  2577. u32 l5_cid;
  2578. struct cnic_sock *csk;
  2579. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2580. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2581. cnic_cm_process_offld_pg(dev, l4kcqe);
  2582. return;
  2583. }
  2584. l5_cid = l4kcqe->conn_id;
  2585. if (opcode & 0x80)
  2586. l5_cid = l4kcqe->cid;
  2587. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2588. return;
  2589. csk = &cp->csk_tbl[l5_cid];
  2590. csk_hold(csk);
  2591. if (!cnic_in_use(csk)) {
  2592. csk_put(csk);
  2593. return;
  2594. }
  2595. switch (opcode) {
  2596. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  2597. if (l4kcqe->status != 0) {
  2598. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2599. cnic_cm_upcall(cp, csk,
  2600. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2601. }
  2602. break;
  2603. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2604. if (l4kcqe->status == 0)
  2605. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2606. smp_mb__before_clear_bit();
  2607. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2608. cnic_cm_upcall(cp, csk, opcode);
  2609. break;
  2610. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2611. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  2612. cnic_cm_upcall(cp, csk, opcode);
  2613. break;
  2614. } else if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags))
  2615. csk->state = opcode;
  2616. /* fall through */
  2617. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2618. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2619. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2620. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2621. cp->close_conn(csk, opcode);
  2622. break;
  2623. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2624. cnic_cm_upcall(cp, csk, opcode);
  2625. break;
  2626. }
  2627. csk_put(csk);
  2628. }
  2629. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2630. {
  2631. struct cnic_dev *dev = data;
  2632. int i;
  2633. for (i = 0; i < num; i++)
  2634. cnic_cm_process_kcqe(dev, kcqe[i]);
  2635. }
  2636. static struct cnic_ulp_ops cm_ulp_ops = {
  2637. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2638. };
  2639. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2640. {
  2641. struct cnic_local *cp = dev->cnic_priv;
  2642. kfree(cp->csk_tbl);
  2643. cp->csk_tbl = NULL;
  2644. cnic_free_id_tbl(&cp->csk_port_tbl);
  2645. }
  2646. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2647. {
  2648. struct cnic_local *cp = dev->cnic_priv;
  2649. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2650. GFP_KERNEL);
  2651. if (!cp->csk_tbl)
  2652. return -ENOMEM;
  2653. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2654. CNIC_LOCAL_PORT_MIN)) {
  2655. cnic_cm_free_mem(dev);
  2656. return -ENOMEM;
  2657. }
  2658. return 0;
  2659. }
  2660. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2661. {
  2662. if ((opcode == csk->state) ||
  2663. (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED &&
  2664. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)) {
  2665. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags))
  2666. return 1;
  2667. }
  2668. /* 57710+ only workaround to handle unsolicited RESET_COMP
  2669. * which will be treated like a RESET RCVD notification
  2670. * which triggers the clean up procedure
  2671. */
  2672. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  2673. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  2674. csk->state = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  2675. return 1;
  2676. }
  2677. }
  2678. return 0;
  2679. }
  2680. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2681. {
  2682. struct cnic_dev *dev = csk->dev;
  2683. struct cnic_local *cp = dev->cnic_priv;
  2684. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2685. cnic_close_conn(csk);
  2686. cnic_cm_upcall(cp, csk, opcode);
  2687. }
  2688. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2689. {
  2690. }
  2691. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2692. {
  2693. u32 seed;
  2694. get_random_bytes(&seed, 4);
  2695. cnic_ctx_wr(dev, 45, 0, seed);
  2696. return 0;
  2697. }
  2698. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2699. {
  2700. struct cnic_dev *dev = csk->dev;
  2701. struct cnic_local *cp = dev->cnic_priv;
  2702. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2703. union l5cm_specific_data l5_data;
  2704. u32 cmd = 0;
  2705. int close_complete = 0;
  2706. switch (opcode) {
  2707. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2708. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2709. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2710. if (cnic_ready_to_close(csk, opcode))
  2711. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2712. break;
  2713. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2714. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2715. break;
  2716. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2717. close_complete = 1;
  2718. break;
  2719. }
  2720. if (cmd) {
  2721. memset(&l5_data, 0, sizeof(l5_data));
  2722. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2723. &l5_data);
  2724. } else if (close_complete) {
  2725. ctx->timestamp = jiffies;
  2726. cnic_close_conn(csk);
  2727. cnic_cm_upcall(cp, csk, csk->state);
  2728. }
  2729. }
  2730. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2731. {
  2732. }
  2733. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2734. {
  2735. struct cnic_local *cp = dev->cnic_priv;
  2736. int func = CNIC_FUNC(cp);
  2737. cnic_init_bnx2x_mac(dev);
  2738. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2739. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2740. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(func), 0);
  2741. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2742. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(func), 1);
  2743. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2744. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(func),
  2745. DEF_MAX_DA_COUNT);
  2746. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2747. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(func), DEF_TTL);
  2748. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2749. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(func), DEF_TOS);
  2750. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2751. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(func), 2);
  2752. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2753. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(func), DEF_SWS_TIMER);
  2754. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(func),
  2755. DEF_MAX_CWND);
  2756. return 0;
  2757. }
  2758. static int cnic_cm_open(struct cnic_dev *dev)
  2759. {
  2760. struct cnic_local *cp = dev->cnic_priv;
  2761. int err;
  2762. err = cnic_cm_alloc_mem(dev);
  2763. if (err)
  2764. return err;
  2765. err = cp->start_cm(dev);
  2766. if (err)
  2767. goto err_out;
  2768. dev->cm_create = cnic_cm_create;
  2769. dev->cm_destroy = cnic_cm_destroy;
  2770. dev->cm_connect = cnic_cm_connect;
  2771. dev->cm_abort = cnic_cm_abort;
  2772. dev->cm_close = cnic_cm_close;
  2773. dev->cm_select_dev = cnic_cm_select_dev;
  2774. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2775. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2776. return 0;
  2777. err_out:
  2778. cnic_cm_free_mem(dev);
  2779. return err;
  2780. }
  2781. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2782. {
  2783. struct cnic_local *cp = dev->cnic_priv;
  2784. int i;
  2785. cp->stop_cm(dev);
  2786. if (!cp->csk_tbl)
  2787. return 0;
  2788. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2789. struct cnic_sock *csk = &cp->csk_tbl[i];
  2790. clear_bit(SK_F_INUSE, &csk->flags);
  2791. cnic_cm_cleanup(csk);
  2792. }
  2793. cnic_cm_free_mem(dev);
  2794. return 0;
  2795. }
  2796. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2797. {
  2798. u32 cid_addr;
  2799. int i;
  2800. cid_addr = GET_CID_ADDR(cid);
  2801. for (i = 0; i < CTX_SIZE; i += 4)
  2802. cnic_ctx_wr(dev, cid_addr, i, 0);
  2803. }
  2804. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2805. {
  2806. struct cnic_local *cp = dev->cnic_priv;
  2807. int ret = 0, i;
  2808. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2809. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2810. return 0;
  2811. for (i = 0; i < cp->ctx_blks; i++) {
  2812. int j;
  2813. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2814. u32 val;
  2815. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2816. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2817. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2818. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2819. (u64) cp->ctx_arr[i].mapping >> 32);
  2820. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2821. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2822. for (j = 0; j < 10; j++) {
  2823. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2824. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2825. break;
  2826. udelay(5);
  2827. }
  2828. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2829. ret = -EBUSY;
  2830. break;
  2831. }
  2832. }
  2833. return ret;
  2834. }
  2835. static void cnic_free_irq(struct cnic_dev *dev)
  2836. {
  2837. struct cnic_local *cp = dev->cnic_priv;
  2838. struct cnic_eth_dev *ethdev = cp->ethdev;
  2839. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2840. cp->disable_int_sync(dev);
  2841. tasklet_disable(&cp->cnic_irq_task);
  2842. free_irq(ethdev->irq_arr[0].vector, dev);
  2843. }
  2844. }
  2845. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2846. {
  2847. struct cnic_local *cp = dev->cnic_priv;
  2848. struct cnic_eth_dev *ethdev = cp->ethdev;
  2849. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2850. int err, i = 0;
  2851. int sblk_num = cp->status_blk_num;
  2852. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  2853. BNX2_HC_SB_CONFIG_1;
  2854. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  2855. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  2856. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  2857. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  2858. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  2859. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  2860. (unsigned long) dev);
  2861. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  2862. "cnic", dev);
  2863. if (err) {
  2864. tasklet_disable(&cp->cnic_irq_task);
  2865. return err;
  2866. }
  2867. while (cp->status_blk.bnx2->status_completion_producer_index &&
  2868. i < 10) {
  2869. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  2870. 1 << (11 + sblk_num));
  2871. udelay(10);
  2872. i++;
  2873. barrier();
  2874. }
  2875. if (cp->status_blk.bnx2->status_completion_producer_index) {
  2876. cnic_free_irq(dev);
  2877. goto failed;
  2878. }
  2879. } else {
  2880. struct status_block *sblk = cp->status_blk.gen;
  2881. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  2882. int i = 0;
  2883. while (sblk->status_completion_producer_index && i < 10) {
  2884. CNIC_WR(dev, BNX2_HC_COMMAND,
  2885. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2886. udelay(10);
  2887. i++;
  2888. barrier();
  2889. }
  2890. if (sblk->status_completion_producer_index)
  2891. goto failed;
  2892. }
  2893. return 0;
  2894. failed:
  2895. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  2896. return -EBUSY;
  2897. }
  2898. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  2899. {
  2900. struct cnic_local *cp = dev->cnic_priv;
  2901. struct cnic_eth_dev *ethdev = cp->ethdev;
  2902. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2903. return;
  2904. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2905. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2906. }
  2907. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  2908. {
  2909. struct cnic_local *cp = dev->cnic_priv;
  2910. struct cnic_eth_dev *ethdev = cp->ethdev;
  2911. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2912. return;
  2913. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2914. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2915. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  2916. synchronize_irq(ethdev->irq_arr[0].vector);
  2917. }
  2918. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  2919. {
  2920. struct cnic_local *cp = dev->cnic_priv;
  2921. struct cnic_eth_dev *ethdev = cp->ethdev;
  2922. u32 cid_addr, tx_cid, sb_id;
  2923. u32 val, offset0, offset1, offset2, offset3;
  2924. int i;
  2925. struct tx_bd *txbd;
  2926. dma_addr_t buf_map;
  2927. struct status_block *s_blk = cp->status_blk.gen;
  2928. sb_id = cp->status_blk_num;
  2929. tx_cid = 20;
  2930. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  2931. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2932. struct status_block_msix *sblk = cp->status_blk.bnx2;
  2933. tx_cid = TX_TSS_CID + sb_id - 1;
  2934. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  2935. (TX_TSS_CID << 7));
  2936. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  2937. }
  2938. cp->tx_cons = *cp->tx_cons_ptr;
  2939. cid_addr = GET_CID_ADDR(tx_cid);
  2940. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  2941. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  2942. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  2943. cnic_ctx_wr(dev, cid_addr2, i, 0);
  2944. offset0 = BNX2_L2CTX_TYPE_XI;
  2945. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  2946. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  2947. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  2948. } else {
  2949. cnic_init_context(dev, tx_cid);
  2950. cnic_init_context(dev, tx_cid + 1);
  2951. offset0 = BNX2_L2CTX_TYPE;
  2952. offset1 = BNX2_L2CTX_CMD_TYPE;
  2953. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  2954. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  2955. }
  2956. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  2957. cnic_ctx_wr(dev, cid_addr, offset0, val);
  2958. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  2959. cnic_ctx_wr(dev, cid_addr, offset1, val);
  2960. txbd = (struct tx_bd *) cp->l2_ring;
  2961. buf_map = cp->l2_buf_map;
  2962. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  2963. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  2964. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  2965. }
  2966. val = (u64) cp->l2_ring_map >> 32;
  2967. cnic_ctx_wr(dev, cid_addr, offset2, val);
  2968. txbd->tx_bd_haddr_hi = val;
  2969. val = (u64) cp->l2_ring_map & 0xffffffff;
  2970. cnic_ctx_wr(dev, cid_addr, offset3, val);
  2971. txbd->tx_bd_haddr_lo = val;
  2972. }
  2973. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  2974. {
  2975. struct cnic_local *cp = dev->cnic_priv;
  2976. struct cnic_eth_dev *ethdev = cp->ethdev;
  2977. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  2978. int i;
  2979. struct rx_bd *rxbd;
  2980. struct status_block *s_blk = cp->status_blk.gen;
  2981. sb_id = cp->status_blk_num;
  2982. cnic_init_context(dev, 2);
  2983. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  2984. coal_reg = BNX2_HC_COMMAND;
  2985. coal_val = CNIC_RD(dev, coal_reg);
  2986. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2987. struct status_block_msix *sblk = cp->status_blk.bnx2;
  2988. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  2989. coal_reg = BNX2_HC_COALESCE_NOW;
  2990. coal_val = 1 << (11 + sb_id);
  2991. }
  2992. i = 0;
  2993. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  2994. CNIC_WR(dev, coal_reg, coal_val);
  2995. udelay(10);
  2996. i++;
  2997. barrier();
  2998. }
  2999. cp->rx_cons = *cp->rx_cons_ptr;
  3000. cid_addr = GET_CID_ADDR(2);
  3001. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3002. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3003. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3004. if (sb_id == 0)
  3005. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3006. else
  3007. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3008. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3009. rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
  3010. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3011. dma_addr_t buf_map;
  3012. int n = (i % cp->l2_rx_ring_size) + 1;
  3013. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3014. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3015. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3016. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3017. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3018. }
  3019. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  3020. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3021. rxbd->rx_bd_haddr_hi = val;
  3022. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3023. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3024. rxbd->rx_bd_haddr_lo = val;
  3025. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3026. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3027. }
  3028. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3029. {
  3030. struct kwqe *wqes[1], l2kwqe;
  3031. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3032. wqes[0] = &l2kwqe;
  3033. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  3034. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3035. KWQE_OPCODE_SHIFT) | 2;
  3036. dev->submit_kwqes(dev, wqes, 1);
  3037. }
  3038. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3039. {
  3040. struct cnic_local *cp = dev->cnic_priv;
  3041. u32 val;
  3042. val = cp->func << 2;
  3043. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3044. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3045. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3046. dev->mac_addr[0] = (u8) (val >> 8);
  3047. dev->mac_addr[1] = (u8) val;
  3048. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3049. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3050. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3051. dev->mac_addr[2] = (u8) (val >> 24);
  3052. dev->mac_addr[3] = (u8) (val >> 16);
  3053. dev->mac_addr[4] = (u8) (val >> 8);
  3054. dev->mac_addr[5] = (u8) val;
  3055. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3056. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3057. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3058. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3059. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3060. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3061. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3062. }
  3063. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3064. {
  3065. struct cnic_local *cp = dev->cnic_priv;
  3066. struct cnic_eth_dev *ethdev = cp->ethdev;
  3067. struct status_block *sblk = cp->status_blk.gen;
  3068. u32 val;
  3069. int err;
  3070. cnic_set_bnx2_mac(dev);
  3071. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3072. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3073. if (BCM_PAGE_BITS > 12)
  3074. val |= (12 - 8) << 4;
  3075. else
  3076. val |= (BCM_PAGE_BITS - 8) << 4;
  3077. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3078. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3079. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3080. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3081. err = cnic_setup_5709_context(dev, 1);
  3082. if (err)
  3083. return err;
  3084. cnic_init_context(dev, KWQ_CID);
  3085. cnic_init_context(dev, KCQ_CID);
  3086. cp->kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3087. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3088. cp->max_kwq_idx = MAX_KWQ_IDX;
  3089. cp->kwq_prod_idx = 0;
  3090. cp->kwq_con_idx = 0;
  3091. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3092. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3093. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3094. else
  3095. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3096. /* Initialize the kernel work queue context. */
  3097. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3098. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3099. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3100. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3101. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3102. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3103. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3104. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3105. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3106. val = (u32) cp->kwq_info.pgtbl_map;
  3107. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3108. cp->kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3109. cp->kcq_io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3110. cp->kcq_prod_idx = 0;
  3111. /* Initialize the kernel complete queue context. */
  3112. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3113. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3114. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3115. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3116. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3117. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3118. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3119. val = (u32) ((u64) cp->kcq_info.pgtbl_map >> 32);
  3120. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3121. val = (u32) cp->kcq_info.pgtbl_map;
  3122. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3123. cp->int_num = 0;
  3124. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3125. u32 sb_id = cp->status_blk_num;
  3126. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3127. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3128. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3129. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3130. }
  3131. /* Enable Commnad Scheduler notification when we write to the
  3132. * host producer index of the kernel contexts. */
  3133. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3134. /* Enable Command Scheduler notification when we write to either
  3135. * the Send Queue or Receive Queue producer indexes of the kernel
  3136. * bypass contexts. */
  3137. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3138. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3139. /* Notify COM when the driver post an application buffer. */
  3140. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3141. /* Set the CP and COM doorbells. These two processors polls the
  3142. * doorbell for a non zero value before running. This must be done
  3143. * after setting up the kernel queue contexts. */
  3144. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3145. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3146. cnic_init_bnx2_tx_ring(dev);
  3147. cnic_init_bnx2_rx_ring(dev);
  3148. err = cnic_init_bnx2_irq(dev);
  3149. if (err) {
  3150. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3151. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3152. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3153. return err;
  3154. }
  3155. return 0;
  3156. }
  3157. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3158. {
  3159. struct cnic_local *cp = dev->cnic_priv;
  3160. struct cnic_eth_dev *ethdev = cp->ethdev;
  3161. u32 start_offset = ethdev->ctx_tbl_offset;
  3162. int i;
  3163. for (i = 0; i < cp->ctx_blks; i++) {
  3164. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3165. dma_addr_t map = ctx->mapping;
  3166. if (cp->ctx_align) {
  3167. unsigned long mask = cp->ctx_align - 1;
  3168. map = (map + mask) & ~mask;
  3169. }
  3170. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3171. }
  3172. }
  3173. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3174. {
  3175. struct cnic_local *cp = dev->cnic_priv;
  3176. struct cnic_eth_dev *ethdev = cp->ethdev;
  3177. int err = 0;
  3178. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3179. (unsigned long) dev);
  3180. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3181. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  3182. "cnic", dev);
  3183. if (err)
  3184. tasklet_disable(&cp->cnic_irq_task);
  3185. }
  3186. return err;
  3187. }
  3188. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3189. {
  3190. struct cnic_local *cp = dev->cnic_priv;
  3191. u8 sb_id = cp->status_blk_num;
  3192. int port = CNIC_PORT(cp);
  3193. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3194. CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
  3195. HC_INDEX_C_ISCSI_EQ_CONS),
  3196. 64 / 12);
  3197. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3198. CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
  3199. HC_INDEX_C_ISCSI_EQ_CONS), 0);
  3200. }
  3201. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3202. {
  3203. }
  3204. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev)
  3205. {
  3206. struct cnic_local *cp = dev->cnic_priv;
  3207. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) cp->l2_ring;
  3208. struct eth_context *context;
  3209. struct regpair context_addr;
  3210. dma_addr_t buf_map;
  3211. int func = CNIC_FUNC(cp);
  3212. int port = CNIC_PORT(cp);
  3213. int i;
  3214. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3215. u32 val;
  3216. memset(txbd, 0, BCM_PAGE_SIZE);
  3217. buf_map = cp->l2_buf_map;
  3218. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3219. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3220. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3221. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3222. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3223. reg_bd->addr_hi = start_bd->addr_hi;
  3224. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3225. start_bd->nbytes = cpu_to_le16(0x10);
  3226. start_bd->nbd = cpu_to_le16(3);
  3227. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3228. start_bd->general_data = (UNICAST_ADDRESS <<
  3229. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3230. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3231. }
  3232. context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 1, &context_addr);
  3233. val = (u64) cp->l2_ring_map >> 32;
  3234. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3235. context->xstorm_st_context.tx_bd_page_base_hi = val;
  3236. val = (u64) cp->l2_ring_map & 0xffffffff;
  3237. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3238. context->xstorm_st_context.tx_bd_page_base_lo = val;
  3239. context->cstorm_st_context.sb_index_number =
  3240. HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS;
  3241. context->cstorm_st_context.status_block_id = BNX2X_DEF_SB_ID;
  3242. context->xstorm_st_context.statistics_data = (cli |
  3243. XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
  3244. context->xstorm_ag_context.cdu_reserved =
  3245. CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
  3246. CDU_REGION_NUMBER_XCM_AG,
  3247. ETH_CONNECTION_TYPE);
  3248. /* reset xstorm per client statistics */
  3249. val = BAR_XSTRORM_INTMEM +
  3250. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3251. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3252. CNIC_WR(dev, val + i * 4, 0);
  3253. cp->tx_cons_ptr =
  3254. &cp->bnx2x_def_status_blk->c_def_status_block.index_values[
  3255. HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS];
  3256. }
  3257. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev)
  3258. {
  3259. struct cnic_local *cp = dev->cnic_priv;
  3260. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (cp->l2_ring +
  3261. BCM_PAGE_SIZE);
  3262. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3263. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  3264. struct eth_context *context;
  3265. struct regpair context_addr;
  3266. int i;
  3267. int port = CNIC_PORT(cp);
  3268. int func = CNIC_FUNC(cp);
  3269. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3270. u32 val;
  3271. struct tstorm_eth_client_config tstorm_client = {0};
  3272. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3273. dma_addr_t buf_map;
  3274. int n = (i % cp->l2_rx_ring_size) + 1;
  3275. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3276. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3277. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3278. }
  3279. context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 0, &context_addr);
  3280. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  3281. rxbd->addr_hi = cpu_to_le32(val);
  3282. context->ustorm_st_context.common.bd_page_base_hi = val;
  3283. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3284. rxbd->addr_lo = cpu_to_le32(val);
  3285. context->ustorm_st_context.common.bd_page_base_lo = val;
  3286. context->ustorm_st_context.common.sb_index_numbers =
  3287. BNX2X_ISCSI_RX_SB_INDEX_NUM;
  3288. context->ustorm_st_context.common.clientId = cli;
  3289. context->ustorm_st_context.common.status_block_id = BNX2X_DEF_SB_ID;
  3290. context->ustorm_st_context.common.flags =
  3291. USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS;
  3292. context->ustorm_st_context.common.statistics_counter_id = cli;
  3293. context->ustorm_st_context.common.mc_alignment_log_size = 0;
  3294. context->ustorm_st_context.common.bd_buff_size =
  3295. cp->l2_single_buf_size;
  3296. context->ustorm_ag_context.cdu_usage =
  3297. CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
  3298. CDU_REGION_NUMBER_UCM_AG,
  3299. ETH_CONNECTION_TYPE);
  3300. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3301. val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3302. rxcqe->addr_hi = cpu_to_le32(val);
  3303. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3304. USTORM_CQE_PAGE_BASE_OFFSET(port, cli) + 4, val);
  3305. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3306. USTORM_CQE_PAGE_NEXT_OFFSET(port, cli) + 4, val);
  3307. val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3308. rxcqe->addr_lo = cpu_to_le32(val);
  3309. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3310. USTORM_CQE_PAGE_BASE_OFFSET(port, cli), val);
  3311. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3312. USTORM_CQE_PAGE_NEXT_OFFSET(port, cli), val);
  3313. /* client tstorm info */
  3314. tstorm_client.mtu = cp->l2_single_buf_size - 14;
  3315. tstorm_client.config_flags =
  3316. (TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE |
  3317. TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE);
  3318. tstorm_client.statistics_counter_id = cli;
  3319. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3320. TSTORM_CLIENT_CONFIG_OFFSET(port, cli),
  3321. ((u32 *)&tstorm_client)[0]);
  3322. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3323. TSTORM_CLIENT_CONFIG_OFFSET(port, cli) + 4,
  3324. ((u32 *)&tstorm_client)[1]);
  3325. /* reset tstorm per client statistics */
  3326. val = BAR_TSTRORM_INTMEM +
  3327. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3328. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3329. CNIC_WR(dev, val + i * 4, 0);
  3330. /* reset ustorm per client statistics */
  3331. val = BAR_USTRORM_INTMEM +
  3332. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3333. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3334. CNIC_WR(dev, val + i * 4, 0);
  3335. cp->rx_cons_ptr =
  3336. &cp->bnx2x_def_status_blk->u_def_status_block.index_values[
  3337. HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS];
  3338. }
  3339. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3340. {
  3341. struct cnic_local *cp = dev->cnic_priv;
  3342. u32 base, addr, val;
  3343. int port = CNIC_PORT(cp);
  3344. dev->max_iscsi_conn = 0;
  3345. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3346. if (base < 0xa0000 || base >= 0xc0000)
  3347. return;
  3348. addr = BNX2X_SHMEM_ADDR(base,
  3349. dev_info.port_hw_config[port].iscsi_mac_upper);
  3350. val = CNIC_RD(dev, addr);
  3351. dev->mac_addr[0] = (u8) (val >> 8);
  3352. dev->mac_addr[1] = (u8) val;
  3353. addr = BNX2X_SHMEM_ADDR(base,
  3354. dev_info.port_hw_config[port].iscsi_mac_lower);
  3355. val = CNIC_RD(dev, addr);
  3356. dev->mac_addr[2] = (u8) (val >> 24);
  3357. dev->mac_addr[3] = (u8) (val >> 16);
  3358. dev->mac_addr[4] = (u8) (val >> 8);
  3359. dev->mac_addr[5] = (u8) val;
  3360. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3361. val = CNIC_RD(dev, addr);
  3362. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3363. u16 val16;
  3364. addr = BNX2X_SHMEM_ADDR(base,
  3365. drv_lic_key[port].max_iscsi_init_conn);
  3366. val16 = CNIC_RD16(dev, addr);
  3367. if (val16)
  3368. val16 ^= 0x1e1e;
  3369. dev->max_iscsi_conn = val16;
  3370. }
  3371. if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
  3372. int func = CNIC_FUNC(cp);
  3373. addr = BNX2X_SHMEM_ADDR(base,
  3374. mf_cfg.func_mf_config[func].e1hov_tag);
  3375. val = CNIC_RD(dev, addr);
  3376. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3377. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3378. addr = BNX2X_SHMEM_ADDR(base,
  3379. mf_cfg.func_mf_config[func].config);
  3380. val = CNIC_RD(dev, addr);
  3381. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3382. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3383. dev->max_iscsi_conn = 0;
  3384. }
  3385. }
  3386. }
  3387. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3388. {
  3389. struct cnic_local *cp = dev->cnic_priv;
  3390. int func = CNIC_FUNC(cp), ret, i;
  3391. int port = CNIC_PORT(cp);
  3392. u16 eq_idx;
  3393. u8 sb_id = cp->status_blk_num;
  3394. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3395. BNX2X_ISCSI_START_CID);
  3396. if (ret)
  3397. return -ENOMEM;
  3398. cp->kcq_io_addr = BAR_CSTRORM_INTMEM +
  3399. CSTORM_ISCSI_EQ_PROD_OFFSET(func, 0);
  3400. cp->kcq_prod_idx = 0;
  3401. cnic_get_bnx2x_iscsi_info(dev);
  3402. /* Only 1 EQ */
  3403. CNIC_WR16(dev, cp->kcq_io_addr, MAX_KCQ_IDX);
  3404. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3405. CSTORM_ISCSI_EQ_CONS_OFFSET(func, 0), 0);
  3406. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3407. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0),
  3408. cp->kcq_info.pg_map_arr[1] & 0xffffffff);
  3409. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3410. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0) + 4,
  3411. (u64) cp->kcq_info.pg_map_arr[1] >> 32);
  3412. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3413. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0),
  3414. cp->kcq_info.pg_map_arr[0] & 0xffffffff);
  3415. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3416. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0) + 4,
  3417. (u64) cp->kcq_info.pg_map_arr[0] >> 32);
  3418. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3419. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(func, 0), 1);
  3420. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3421. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(func, 0), cp->status_blk_num);
  3422. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3423. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(func, 0),
  3424. HC_INDEX_C_ISCSI_EQ_CONS);
  3425. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3426. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3427. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i),
  3428. cp->conn_buf_info.pgtbl[2 * i]);
  3429. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3430. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i) + 4,
  3431. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3432. }
  3433. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3434. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func),
  3435. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3436. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3437. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func) + 4,
  3438. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3439. cnic_setup_bnx2x_context(dev);
  3440. eq_idx = CNIC_RD16(dev, BAR_CSTRORM_INTMEM +
  3441. CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
  3442. offsetof(struct cstorm_status_block_c,
  3443. index_values[HC_INDEX_C_ISCSI_EQ_CONS]));
  3444. if (eq_idx != 0) {
  3445. netdev_err(dev->netdev, "EQ cons index %x != 0\n", eq_idx);
  3446. return -EBUSY;
  3447. }
  3448. ret = cnic_init_bnx2x_irq(dev);
  3449. if (ret)
  3450. return ret;
  3451. cnic_init_bnx2x_tx_ring(dev);
  3452. cnic_init_bnx2x_rx_ring(dev);
  3453. return 0;
  3454. }
  3455. static void cnic_init_rings(struct cnic_dev *dev)
  3456. {
  3457. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3458. cnic_init_bnx2_tx_ring(dev);
  3459. cnic_init_bnx2_rx_ring(dev);
  3460. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3461. struct cnic_local *cp = dev->cnic_priv;
  3462. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3463. union l5cm_specific_data l5_data;
  3464. struct ustorm_eth_rx_producers rx_prods = {0};
  3465. u32 off, i;
  3466. rx_prods.bd_prod = 0;
  3467. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3468. barrier();
  3469. off = BAR_USTRORM_INTMEM +
  3470. USTORM_RX_PRODS_OFFSET(CNIC_PORT(cp), cli);
  3471. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3472. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  3473. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3474. cnic_init_bnx2x_tx_ring(dev);
  3475. cnic_init_bnx2x_rx_ring(dev);
  3476. l5_data.phy_address.lo = cli;
  3477. l5_data.phy_address.hi = 0;
  3478. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3479. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3480. i = 0;
  3481. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3482. ++i < 10)
  3483. msleep(1);
  3484. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3485. netdev_err(dev->netdev,
  3486. "iSCSI CLIENT_SETUP did not complete\n");
  3487. cnic_kwq_completion(dev, 1);
  3488. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3489. }
  3490. }
  3491. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3492. {
  3493. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3494. cnic_shutdown_bnx2_rx_ring(dev);
  3495. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3496. struct cnic_local *cp = dev->cnic_priv;
  3497. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3498. union l5cm_specific_data l5_data;
  3499. int i;
  3500. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3501. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3502. l5_data.phy_address.lo = cli;
  3503. l5_data.phy_address.hi = 0;
  3504. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  3505. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3506. i = 0;
  3507. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3508. ++i < 10)
  3509. msleep(1);
  3510. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3511. netdev_err(dev->netdev,
  3512. "iSCSI CLIENT_HALT did not complete\n");
  3513. cnic_kwq_completion(dev, 1);
  3514. memset(&l5_data, 0, sizeof(l5_data));
  3515. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
  3516. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE |
  3517. (1 << SPE_HDR_COMMON_RAMROD_SHIFT), &l5_data);
  3518. msleep(10);
  3519. }
  3520. }
  3521. static int cnic_register_netdev(struct cnic_dev *dev)
  3522. {
  3523. struct cnic_local *cp = dev->cnic_priv;
  3524. struct cnic_eth_dev *ethdev = cp->ethdev;
  3525. int err;
  3526. if (!ethdev)
  3527. return -ENODEV;
  3528. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3529. return 0;
  3530. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3531. if (err)
  3532. netdev_err(dev->netdev, "register_cnic failed\n");
  3533. return err;
  3534. }
  3535. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3536. {
  3537. struct cnic_local *cp = dev->cnic_priv;
  3538. struct cnic_eth_dev *ethdev = cp->ethdev;
  3539. if (!ethdev)
  3540. return;
  3541. ethdev->drv_unregister_cnic(dev->netdev);
  3542. }
  3543. static int cnic_start_hw(struct cnic_dev *dev)
  3544. {
  3545. struct cnic_local *cp = dev->cnic_priv;
  3546. struct cnic_eth_dev *ethdev = cp->ethdev;
  3547. int err;
  3548. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3549. return -EALREADY;
  3550. dev->regview = ethdev->io_base;
  3551. cp->chip_id = ethdev->chip_id;
  3552. pci_dev_get(dev->pcidev);
  3553. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3554. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  3555. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3556. err = cp->alloc_resc(dev);
  3557. if (err) {
  3558. netdev_err(dev->netdev, "allocate resource failure\n");
  3559. goto err1;
  3560. }
  3561. err = cp->start_hw(dev);
  3562. if (err)
  3563. goto err1;
  3564. err = cnic_cm_open(dev);
  3565. if (err)
  3566. goto err1;
  3567. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3568. cp->enable_int(dev);
  3569. return 0;
  3570. err1:
  3571. cp->free_resc(dev);
  3572. pci_dev_put(dev->pcidev);
  3573. return err;
  3574. }
  3575. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3576. {
  3577. cnic_disable_bnx2_int_sync(dev);
  3578. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3579. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3580. cnic_init_context(dev, KWQ_CID);
  3581. cnic_init_context(dev, KCQ_CID);
  3582. cnic_setup_5709_context(dev, 0);
  3583. cnic_free_irq(dev);
  3584. cnic_free_resc(dev);
  3585. }
  3586. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3587. {
  3588. struct cnic_local *cp = dev->cnic_priv;
  3589. u8 sb_id = cp->status_blk_num;
  3590. int port = CNIC_PORT(cp);
  3591. cnic_free_irq(dev);
  3592. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3593. CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
  3594. offsetof(struct cstorm_status_block_c,
  3595. index_values[HC_INDEX_C_ISCSI_EQ_CONS]),
  3596. 0);
  3597. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3598. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->func, 0), 0);
  3599. CNIC_WR16(dev, cp->kcq_io_addr, 0);
  3600. cnic_free_resc(dev);
  3601. }
  3602. static void cnic_stop_hw(struct cnic_dev *dev)
  3603. {
  3604. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3605. struct cnic_local *cp = dev->cnic_priv;
  3606. int i = 0;
  3607. /* Need to wait for the ring shutdown event to complete
  3608. * before clearing the CNIC_UP flag.
  3609. */
  3610. while (cp->uio_dev != -1 && i < 15) {
  3611. msleep(100);
  3612. i++;
  3613. }
  3614. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3615. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3616. synchronize_rcu();
  3617. cnic_cm_shutdown(dev);
  3618. cp->stop_hw(dev);
  3619. pci_dev_put(dev->pcidev);
  3620. }
  3621. }
  3622. static void cnic_free_dev(struct cnic_dev *dev)
  3623. {
  3624. int i = 0;
  3625. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3626. msleep(100);
  3627. i++;
  3628. }
  3629. if (atomic_read(&dev->ref_count) != 0)
  3630. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  3631. netdev_info(dev->netdev, "Removed CNIC device\n");
  3632. dev_put(dev->netdev);
  3633. kfree(dev);
  3634. }
  3635. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3636. struct pci_dev *pdev)
  3637. {
  3638. struct cnic_dev *cdev;
  3639. struct cnic_local *cp;
  3640. int alloc_size;
  3641. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3642. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3643. if (cdev == NULL) {
  3644. netdev_err(dev, "allocate dev struct failure\n");
  3645. return NULL;
  3646. }
  3647. cdev->netdev = dev;
  3648. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3649. cdev->register_device = cnic_register_device;
  3650. cdev->unregister_device = cnic_unregister_device;
  3651. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3652. cp = cdev->cnic_priv;
  3653. cp->dev = cdev;
  3654. cp->uio_dev = -1;
  3655. cp->l2_single_buf_size = 0x400;
  3656. cp->l2_rx_ring_size = 3;
  3657. spin_lock_init(&cp->cnic_ulp_lock);
  3658. netdev_info(dev, "Added CNIC device\n");
  3659. return cdev;
  3660. }
  3661. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3662. {
  3663. struct pci_dev *pdev;
  3664. struct cnic_dev *cdev;
  3665. struct cnic_local *cp;
  3666. struct cnic_eth_dev *ethdev = NULL;
  3667. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3668. probe = symbol_get(bnx2_cnic_probe);
  3669. if (probe) {
  3670. ethdev = (*probe)(dev);
  3671. symbol_put(bnx2_cnic_probe);
  3672. }
  3673. if (!ethdev)
  3674. return NULL;
  3675. pdev = ethdev->pdev;
  3676. if (!pdev)
  3677. return NULL;
  3678. dev_hold(dev);
  3679. pci_dev_get(pdev);
  3680. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3681. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3682. u8 rev;
  3683. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3684. if (rev < 0x10) {
  3685. pci_dev_put(pdev);
  3686. goto cnic_err;
  3687. }
  3688. }
  3689. pci_dev_put(pdev);
  3690. cdev = cnic_alloc_dev(dev, pdev);
  3691. if (cdev == NULL)
  3692. goto cnic_err;
  3693. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3694. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3695. cp = cdev->cnic_priv;
  3696. cp->ethdev = ethdev;
  3697. cdev->pcidev = pdev;
  3698. cp->cnic_ops = &cnic_bnx2_ops;
  3699. cp->start_hw = cnic_start_bnx2_hw;
  3700. cp->stop_hw = cnic_stop_bnx2_hw;
  3701. cp->setup_pgtbl = cnic_setup_page_tbl;
  3702. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3703. cp->free_resc = cnic_free_resc;
  3704. cp->start_cm = cnic_cm_init_bnx2_hw;
  3705. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3706. cp->enable_int = cnic_enable_bnx2_int;
  3707. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3708. cp->close_conn = cnic_close_bnx2_conn;
  3709. cp->next_idx = cnic_bnx2_next_idx;
  3710. cp->hw_idx = cnic_bnx2_hw_idx;
  3711. return cdev;
  3712. cnic_err:
  3713. dev_put(dev);
  3714. return NULL;
  3715. }
  3716. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3717. {
  3718. struct pci_dev *pdev;
  3719. struct cnic_dev *cdev;
  3720. struct cnic_local *cp;
  3721. struct cnic_eth_dev *ethdev = NULL;
  3722. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3723. probe = symbol_get(bnx2x_cnic_probe);
  3724. if (probe) {
  3725. ethdev = (*probe)(dev);
  3726. symbol_put(bnx2x_cnic_probe);
  3727. }
  3728. if (!ethdev)
  3729. return NULL;
  3730. pdev = ethdev->pdev;
  3731. if (!pdev)
  3732. return NULL;
  3733. dev_hold(dev);
  3734. cdev = cnic_alloc_dev(dev, pdev);
  3735. if (cdev == NULL) {
  3736. dev_put(dev);
  3737. return NULL;
  3738. }
  3739. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3740. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3741. cp = cdev->cnic_priv;
  3742. cp->ethdev = ethdev;
  3743. cdev->pcidev = pdev;
  3744. cp->cnic_ops = &cnic_bnx2x_ops;
  3745. cp->start_hw = cnic_start_bnx2x_hw;
  3746. cp->stop_hw = cnic_stop_bnx2x_hw;
  3747. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3748. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3749. cp->free_resc = cnic_free_resc;
  3750. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3751. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3752. cp->enable_int = cnic_enable_bnx2x_int;
  3753. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3754. cp->ack_int = cnic_ack_bnx2x_msix;
  3755. cp->close_conn = cnic_close_bnx2x_conn;
  3756. cp->next_idx = cnic_bnx2x_next_idx;
  3757. cp->hw_idx = cnic_bnx2x_hw_idx;
  3758. return cdev;
  3759. }
  3760. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3761. {
  3762. struct ethtool_drvinfo drvinfo;
  3763. struct cnic_dev *cdev = NULL;
  3764. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3765. memset(&drvinfo, 0, sizeof(drvinfo));
  3766. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3767. if (!strcmp(drvinfo.driver, "bnx2"))
  3768. cdev = init_bnx2_cnic(dev);
  3769. if (!strcmp(drvinfo.driver, "bnx2x"))
  3770. cdev = init_bnx2x_cnic(dev);
  3771. if (cdev) {
  3772. write_lock(&cnic_dev_lock);
  3773. list_add(&cdev->list, &cnic_dev_list);
  3774. write_unlock(&cnic_dev_lock);
  3775. }
  3776. }
  3777. return cdev;
  3778. }
  3779. /**
  3780. * netdev event handler
  3781. */
  3782. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3783. void *ptr)
  3784. {
  3785. struct net_device *netdev = ptr;
  3786. struct cnic_dev *dev;
  3787. int if_type;
  3788. int new_dev = 0;
  3789. dev = cnic_from_netdev(netdev);
  3790. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3791. /* Check for the hot-plug device */
  3792. dev = is_cnic_dev(netdev);
  3793. if (dev) {
  3794. new_dev = 1;
  3795. cnic_hold(dev);
  3796. }
  3797. }
  3798. if (dev) {
  3799. struct cnic_local *cp = dev->cnic_priv;
  3800. if (new_dev)
  3801. cnic_ulp_init(dev);
  3802. else if (event == NETDEV_UNREGISTER)
  3803. cnic_ulp_exit(dev);
  3804. if (event == NETDEV_UP) {
  3805. if (cnic_register_netdev(dev) != 0) {
  3806. cnic_put(dev);
  3807. goto done;
  3808. }
  3809. if (!cnic_start_hw(dev))
  3810. cnic_ulp_start(dev);
  3811. }
  3812. rcu_read_lock();
  3813. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  3814. struct cnic_ulp_ops *ulp_ops;
  3815. void *ctx;
  3816. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  3817. if (!ulp_ops || !ulp_ops->indicate_netevent)
  3818. continue;
  3819. ctx = cp->ulp_handle[if_type];
  3820. ulp_ops->indicate_netevent(ctx, event);
  3821. }
  3822. rcu_read_unlock();
  3823. if (event == NETDEV_GOING_DOWN) {
  3824. cnic_ulp_stop(dev);
  3825. cnic_stop_hw(dev);
  3826. cnic_unregister_netdev(dev);
  3827. } else if (event == NETDEV_UNREGISTER) {
  3828. write_lock(&cnic_dev_lock);
  3829. list_del_init(&dev->list);
  3830. write_unlock(&cnic_dev_lock);
  3831. cnic_put(dev);
  3832. cnic_free_dev(dev);
  3833. goto done;
  3834. }
  3835. cnic_put(dev);
  3836. }
  3837. done:
  3838. return NOTIFY_DONE;
  3839. }
  3840. static struct notifier_block cnic_netdev_notifier = {
  3841. .notifier_call = cnic_netdev_event
  3842. };
  3843. static void cnic_release(void)
  3844. {
  3845. struct cnic_dev *dev;
  3846. while (!list_empty(&cnic_dev_list)) {
  3847. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  3848. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3849. cnic_ulp_stop(dev);
  3850. cnic_stop_hw(dev);
  3851. }
  3852. cnic_ulp_exit(dev);
  3853. cnic_unregister_netdev(dev);
  3854. list_del_init(&dev->list);
  3855. cnic_free_dev(dev);
  3856. }
  3857. }
  3858. static int __init cnic_init(void)
  3859. {
  3860. int rc = 0;
  3861. pr_info("%s", version);
  3862. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  3863. if (rc) {
  3864. cnic_release();
  3865. return rc;
  3866. }
  3867. return 0;
  3868. }
  3869. static void __exit cnic_exit(void)
  3870. {
  3871. unregister_netdevice_notifier(&cnic_netdev_notifier);
  3872. cnic_release();
  3873. }
  3874. module_init(cnic_init);
  3875. module_exit(cnic_exit);