prpmc2800.dts 6.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299
  1. /* Device Tree Source for Motorola PrPMC2800
  2. *
  3. * Author: Mark A. Greer <mgreer@mvista.com>
  4. *
  5. * 2007 (c) MontaVista, Software, Inc. This file is licensed under
  6. * the terms of the GNU General Public License version 2. This program
  7. * is licensed "as is" without any warranty of any kind, whether express
  8. * or implied.
  9. *
  10. * Property values that are labeled as "Default" will be updated by bootwrapper
  11. * if it can determine the exact PrPMC type.
  12. */
  13. /dts-v1/;
  14. / {
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. model = "PrPMC280/PrPMC2800"; /* Default */
  18. compatible = "motorola,PrPMC2800";
  19. coherency-off;
  20. cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. PowerPC,7447 {
  24. device_type = "cpu";
  25. reg = <0>;
  26. clock-frequency = <733333333>; /* Default */
  27. bus-frequency = <133333333>;
  28. timebase-frequency = <33333333>;
  29. i-cache-line-size = <32>;
  30. d-cache-line-size = <32>;
  31. i-cache-size = <32768>;
  32. d-cache-size = <32768>;
  33. };
  34. };
  35. memory {
  36. device_type = "memory";
  37. reg = <0x0 0x20000000>; /* Default (512MB) */
  38. };
  39. system-controller@f1000000 { /* Marvell Discovery mv64360 */
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. model = "mv64360"; /* Default */
  43. compatible = "marvell,mv64360";
  44. clock-frequency = <133333333>;
  45. reg = <0xf1000000 0x10000>;
  46. virtual-reg = <0xf1000000>;
  47. ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
  48. 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
  49. 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
  50. 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
  51. 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
  52. flash@a0000000 {
  53. device_type = "rom";
  54. compatible = "direct-mapped";
  55. reg = <0xa0000000 0x4000000>; /* Default (64MB) */
  56. probe-type = "CFI";
  57. bank-width = <4>;
  58. partitions = <0x00000000 0x00100000 /* RO */
  59. 0x00100000 0x00040001 /* RW */
  60. 0x00140000 0x00400000 /* RO */
  61. 0x00540000 0x039c0000 /* RO */
  62. 0x03f00000 0x00100000>; /* RO */
  63. partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B";
  64. };
  65. mdio {
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. device_type = "mdio";
  69. compatible = "marvell,mv64360-mdio";
  70. PHY0: ethernet-phy@1 {
  71. device_type = "ethernet-phy";
  72. compatible = "broadcom,bcm5421";
  73. interrupts = <76>; /* GPP 12 */
  74. interrupt-parent = <&PIC>;
  75. reg = <1>;
  76. };
  77. PHY1: ethernet-phy@3 {
  78. device_type = "ethernet-phy";
  79. compatible = "broadcom,bcm5421";
  80. interrupts = <76>; /* GPP 12 */
  81. interrupt-parent = <&PIC>;
  82. reg = <3>;
  83. };
  84. };
  85. ethernet@2000 {
  86. reg = <0x2000 0x2000>;
  87. eth0 {
  88. device_type = "network";
  89. compatible = "marvell,mv64360-eth";
  90. block-index = <0>;
  91. interrupts = <32>;
  92. interrupt-parent = <&PIC>;
  93. phy = <&PHY0>;
  94. local-mac-address = [ 00 00 00 00 00 00 ];
  95. };
  96. eth1 {
  97. device_type = "network";
  98. compatible = "marvell,mv64360-eth";
  99. block-index = <1>;
  100. interrupts = <33>;
  101. interrupt-parent = <&PIC>;
  102. phy = <&PHY1>;
  103. local-mac-address = [ 00 00 00 00 00 00 ];
  104. };
  105. };
  106. SDMA0: sdma@4000 {
  107. compatible = "marvell,mv64360-sdma";
  108. reg = <0x4000 0xc18>;
  109. virtual-reg = <0xf1004000>;
  110. interrupts = <36>;
  111. interrupt-parent = <&PIC>;
  112. };
  113. SDMA1: sdma@6000 {
  114. compatible = "marvell,mv64360-sdma";
  115. reg = <0x6000 0xc18>;
  116. virtual-reg = <0xf1006000>;
  117. interrupts = <38>;
  118. interrupt-parent = <&PIC>;
  119. };
  120. BRG0: brg@b200 {
  121. compatible = "marvell,mv64360-brg";
  122. reg = <0xb200 0x8>;
  123. clock-src = <8>;
  124. clock-frequency = <133333333>;
  125. current-speed = <9600>;
  126. };
  127. BRG1: brg@b208 {
  128. compatible = "marvell,mv64360-brg";
  129. reg = <0xb208 0x8>;
  130. clock-src = <8>;
  131. clock-frequency = <133333333>;
  132. current-speed = <9600>;
  133. };
  134. CUNIT: cunit@f200 {
  135. reg = <0xf200 0x200>;
  136. };
  137. MPSCROUTING: mpscrouting@b400 {
  138. reg = <0xb400 0xc>;
  139. };
  140. MPSCINTR: mpscintr@b800 {
  141. reg = <0xb800 0x100>;
  142. virtual-reg = <0xf100b800>;
  143. };
  144. MPSC0: mpsc@8000 {
  145. device_type = "serial";
  146. compatible = "marvell,mv64360-mpsc";
  147. reg = <0x8000 0x38>;
  148. virtual-reg = <0xf1008000>;
  149. sdma = <&SDMA0>;
  150. brg = <&BRG0>;
  151. cunit = <&CUNIT>;
  152. mpscrouting = <&MPSCROUTING>;
  153. mpscintr = <&MPSCINTR>;
  154. cell-index = <0>;
  155. interrupts = <40>;
  156. interrupt-parent = <&PIC>;
  157. };
  158. MPSC1: mpsc@9000 {
  159. device_type = "serial";
  160. compatible = "marvell,mv64360-mpsc";
  161. reg = <0x9000 0x38>;
  162. virtual-reg = <0xf1009000>;
  163. sdma = <&SDMA1>;
  164. brg = <&BRG1>;
  165. cunit = <&CUNIT>;
  166. mpscrouting = <&MPSCROUTING>;
  167. mpscintr = <&MPSCINTR>;
  168. cell-index = <1>;
  169. interrupts = <42>;
  170. interrupt-parent = <&PIC>;
  171. };
  172. wdt@b410 { /* watchdog timer */
  173. compatible = "marvell,mv64360-wdt";
  174. reg = <0xb410 0x8>;
  175. };
  176. i2c@c000 {
  177. device_type = "i2c";
  178. compatible = "marvell,mv64360-i2c";
  179. reg = <0xc000 0x20>;
  180. virtual-reg = <0xf100c000>;
  181. interrupts = <37>;
  182. interrupt-parent = <&PIC>;
  183. };
  184. PIC: pic {
  185. #interrupt-cells = <1>;
  186. #address-cells = <0>;
  187. compatible = "marvell,mv64360-pic";
  188. reg = <0x0 0x88>;
  189. interrupt-controller;
  190. };
  191. mpp@f000 {
  192. compatible = "marvell,mv64360-mpp";
  193. reg = <0xf000 0x10>;
  194. };
  195. gpp@f100 {
  196. compatible = "marvell,mv64360-gpp";
  197. reg = <0xf100 0x20>;
  198. };
  199. pci@80000000 {
  200. #address-cells = <3>;
  201. #size-cells = <2>;
  202. #interrupt-cells = <1>;
  203. device_type = "pci";
  204. compatible = "marvell,mv64360-pci";
  205. reg = <0xcf8 0x8>;
  206. ranges = <0x01000000 0x0 0x0
  207. 0x88000000 0x0 0x01000000
  208. 0x02000000 0x0 0x80000000
  209. 0x80000000 0x0 0x08000000>;
  210. bus-range = <0 255>;
  211. clock-frequency = <66000000>;
  212. interrupt-pci-iack = <0xc34>;
  213. interrupt-parent = <&PIC>;
  214. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  215. interrupt-map = <
  216. /* IDSEL 0x0a */
  217. 0x5000 0 0 1 &PIC 80
  218. 0x5000 0 0 2 &PIC 81
  219. 0x5000 0 0 3 &PIC 91
  220. 0x5000 0 0 4 &PIC 93
  221. /* IDSEL 0x0b */
  222. 0x5800 0 0 1 &PIC 91
  223. 0x5800 0 0 2 &PIC 93
  224. 0x5800 0 0 3 &PIC 80
  225. 0x5800 0 0 4 &PIC 81
  226. /* IDSEL 0x0c */
  227. 0x6000 0 0 1 &PIC 91
  228. 0x6000 0 0 2 &PIC 93
  229. 0x6000 0 0 3 &PIC 80
  230. 0x6000 0 0 4 &PIC 81
  231. /* IDSEL 0x0d */
  232. 0x6800 0 0 1 &PIC 93
  233. 0x6800 0 0 2 &PIC 80
  234. 0x6800 0 0 3 &PIC 81
  235. 0x6800 0 0 4 &PIC 91
  236. >;
  237. };
  238. cpu-error@0070 {
  239. compatible = "marvell,mv64360-cpu-error";
  240. reg = <0x70 0x10 0x128 0x28>;
  241. interrupts = <3>;
  242. interrupt-parent = <&PIC>;
  243. };
  244. sram-ctrl@0380 {
  245. compatible = "marvell,mv64360-sram-ctrl";
  246. reg = <0x380 0x80>;
  247. interrupts = <13>;
  248. interrupt-parent = <&PIC>;
  249. };
  250. pci-error@1d40 {
  251. compatible = "marvell,mv64360-pci-error";
  252. reg = <0x1d40 0x40 0xc28 0x4>;
  253. interrupts = <12>;
  254. interrupt-parent = <&PIC>;
  255. };
  256. mem-ctrl@1400 {
  257. compatible = "marvell,mv64360-mem-ctrl";
  258. reg = <0x1400 0x60>;
  259. interrupts = <17>;
  260. interrupt-parent = <&PIC>;
  261. };
  262. };
  263. chosen {
  264. bootargs = "ip=on";
  265. linux,stdout-path = &MPSC0;
  266. };
  267. };