ci13xxx_udc.c 72 KB

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  1. /*
  2. * ci13xxx_udc.c - MIPS USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: MIPS USB IP core family device controller
  14. * Currently it only supports IP part number CI13412
  15. *
  16. * This driver is composed of several blocks:
  17. * - HW: hardware interface
  18. * - DBG: debug facilities (optional)
  19. * - UTIL: utilities
  20. * - ISR: interrupts handling
  21. * - ENDPT: endpoint operations (Gadget API)
  22. * - GADGET: gadget operations (Gadget API)
  23. * - BUS: bus glue code, bus abstraction layer
  24. *
  25. * Compile Options
  26. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  27. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  28. * if defined mass storage compliance succeeds but with warnings
  29. * => case 4: Hi > Dn
  30. * => case 5: Hi > Di
  31. * => case 8: Hi <> Do
  32. * if undefined usbtest 13 fails
  33. * - TRACE: enable function tracing (depends on DEBUG)
  34. *
  35. * Main Features
  36. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  37. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  38. * - Normal & LPM support
  39. *
  40. * USBTEST Report
  41. * - OK: 0-12, 13 (STALL_IN defined) & 14
  42. * - Not Supported: 15 & 16 (ISO)
  43. *
  44. * TODO List
  45. * - OTG
  46. * - Isochronous & Interrupt Traffic
  47. * - Handle requests which spawns into several TDs
  48. * - GET_STATUS(device) - always reports 0
  49. * - Gadget API (majority of optional features)
  50. * - Suspend & Remote Wakeup
  51. */
  52. #include <linux/delay.h>
  53. #include <linux/device.h>
  54. #include <linux/dmapool.h>
  55. #include <linux/dma-mapping.h>
  56. #include <linux/init.h>
  57. #include <linux/platform_device.h>
  58. #include <linux/module.h>
  59. #include <linux/interrupt.h>
  60. #include <linux/io.h>
  61. #include <linux/irq.h>
  62. #include <linux/kernel.h>
  63. #include <linux/slab.h>
  64. #include <linux/pm_runtime.h>
  65. #include <linux/usb/ch9.h>
  66. #include <linux/usb/gadget.h>
  67. #include <linux/usb/otg.h>
  68. #include "ci13xxx_udc.h"
  69. /******************************************************************************
  70. * DEFINE
  71. *****************************************************************************/
  72. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  73. /* control endpoint description */
  74. static const struct usb_endpoint_descriptor
  75. ctrl_endpt_out_desc = {
  76. .bLength = USB_DT_ENDPOINT_SIZE,
  77. .bDescriptorType = USB_DT_ENDPOINT,
  78. .bEndpointAddress = USB_DIR_OUT,
  79. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  80. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  81. };
  82. static const struct usb_endpoint_descriptor
  83. ctrl_endpt_in_desc = {
  84. .bLength = USB_DT_ENDPOINT_SIZE,
  85. .bDescriptorType = USB_DT_ENDPOINT,
  86. .bEndpointAddress = USB_DIR_IN,
  87. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  88. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  89. };
  90. /* Interrupt statistics */
  91. #define ISR_MASK 0x1F
  92. static struct {
  93. u32 test;
  94. u32 ui;
  95. u32 uei;
  96. u32 pci;
  97. u32 uri;
  98. u32 sli;
  99. u32 none;
  100. struct {
  101. u32 cnt;
  102. u32 buf[ISR_MASK+1];
  103. u32 idx;
  104. } hndl;
  105. } isr_statistics;
  106. /**
  107. * ffs_nr: find first (least significant) bit set
  108. * @x: the word to search
  109. *
  110. * This function returns bit number (instead of position)
  111. */
  112. static int ffs_nr(u32 x)
  113. {
  114. int n = ffs(x);
  115. return n ? n-1 : 32;
  116. }
  117. /******************************************************************************
  118. * HW block
  119. *****************************************************************************/
  120. /* MSM specific */
  121. #define ABS_AHBBURST (0x0090UL)
  122. #define ABS_AHBMODE (0x0098UL)
  123. /* UDC register map */
  124. static uintptr_t ci_regs_nolpm[] = {
  125. [CAP_CAPLENGTH] = 0x000UL,
  126. [CAP_HCCPARAMS] = 0x008UL,
  127. [CAP_DCCPARAMS] = 0x024UL,
  128. [CAP_TESTMODE] = 0x038UL,
  129. [OP_USBCMD] = 0x000UL,
  130. [OP_USBSTS] = 0x004UL,
  131. [OP_USBINTR] = 0x008UL,
  132. [OP_DEVICEADDR] = 0x014UL,
  133. [OP_ENDPTLISTADDR] = 0x018UL,
  134. [OP_PORTSC] = 0x044UL,
  135. [OP_DEVLC] = 0x084UL,
  136. [OP_USBMODE] = 0x068UL,
  137. [OP_ENDPTSETUPSTAT] = 0x06CUL,
  138. [OP_ENDPTPRIME] = 0x070UL,
  139. [OP_ENDPTFLUSH] = 0x074UL,
  140. [OP_ENDPTSTAT] = 0x078UL,
  141. [OP_ENDPTCOMPLETE] = 0x07CUL,
  142. [OP_ENDPTCTRL] = 0x080UL,
  143. };
  144. static uintptr_t ci_regs_lpm[] = {
  145. [CAP_CAPLENGTH] = 0x000UL,
  146. [CAP_HCCPARAMS] = 0x008UL,
  147. [CAP_DCCPARAMS] = 0x024UL,
  148. [CAP_TESTMODE] = 0x0FCUL,
  149. [OP_USBCMD] = 0x000UL,
  150. [OP_USBSTS] = 0x004UL,
  151. [OP_USBINTR] = 0x008UL,
  152. [OP_DEVICEADDR] = 0x014UL,
  153. [OP_ENDPTLISTADDR] = 0x018UL,
  154. [OP_PORTSC] = 0x044UL,
  155. [OP_DEVLC] = 0x084UL,
  156. [OP_USBMODE] = 0x0C8UL,
  157. [OP_ENDPTSETUPSTAT] = 0x0D8UL,
  158. [OP_ENDPTPRIME] = 0x0DCUL,
  159. [OP_ENDPTFLUSH] = 0x0E0UL,
  160. [OP_ENDPTSTAT] = 0x0E4UL,
  161. [OP_ENDPTCOMPLETE] = 0x0E8UL,
  162. [OP_ENDPTCTRL] = 0x0ECUL,
  163. };
  164. static int hw_alloc_regmap(struct ci13xxx *udc, bool is_lpm)
  165. {
  166. int i;
  167. kfree(udc->hw_bank.regmap);
  168. udc->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
  169. GFP_KERNEL);
  170. if (!udc->hw_bank.regmap)
  171. return -ENOMEM;
  172. for (i = 0; i < OP_ENDPTCTRL; i++)
  173. udc->hw_bank.regmap[i] =
  174. (i <= CAP_LAST ? udc->hw_bank.cap : udc->hw_bank.op) +
  175. (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
  176. for (; i <= OP_LAST; i++)
  177. udc->hw_bank.regmap[i] = udc->hw_bank.op +
  178. 4 * (i - OP_ENDPTCTRL) +
  179. (is_lpm
  180. ? ci_regs_lpm[OP_ENDPTCTRL]
  181. : ci_regs_nolpm[OP_ENDPTCTRL]);
  182. return 0;
  183. }
  184. /**
  185. * hw_ep_bit: calculates the bit number
  186. * @num: endpoint number
  187. * @dir: endpoint direction
  188. *
  189. * This function returns bit number
  190. */
  191. static inline int hw_ep_bit(int num, int dir)
  192. {
  193. return num + (dir ? 16 : 0);
  194. }
  195. static int ep_to_bit(struct ci13xxx *udc, int n)
  196. {
  197. int fill = 16 - udc->hw_ep_max / 2;
  198. if (n >= udc->hw_ep_max / 2)
  199. n += fill;
  200. return n;
  201. }
  202. /**
  203. * hw_read: reads from a hw register
  204. * @reg: register index
  205. * @mask: bitfield mask
  206. *
  207. * This function returns register contents
  208. */
  209. static u32 hw_read(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask)
  210. {
  211. return ioread32(udc->hw_bank.regmap[reg]) & mask;
  212. }
  213. /**
  214. * hw_write: writes to a hw register
  215. * @reg: register index
  216. * @mask: bitfield mask
  217. * @data: new value
  218. */
  219. static void hw_write(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask,
  220. u32 data)
  221. {
  222. if (~mask)
  223. data = (ioread32(udc->hw_bank.regmap[reg]) & ~mask)
  224. | (data & mask);
  225. iowrite32(data, udc->hw_bank.regmap[reg]);
  226. }
  227. /**
  228. * hw_test_and_clear: tests & clears a hw register
  229. * @reg: register index
  230. * @mask: bitfield mask
  231. *
  232. * This function returns register contents
  233. */
  234. static u32 hw_test_and_clear(struct ci13xxx *udc, enum ci13xxx_regs reg,
  235. u32 mask)
  236. {
  237. u32 val = ioread32(udc->hw_bank.regmap[reg]) & mask;
  238. iowrite32(val, udc->hw_bank.regmap[reg]);
  239. return val;
  240. }
  241. /**
  242. * hw_test_and_write: tests & writes a hw register
  243. * @reg: register index
  244. * @mask: bitfield mask
  245. * @data: new value
  246. *
  247. * This function returns register contents
  248. */
  249. static u32 hw_test_and_write(struct ci13xxx *udc, enum ci13xxx_regs reg,
  250. u32 mask, u32 data)
  251. {
  252. u32 val = hw_read(udc, reg, ~0);
  253. hw_write(udc, reg, mask, data);
  254. return (val & mask) >> ffs_nr(mask);
  255. }
  256. static int hw_device_init(struct ci13xxx *udc, void __iomem *base,
  257. uintptr_t cap_offset)
  258. {
  259. u32 reg;
  260. /* bank is a module variable */
  261. udc->hw_bank.abs = base;
  262. udc->hw_bank.cap = udc->hw_bank.abs;
  263. udc->hw_bank.cap += cap_offset;
  264. udc->hw_bank.op = udc->hw_bank.cap + ioread8(udc->hw_bank.cap);
  265. hw_alloc_regmap(udc, false);
  266. reg = hw_read(udc, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
  267. ffs_nr(HCCPARAMS_LEN);
  268. udc->hw_bank.lpm = reg;
  269. hw_alloc_regmap(udc, !!reg);
  270. udc->hw_bank.size = udc->hw_bank.op - udc->hw_bank.abs;
  271. udc->hw_bank.size += OP_LAST;
  272. udc->hw_bank.size /= sizeof(u32);
  273. reg = hw_read(udc, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
  274. ffs_nr(DCCPARAMS_DEN);
  275. udc->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  276. if (udc->hw_ep_max == 0 || udc->hw_ep_max > ENDPT_MAX)
  277. return -ENODEV;
  278. /* setup lock mode ? */
  279. /* ENDPTSETUPSTAT is '0' by default */
  280. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  281. return 0;
  282. }
  283. /**
  284. * hw_device_reset: resets chip (execute without interruption)
  285. * @base: register base address
  286. *
  287. * This function returns an error code
  288. */
  289. static int hw_device_reset(struct ci13xxx *udc)
  290. {
  291. /* should flush & stop before reset */
  292. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  293. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  294. hw_write(udc, OP_USBCMD, USBCMD_RST, USBCMD_RST);
  295. while (hw_read(udc, OP_USBCMD, USBCMD_RST))
  296. udelay(10); /* not RTOS friendly */
  297. if (udc->udc_driver->notify_event)
  298. udc->udc_driver->notify_event(udc,
  299. CI13XXX_CONTROLLER_RESET_EVENT);
  300. if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
  301. hw_write(udc, OP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
  302. /* USBMODE should be configured step by step */
  303. hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  304. hw_write(udc, OP_USBMODE, USBMODE_CM, USBMODE_CM_DEVICE);
  305. /* HW >= 2.3 */
  306. hw_write(udc, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
  307. if (hw_read(udc, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DEVICE) {
  308. pr_err("cannot enter in device mode");
  309. pr_err("lpm = %i", udc->hw_bank.lpm);
  310. return -ENODEV;
  311. }
  312. return 0;
  313. }
  314. /**
  315. * hw_device_state: enables/disables interrupts & starts/stops device (execute
  316. * without interruption)
  317. * @dma: 0 => disable, !0 => enable and set dma engine
  318. *
  319. * This function returns an error code
  320. */
  321. static int hw_device_state(struct ci13xxx *udc, u32 dma)
  322. {
  323. if (dma) {
  324. hw_write(udc, OP_ENDPTLISTADDR, ~0, dma);
  325. /* interrupt, error, port change, reset, sleep/suspend */
  326. hw_write(udc, OP_USBINTR, ~0,
  327. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  328. hw_write(udc, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  329. } else {
  330. hw_write(udc, OP_USBCMD, USBCMD_RS, 0);
  331. hw_write(udc, OP_USBINTR, ~0, 0);
  332. }
  333. return 0;
  334. }
  335. /**
  336. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  337. * @num: endpoint number
  338. * @dir: endpoint direction
  339. *
  340. * This function returns an error code
  341. */
  342. static int hw_ep_flush(struct ci13xxx *udc, int num, int dir)
  343. {
  344. int n = hw_ep_bit(num, dir);
  345. do {
  346. /* flush any pending transfer */
  347. hw_write(udc, OP_ENDPTFLUSH, BIT(n), BIT(n));
  348. while (hw_read(udc, OP_ENDPTFLUSH, BIT(n)))
  349. cpu_relax();
  350. } while (hw_read(udc, OP_ENDPTSTAT, BIT(n)));
  351. return 0;
  352. }
  353. /**
  354. * hw_ep_disable: disables endpoint (execute without interruption)
  355. * @num: endpoint number
  356. * @dir: endpoint direction
  357. *
  358. * This function returns an error code
  359. */
  360. static int hw_ep_disable(struct ci13xxx *udc, int num, int dir)
  361. {
  362. hw_ep_flush(udc, num, dir);
  363. hw_write(udc, OP_ENDPTCTRL + num,
  364. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  365. return 0;
  366. }
  367. /**
  368. * hw_ep_enable: enables endpoint (execute without interruption)
  369. * @num: endpoint number
  370. * @dir: endpoint direction
  371. * @type: endpoint type
  372. *
  373. * This function returns an error code
  374. */
  375. static int hw_ep_enable(struct ci13xxx *udc, int num, int dir, int type)
  376. {
  377. u32 mask, data;
  378. if (dir) {
  379. mask = ENDPTCTRL_TXT; /* type */
  380. data = type << ffs_nr(mask);
  381. mask |= ENDPTCTRL_TXS; /* unstall */
  382. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  383. data |= ENDPTCTRL_TXR;
  384. mask |= ENDPTCTRL_TXE; /* enable */
  385. data |= ENDPTCTRL_TXE;
  386. } else {
  387. mask = ENDPTCTRL_RXT; /* type */
  388. data = type << ffs_nr(mask);
  389. mask |= ENDPTCTRL_RXS; /* unstall */
  390. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  391. data |= ENDPTCTRL_RXR;
  392. mask |= ENDPTCTRL_RXE; /* enable */
  393. data |= ENDPTCTRL_RXE;
  394. }
  395. hw_write(udc, OP_ENDPTCTRL + num, mask, data);
  396. return 0;
  397. }
  398. /**
  399. * hw_ep_get_halt: return endpoint halt status
  400. * @num: endpoint number
  401. * @dir: endpoint direction
  402. *
  403. * This function returns 1 if endpoint halted
  404. */
  405. static int hw_ep_get_halt(struct ci13xxx *udc, int num, int dir)
  406. {
  407. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  408. return hw_read(udc, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  409. }
  410. /**
  411. * hw_test_and_clear_setup_status: test & clear setup status (execute without
  412. * interruption)
  413. * @n: endpoint number
  414. *
  415. * This function returns setup status
  416. */
  417. static int hw_test_and_clear_setup_status(struct ci13xxx *udc, int n)
  418. {
  419. n = ep_to_bit(udc, n);
  420. return hw_test_and_clear(udc, OP_ENDPTSETUPSTAT, BIT(n));
  421. }
  422. /**
  423. * hw_ep_prime: primes endpoint (execute without interruption)
  424. * @num: endpoint number
  425. * @dir: endpoint direction
  426. * @is_ctrl: true if control endpoint
  427. *
  428. * This function returns an error code
  429. */
  430. static int hw_ep_prime(struct ci13xxx *udc, int num, int dir, int is_ctrl)
  431. {
  432. int n = hw_ep_bit(num, dir);
  433. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  434. return -EAGAIN;
  435. hw_write(udc, OP_ENDPTPRIME, BIT(n), BIT(n));
  436. while (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  437. cpu_relax();
  438. if (is_ctrl && dir == RX && hw_read(udc, OP_ENDPTSETUPSTAT, BIT(num)))
  439. return -EAGAIN;
  440. /* status shoult be tested according with manual but it doesn't work */
  441. return 0;
  442. }
  443. /**
  444. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  445. * without interruption)
  446. * @num: endpoint number
  447. * @dir: endpoint direction
  448. * @value: true => stall, false => unstall
  449. *
  450. * This function returns an error code
  451. */
  452. static int hw_ep_set_halt(struct ci13xxx *udc, int num, int dir, int value)
  453. {
  454. if (value != 0 && value != 1)
  455. return -EINVAL;
  456. do {
  457. enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
  458. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  459. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  460. /* data toggle - reserved for EP0 but it's in ESS */
  461. hw_write(udc, reg, mask_xs|mask_xr,
  462. value ? mask_xs : mask_xr);
  463. } while (value != hw_ep_get_halt(udc, num, dir));
  464. return 0;
  465. }
  466. /**
  467. * hw_intr_clear: disables interrupt & clears interrupt status (execute without
  468. * interruption)
  469. * @n: interrupt bit
  470. *
  471. * This function returns an error code
  472. */
  473. static int hw_intr_clear(struct ci13xxx *udc, int n)
  474. {
  475. if (n >= REG_BITS)
  476. return -EINVAL;
  477. hw_write(udc, OP_USBINTR, BIT(n), 0);
  478. hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
  479. return 0;
  480. }
  481. /**
  482. * hw_intr_force: enables interrupt & forces interrupt status (execute without
  483. * interruption)
  484. * @n: interrupt bit
  485. *
  486. * This function returns an error code
  487. */
  488. static int hw_intr_force(struct ci13xxx *udc, int n)
  489. {
  490. if (n >= REG_BITS)
  491. return -EINVAL;
  492. hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, TESTMODE_FORCE);
  493. hw_write(udc, OP_USBINTR, BIT(n), BIT(n));
  494. hw_write(udc, OP_USBSTS, BIT(n), BIT(n));
  495. hw_write(udc, CAP_TESTMODE, TESTMODE_FORCE, 0);
  496. return 0;
  497. }
  498. /**
  499. * hw_is_port_high_speed: test if port is high speed
  500. *
  501. * This function returns true if high speed port
  502. */
  503. static int hw_port_is_high_speed(struct ci13xxx *udc)
  504. {
  505. return udc->hw_bank.lpm ? hw_read(udc, OP_DEVLC, DEVLC_PSPD) :
  506. hw_read(udc, OP_PORTSC, PORTSC_HSP);
  507. }
  508. /**
  509. * hw_port_test_get: reads port test mode value
  510. *
  511. * This function returns port test mode value
  512. */
  513. static u8 hw_port_test_get(struct ci13xxx *udc)
  514. {
  515. return hw_read(udc, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  516. }
  517. /**
  518. * hw_port_test_set: writes port test mode (execute without interruption)
  519. * @mode: new value
  520. *
  521. * This function returns an error code
  522. */
  523. static int hw_port_test_set(struct ci13xxx *udc, u8 mode)
  524. {
  525. const u8 TEST_MODE_MAX = 7;
  526. if (mode > TEST_MODE_MAX)
  527. return -EINVAL;
  528. hw_write(udc, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  529. return 0;
  530. }
  531. /**
  532. * hw_read_intr_enable: returns interrupt enable register
  533. *
  534. * This function returns register data
  535. */
  536. static u32 hw_read_intr_enable(struct ci13xxx *udc)
  537. {
  538. return hw_read(udc, OP_USBINTR, ~0);
  539. }
  540. /**
  541. * hw_read_intr_status: returns interrupt status register
  542. *
  543. * This function returns register data
  544. */
  545. static u32 hw_read_intr_status(struct ci13xxx *udc)
  546. {
  547. return hw_read(udc, OP_USBSTS, ~0);
  548. }
  549. /**
  550. * hw_register_read: reads all device registers (execute without interruption)
  551. * @buf: destination buffer
  552. * @size: buffer size
  553. *
  554. * This function returns number of registers read
  555. */
  556. static size_t hw_register_read(struct ci13xxx *udc, u32 *buf, size_t size)
  557. {
  558. unsigned i;
  559. if (size > udc->hw_bank.size)
  560. size = udc->hw_bank.size;
  561. for (i = 0; i < size; i++)
  562. buf[i] = hw_read(udc, i * sizeof(u32), ~0);
  563. return size;
  564. }
  565. /**
  566. * hw_register_write: writes to register
  567. * @addr: register address
  568. * @data: register value
  569. *
  570. * This function returns an error code
  571. */
  572. static int hw_register_write(struct ci13xxx *udc, u16 addr, u32 data)
  573. {
  574. /* align */
  575. addr /= sizeof(u32);
  576. if (addr >= udc->hw_bank.size)
  577. return -EINVAL;
  578. /* align */
  579. addr *= sizeof(u32);
  580. hw_write(udc, addr, ~0, data);
  581. return 0;
  582. }
  583. /**
  584. * hw_test_and_clear_complete: test & clear complete status (execute without
  585. * interruption)
  586. * @n: endpoint number
  587. *
  588. * This function returns complete status
  589. */
  590. static int hw_test_and_clear_complete(struct ci13xxx *udc, int n)
  591. {
  592. n = ep_to_bit(udc, n);
  593. return hw_test_and_clear(udc, OP_ENDPTCOMPLETE, BIT(n));
  594. }
  595. /**
  596. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  597. * without interruption)
  598. *
  599. * This function returns active interrutps
  600. */
  601. static u32 hw_test_and_clear_intr_active(struct ci13xxx *udc)
  602. {
  603. u32 reg = hw_read_intr_status(udc) & hw_read_intr_enable(udc);
  604. hw_write(udc, OP_USBSTS, ~0, reg);
  605. return reg;
  606. }
  607. /**
  608. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  609. * interruption)
  610. *
  611. * This function returns guard value
  612. */
  613. static int hw_test_and_clear_setup_guard(struct ci13xxx *udc)
  614. {
  615. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, 0);
  616. }
  617. /**
  618. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  619. * interruption)
  620. *
  621. * This function returns guard value
  622. */
  623. static int hw_test_and_set_setup_guard(struct ci13xxx *udc)
  624. {
  625. return hw_test_and_write(udc, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  626. }
  627. /**
  628. * hw_usb_set_address: configures USB address (execute without interruption)
  629. * @value: new USB address
  630. *
  631. * This function returns an error code
  632. */
  633. static int hw_usb_set_address(struct ci13xxx *udc, u8 value)
  634. {
  635. /* advance */
  636. hw_write(udc, OP_DEVICEADDR, DEVICEADDR_USBADR | DEVICEADDR_USBADRA,
  637. value << ffs_nr(DEVICEADDR_USBADR) | DEVICEADDR_USBADRA);
  638. return 0;
  639. }
  640. /**
  641. * hw_usb_reset: restart device after a bus reset (execute without
  642. * interruption)
  643. *
  644. * This function returns an error code
  645. */
  646. static int hw_usb_reset(struct ci13xxx *udc)
  647. {
  648. hw_usb_set_address(udc, 0);
  649. /* ESS flushes only at end?!? */
  650. hw_write(udc, OP_ENDPTFLUSH, ~0, ~0);
  651. /* clear setup token semaphores */
  652. hw_write(udc, OP_ENDPTSETUPSTAT, 0, 0);
  653. /* clear complete status */
  654. hw_write(udc, OP_ENDPTCOMPLETE, 0, 0);
  655. /* wait until all bits cleared */
  656. while (hw_read(udc, OP_ENDPTPRIME, ~0))
  657. udelay(10); /* not RTOS friendly */
  658. /* reset all endpoints ? */
  659. /* reset internal status and wait for further instructions
  660. no need to verify the port reset status (ESS does it) */
  661. return 0;
  662. }
  663. /******************************************************************************
  664. * DBG block
  665. *****************************************************************************/
  666. /**
  667. * show_device: prints information about device capabilities and status
  668. *
  669. * Check "device.h" for details
  670. */
  671. static ssize_t show_device(struct device *dev, struct device_attribute *attr,
  672. char *buf)
  673. {
  674. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  675. struct usb_gadget *gadget = &udc->gadget;
  676. int n = 0;
  677. if (attr == NULL || buf == NULL) {
  678. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  679. return 0;
  680. }
  681. n += scnprintf(buf + n, PAGE_SIZE - n, "speed = %d\n",
  682. gadget->speed);
  683. n += scnprintf(buf + n, PAGE_SIZE - n, "max_speed = %d\n",
  684. gadget->max_speed);
  685. /* TODO: Scheduled for removal in 3.8. */
  686. n += scnprintf(buf + n, PAGE_SIZE - n, "is_dualspeed = %d\n",
  687. gadget_is_dualspeed(gadget));
  688. n += scnprintf(buf + n, PAGE_SIZE - n, "is_otg = %d\n",
  689. gadget->is_otg);
  690. n += scnprintf(buf + n, PAGE_SIZE - n, "is_a_peripheral = %d\n",
  691. gadget->is_a_peripheral);
  692. n += scnprintf(buf + n, PAGE_SIZE - n, "b_hnp_enable = %d\n",
  693. gadget->b_hnp_enable);
  694. n += scnprintf(buf + n, PAGE_SIZE - n, "a_hnp_support = %d\n",
  695. gadget->a_hnp_support);
  696. n += scnprintf(buf + n, PAGE_SIZE - n, "a_alt_hnp_support = %d\n",
  697. gadget->a_alt_hnp_support);
  698. n += scnprintf(buf + n, PAGE_SIZE - n, "name = %s\n",
  699. (gadget->name ? gadget->name : ""));
  700. return n;
  701. }
  702. static DEVICE_ATTR(device, S_IRUSR, show_device, NULL);
  703. /**
  704. * show_driver: prints information about attached gadget (if any)
  705. *
  706. * Check "device.h" for details
  707. */
  708. static ssize_t show_driver(struct device *dev, struct device_attribute *attr,
  709. char *buf)
  710. {
  711. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  712. struct usb_gadget_driver *driver = udc->driver;
  713. int n = 0;
  714. if (attr == NULL || buf == NULL) {
  715. dev_err(dev, "[%s] EINVAL\n", __func__);
  716. return 0;
  717. }
  718. if (driver == NULL)
  719. return scnprintf(buf, PAGE_SIZE,
  720. "There is no gadget attached!\n");
  721. n += scnprintf(buf + n, PAGE_SIZE - n, "function = %s\n",
  722. (driver->function ? driver->function : ""));
  723. n += scnprintf(buf + n, PAGE_SIZE - n, "max speed = %d\n",
  724. driver->max_speed);
  725. return n;
  726. }
  727. static DEVICE_ATTR(driver, S_IRUSR, show_driver, NULL);
  728. /* Maximum event message length */
  729. #define DBG_DATA_MSG 64UL
  730. /* Maximum event messages */
  731. #define DBG_DATA_MAX 128UL
  732. /* Event buffer descriptor */
  733. static struct {
  734. char (buf[DBG_DATA_MAX])[DBG_DATA_MSG]; /* buffer */
  735. unsigned idx; /* index */
  736. unsigned tty; /* print to console? */
  737. rwlock_t lck; /* lock */
  738. } dbg_data = {
  739. .idx = 0,
  740. .tty = 0,
  741. .lck = __RW_LOCK_UNLOCKED(lck)
  742. };
  743. /**
  744. * dbg_dec: decrements debug event index
  745. * @idx: buffer index
  746. */
  747. static void dbg_dec(unsigned *idx)
  748. {
  749. *idx = (*idx - 1) & (DBG_DATA_MAX-1);
  750. }
  751. /**
  752. * dbg_inc: increments debug event index
  753. * @idx: buffer index
  754. */
  755. static void dbg_inc(unsigned *idx)
  756. {
  757. *idx = (*idx + 1) & (DBG_DATA_MAX-1);
  758. }
  759. /**
  760. * dbg_print: prints the common part of the event
  761. * @addr: endpoint address
  762. * @name: event name
  763. * @status: status
  764. * @extra: extra information
  765. */
  766. static void dbg_print(u8 addr, const char *name, int status, const char *extra)
  767. {
  768. struct timeval tval;
  769. unsigned int stamp;
  770. unsigned long flags;
  771. write_lock_irqsave(&dbg_data.lck, flags);
  772. do_gettimeofday(&tval);
  773. stamp = tval.tv_sec & 0xFFFF; /* 2^32 = 4294967296. Limit to 4096s */
  774. stamp = stamp * 1000000 + tval.tv_usec;
  775. scnprintf(dbg_data.buf[dbg_data.idx], DBG_DATA_MSG,
  776. "%04X\t? %02X %-7.7s %4i ?\t%s\n",
  777. stamp, addr, name, status, extra);
  778. dbg_inc(&dbg_data.idx);
  779. write_unlock_irqrestore(&dbg_data.lck, flags);
  780. if (dbg_data.tty != 0)
  781. pr_notice("%04X\t? %02X %-7.7s %4i ?\t%s\n",
  782. stamp, addr, name, status, extra);
  783. }
  784. /**
  785. * dbg_done: prints a DONE event
  786. * @addr: endpoint address
  787. * @td: transfer descriptor
  788. * @status: status
  789. */
  790. static void dbg_done(u8 addr, const u32 token, int status)
  791. {
  792. char msg[DBG_DATA_MSG];
  793. scnprintf(msg, sizeof(msg), "%d %02X",
  794. (int)(token & TD_TOTAL_BYTES) >> ffs_nr(TD_TOTAL_BYTES),
  795. (int)(token & TD_STATUS) >> ffs_nr(TD_STATUS));
  796. dbg_print(addr, "DONE", status, msg);
  797. }
  798. /**
  799. * dbg_event: prints a generic event
  800. * @addr: endpoint address
  801. * @name: event name
  802. * @status: status
  803. */
  804. static void dbg_event(u8 addr, const char *name, int status)
  805. {
  806. if (name != NULL)
  807. dbg_print(addr, name, status, "");
  808. }
  809. /*
  810. * dbg_queue: prints a QUEUE event
  811. * @addr: endpoint address
  812. * @req: USB request
  813. * @status: status
  814. */
  815. static void dbg_queue(u8 addr, const struct usb_request *req, int status)
  816. {
  817. char msg[DBG_DATA_MSG];
  818. if (req != NULL) {
  819. scnprintf(msg, sizeof(msg),
  820. "%d %d", !req->no_interrupt, req->length);
  821. dbg_print(addr, "QUEUE", status, msg);
  822. }
  823. }
  824. /**
  825. * dbg_setup: prints a SETUP event
  826. * @addr: endpoint address
  827. * @req: setup request
  828. */
  829. static void dbg_setup(u8 addr, const struct usb_ctrlrequest *req)
  830. {
  831. char msg[DBG_DATA_MSG];
  832. if (req != NULL) {
  833. scnprintf(msg, sizeof(msg),
  834. "%02X %02X %04X %04X %d", req->bRequestType,
  835. req->bRequest, le16_to_cpu(req->wValue),
  836. le16_to_cpu(req->wIndex), le16_to_cpu(req->wLength));
  837. dbg_print(addr, "SETUP", 0, msg);
  838. }
  839. }
  840. /**
  841. * show_events: displays the event buffer
  842. *
  843. * Check "device.h" for details
  844. */
  845. static ssize_t show_events(struct device *dev, struct device_attribute *attr,
  846. char *buf)
  847. {
  848. unsigned long flags;
  849. unsigned i, j, n = 0;
  850. if (attr == NULL || buf == NULL) {
  851. dev_err(dev->parent, "[%s] EINVAL\n", __func__);
  852. return 0;
  853. }
  854. read_lock_irqsave(&dbg_data.lck, flags);
  855. i = dbg_data.idx;
  856. for (dbg_dec(&i); i != dbg_data.idx; dbg_dec(&i)) {
  857. n += strlen(dbg_data.buf[i]);
  858. if (n >= PAGE_SIZE) {
  859. n -= strlen(dbg_data.buf[i]);
  860. break;
  861. }
  862. }
  863. for (j = 0, dbg_inc(&i); j < n; dbg_inc(&i))
  864. j += scnprintf(buf + j, PAGE_SIZE - j,
  865. "%s", dbg_data.buf[i]);
  866. read_unlock_irqrestore(&dbg_data.lck, flags);
  867. return n;
  868. }
  869. /**
  870. * store_events: configure if events are going to be also printed to console
  871. *
  872. * Check "device.h" for details
  873. */
  874. static ssize_t store_events(struct device *dev, struct device_attribute *attr,
  875. const char *buf, size_t count)
  876. {
  877. unsigned tty;
  878. if (attr == NULL || buf == NULL) {
  879. dev_err(dev, "[%s] EINVAL\n", __func__);
  880. goto done;
  881. }
  882. if (sscanf(buf, "%u", &tty) != 1 || tty > 1) {
  883. dev_err(dev, "<1|0>: enable|disable console log\n");
  884. goto done;
  885. }
  886. dbg_data.tty = tty;
  887. dev_info(dev, "tty = %u", dbg_data.tty);
  888. done:
  889. return count;
  890. }
  891. static DEVICE_ATTR(events, S_IRUSR | S_IWUSR, show_events, store_events);
  892. /**
  893. * show_inters: interrupt status, enable status and historic
  894. *
  895. * Check "device.h" for details
  896. */
  897. static ssize_t show_inters(struct device *dev, struct device_attribute *attr,
  898. char *buf)
  899. {
  900. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  901. unsigned long flags;
  902. u32 intr;
  903. unsigned i, j, n = 0;
  904. if (attr == NULL || buf == NULL) {
  905. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  906. return 0;
  907. }
  908. spin_lock_irqsave(&udc->lock, flags);
  909. n += scnprintf(buf + n, PAGE_SIZE - n,
  910. "status = %08x\n", hw_read_intr_status(udc));
  911. n += scnprintf(buf + n, PAGE_SIZE - n,
  912. "enable = %08x\n", hw_read_intr_enable(udc));
  913. n += scnprintf(buf + n, PAGE_SIZE - n, "*test = %d\n",
  914. isr_statistics.test);
  915. n += scnprintf(buf + n, PAGE_SIZE - n, "? ui = %d\n",
  916. isr_statistics.ui);
  917. n += scnprintf(buf + n, PAGE_SIZE - n, "? uei = %d\n",
  918. isr_statistics.uei);
  919. n += scnprintf(buf + n, PAGE_SIZE - n, "? pci = %d\n",
  920. isr_statistics.pci);
  921. n += scnprintf(buf + n, PAGE_SIZE - n, "? uri = %d\n",
  922. isr_statistics.uri);
  923. n += scnprintf(buf + n, PAGE_SIZE - n, "? sli = %d\n",
  924. isr_statistics.sli);
  925. n += scnprintf(buf + n, PAGE_SIZE - n, "*none = %d\n",
  926. isr_statistics.none);
  927. n += scnprintf(buf + n, PAGE_SIZE - n, "*hndl = %d\n",
  928. isr_statistics.hndl.cnt);
  929. for (i = isr_statistics.hndl.idx, j = 0; j <= ISR_MASK; j++, i++) {
  930. i &= ISR_MASK;
  931. intr = isr_statistics.hndl.buf[i];
  932. if (USBi_UI & intr)
  933. n += scnprintf(buf + n, PAGE_SIZE - n, "ui ");
  934. intr &= ~USBi_UI;
  935. if (USBi_UEI & intr)
  936. n += scnprintf(buf + n, PAGE_SIZE - n, "uei ");
  937. intr &= ~USBi_UEI;
  938. if (USBi_PCI & intr)
  939. n += scnprintf(buf + n, PAGE_SIZE - n, "pci ");
  940. intr &= ~USBi_PCI;
  941. if (USBi_URI & intr)
  942. n += scnprintf(buf + n, PAGE_SIZE - n, "uri ");
  943. intr &= ~USBi_URI;
  944. if (USBi_SLI & intr)
  945. n += scnprintf(buf + n, PAGE_SIZE - n, "sli ");
  946. intr &= ~USBi_SLI;
  947. if (intr)
  948. n += scnprintf(buf + n, PAGE_SIZE - n, "??? ");
  949. if (isr_statistics.hndl.buf[i])
  950. n += scnprintf(buf + n, PAGE_SIZE - n, "\n");
  951. }
  952. spin_unlock_irqrestore(&udc->lock, flags);
  953. return n;
  954. }
  955. /**
  956. * store_inters: enable & force or disable an individual interrutps
  957. * (to be used for test purposes only)
  958. *
  959. * Check "device.h" for details
  960. */
  961. static ssize_t store_inters(struct device *dev, struct device_attribute *attr,
  962. const char *buf, size_t count)
  963. {
  964. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  965. unsigned long flags;
  966. unsigned en, bit;
  967. if (attr == NULL || buf == NULL) {
  968. dev_err(udc->dev, "EINVAL\n");
  969. goto done;
  970. }
  971. if (sscanf(buf, "%u %u", &en, &bit) != 2 || en > 1) {
  972. dev_err(udc->dev, "<1|0> <bit>: enable|disable interrupt\n");
  973. goto done;
  974. }
  975. spin_lock_irqsave(&udc->lock, flags);
  976. if (en) {
  977. if (hw_intr_force(udc, bit))
  978. dev_err(dev, "invalid bit number\n");
  979. else
  980. isr_statistics.test++;
  981. } else {
  982. if (hw_intr_clear(udc, bit))
  983. dev_err(dev, "invalid bit number\n");
  984. }
  985. spin_unlock_irqrestore(&udc->lock, flags);
  986. done:
  987. return count;
  988. }
  989. static DEVICE_ATTR(inters, S_IRUSR | S_IWUSR, show_inters, store_inters);
  990. /**
  991. * show_port_test: reads port test mode
  992. *
  993. * Check "device.h" for details
  994. */
  995. static ssize_t show_port_test(struct device *dev,
  996. struct device_attribute *attr, char *buf)
  997. {
  998. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  999. unsigned long flags;
  1000. unsigned mode;
  1001. if (attr == NULL || buf == NULL) {
  1002. dev_err(udc->dev, "EINVAL\n");
  1003. return 0;
  1004. }
  1005. spin_lock_irqsave(&udc->lock, flags);
  1006. mode = hw_port_test_get(udc);
  1007. spin_unlock_irqrestore(&udc->lock, flags);
  1008. return scnprintf(buf, PAGE_SIZE, "mode = %u\n", mode);
  1009. }
  1010. /**
  1011. * store_port_test: writes port test mode
  1012. *
  1013. * Check "device.h" for details
  1014. */
  1015. static ssize_t store_port_test(struct device *dev,
  1016. struct device_attribute *attr,
  1017. const char *buf, size_t count)
  1018. {
  1019. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1020. unsigned long flags;
  1021. unsigned mode;
  1022. if (attr == NULL || buf == NULL) {
  1023. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1024. goto done;
  1025. }
  1026. if (sscanf(buf, "%u", &mode) != 1) {
  1027. dev_err(udc->dev, "<mode>: set port test mode");
  1028. goto done;
  1029. }
  1030. spin_lock_irqsave(&udc->lock, flags);
  1031. if (hw_port_test_set(udc, mode))
  1032. dev_err(udc->dev, "invalid mode\n");
  1033. spin_unlock_irqrestore(&udc->lock, flags);
  1034. done:
  1035. return count;
  1036. }
  1037. static DEVICE_ATTR(port_test, S_IRUSR | S_IWUSR,
  1038. show_port_test, store_port_test);
  1039. /**
  1040. * show_qheads: DMA contents of all queue heads
  1041. *
  1042. * Check "device.h" for details
  1043. */
  1044. static ssize_t show_qheads(struct device *dev, struct device_attribute *attr,
  1045. char *buf)
  1046. {
  1047. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1048. unsigned long flags;
  1049. unsigned i, j, n = 0;
  1050. if (attr == NULL || buf == NULL) {
  1051. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1052. return 0;
  1053. }
  1054. spin_lock_irqsave(&udc->lock, flags);
  1055. for (i = 0; i < udc->hw_ep_max/2; i++) {
  1056. struct ci13xxx_ep *mEpRx = &udc->ci13xxx_ep[i];
  1057. struct ci13xxx_ep *mEpTx =
  1058. &udc->ci13xxx_ep[i + udc->hw_ep_max/2];
  1059. n += scnprintf(buf + n, PAGE_SIZE - n,
  1060. "EP=%02i: RX=%08X TX=%08X\n",
  1061. i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
  1062. for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++) {
  1063. n += scnprintf(buf + n, PAGE_SIZE - n,
  1064. " %04X: %08X %08X\n", j,
  1065. *((u32 *)mEpRx->qh.ptr + j),
  1066. *((u32 *)mEpTx->qh.ptr + j));
  1067. }
  1068. }
  1069. spin_unlock_irqrestore(&udc->lock, flags);
  1070. return n;
  1071. }
  1072. static DEVICE_ATTR(qheads, S_IRUSR, show_qheads, NULL);
  1073. /**
  1074. * show_registers: dumps all registers
  1075. *
  1076. * Check "device.h" for details
  1077. */
  1078. #define DUMP_ENTRIES 512
  1079. static ssize_t show_registers(struct device *dev,
  1080. struct device_attribute *attr, char *buf)
  1081. {
  1082. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1083. unsigned long flags;
  1084. u32 *dump;
  1085. unsigned i, k, n = 0;
  1086. if (attr == NULL || buf == NULL) {
  1087. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1088. return 0;
  1089. }
  1090. dump = kmalloc(sizeof(u32) * DUMP_ENTRIES, GFP_KERNEL);
  1091. if (!dump) {
  1092. dev_err(udc->dev, "%s: out of memory\n", __func__);
  1093. return 0;
  1094. }
  1095. spin_lock_irqsave(&udc->lock, flags);
  1096. k = hw_register_read(udc, dump, DUMP_ENTRIES);
  1097. spin_unlock_irqrestore(&udc->lock, flags);
  1098. for (i = 0; i < k; i++) {
  1099. n += scnprintf(buf + n, PAGE_SIZE - n,
  1100. "reg[0x%04X] = 0x%08X\n",
  1101. i * (unsigned)sizeof(u32), dump[i]);
  1102. }
  1103. kfree(dump);
  1104. return n;
  1105. }
  1106. /**
  1107. * store_registers: writes value to register address
  1108. *
  1109. * Check "device.h" for details
  1110. */
  1111. static ssize_t store_registers(struct device *dev,
  1112. struct device_attribute *attr,
  1113. const char *buf, size_t count)
  1114. {
  1115. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1116. unsigned long addr, data, flags;
  1117. if (attr == NULL || buf == NULL) {
  1118. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1119. goto done;
  1120. }
  1121. if (sscanf(buf, "%li %li", &addr, &data) != 2) {
  1122. dev_err(udc->dev,
  1123. "<addr> <data>: write data to register address\n");
  1124. goto done;
  1125. }
  1126. spin_lock_irqsave(&udc->lock, flags);
  1127. if (hw_register_write(udc, addr, data))
  1128. dev_err(udc->dev, "invalid address range\n");
  1129. spin_unlock_irqrestore(&udc->lock, flags);
  1130. done:
  1131. return count;
  1132. }
  1133. static DEVICE_ATTR(registers, S_IRUSR | S_IWUSR,
  1134. show_registers, store_registers);
  1135. /**
  1136. * show_requests: DMA contents of all requests currently queued (all endpts)
  1137. *
  1138. * Check "device.h" for details
  1139. */
  1140. static ssize_t show_requests(struct device *dev, struct device_attribute *attr,
  1141. char *buf)
  1142. {
  1143. struct ci13xxx *udc = container_of(dev, struct ci13xxx, gadget.dev);
  1144. unsigned long flags;
  1145. struct list_head *ptr = NULL;
  1146. struct ci13xxx_req *req = NULL;
  1147. unsigned i, j, n = 0, qSize = sizeof(struct ci13xxx_td)/sizeof(u32);
  1148. if (attr == NULL || buf == NULL) {
  1149. dev_err(udc->dev, "[%s] EINVAL\n", __func__);
  1150. return 0;
  1151. }
  1152. spin_lock_irqsave(&udc->lock, flags);
  1153. for (i = 0; i < udc->hw_ep_max; i++)
  1154. list_for_each(ptr, &udc->ci13xxx_ep[i].qh.queue)
  1155. {
  1156. req = list_entry(ptr, struct ci13xxx_req, queue);
  1157. n += scnprintf(buf + n, PAGE_SIZE - n,
  1158. "EP=%02i: TD=%08X %s\n",
  1159. i % udc->hw_ep_max/2, (u32)req->dma,
  1160. ((i < udc->hw_ep_max/2) ? "RX" : "TX"));
  1161. for (j = 0; j < qSize; j++)
  1162. n += scnprintf(buf + n, PAGE_SIZE - n,
  1163. " %04X: %08X\n", j,
  1164. *((u32 *)req->ptr + j));
  1165. }
  1166. spin_unlock_irqrestore(&udc->lock, flags);
  1167. return n;
  1168. }
  1169. static DEVICE_ATTR(requests, S_IRUSR, show_requests, NULL);
  1170. /**
  1171. * dbg_create_files: initializes the attribute interface
  1172. * @dev: device
  1173. *
  1174. * This function returns an error code
  1175. */
  1176. __maybe_unused static int dbg_create_files(struct device *dev)
  1177. {
  1178. int retval = 0;
  1179. if (dev == NULL)
  1180. return -EINVAL;
  1181. retval = device_create_file(dev, &dev_attr_device);
  1182. if (retval)
  1183. goto done;
  1184. retval = device_create_file(dev, &dev_attr_driver);
  1185. if (retval)
  1186. goto rm_device;
  1187. retval = device_create_file(dev, &dev_attr_events);
  1188. if (retval)
  1189. goto rm_driver;
  1190. retval = device_create_file(dev, &dev_attr_inters);
  1191. if (retval)
  1192. goto rm_events;
  1193. retval = device_create_file(dev, &dev_attr_port_test);
  1194. if (retval)
  1195. goto rm_inters;
  1196. retval = device_create_file(dev, &dev_attr_qheads);
  1197. if (retval)
  1198. goto rm_port_test;
  1199. retval = device_create_file(dev, &dev_attr_registers);
  1200. if (retval)
  1201. goto rm_qheads;
  1202. retval = device_create_file(dev, &dev_attr_requests);
  1203. if (retval)
  1204. goto rm_registers;
  1205. return 0;
  1206. rm_registers:
  1207. device_remove_file(dev, &dev_attr_registers);
  1208. rm_qheads:
  1209. device_remove_file(dev, &dev_attr_qheads);
  1210. rm_port_test:
  1211. device_remove_file(dev, &dev_attr_port_test);
  1212. rm_inters:
  1213. device_remove_file(dev, &dev_attr_inters);
  1214. rm_events:
  1215. device_remove_file(dev, &dev_attr_events);
  1216. rm_driver:
  1217. device_remove_file(dev, &dev_attr_driver);
  1218. rm_device:
  1219. device_remove_file(dev, &dev_attr_device);
  1220. done:
  1221. return retval;
  1222. }
  1223. /**
  1224. * dbg_remove_files: destroys the attribute interface
  1225. * @dev: device
  1226. *
  1227. * This function returns an error code
  1228. */
  1229. __maybe_unused static int dbg_remove_files(struct device *dev)
  1230. {
  1231. if (dev == NULL)
  1232. return -EINVAL;
  1233. device_remove_file(dev, &dev_attr_requests);
  1234. device_remove_file(dev, &dev_attr_registers);
  1235. device_remove_file(dev, &dev_attr_qheads);
  1236. device_remove_file(dev, &dev_attr_port_test);
  1237. device_remove_file(dev, &dev_attr_inters);
  1238. device_remove_file(dev, &dev_attr_events);
  1239. device_remove_file(dev, &dev_attr_driver);
  1240. device_remove_file(dev, &dev_attr_device);
  1241. return 0;
  1242. }
  1243. /******************************************************************************
  1244. * UTIL block
  1245. *****************************************************************************/
  1246. /**
  1247. * _usb_addr: calculates endpoint address from direction & number
  1248. * @ep: endpoint
  1249. */
  1250. static inline u8 _usb_addr(struct ci13xxx_ep *ep)
  1251. {
  1252. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  1253. }
  1254. /**
  1255. * _hardware_queue: configures a request at hardware level
  1256. * @gadget: gadget
  1257. * @mEp: endpoint
  1258. *
  1259. * This function returns an error code
  1260. */
  1261. static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1262. {
  1263. struct ci13xxx *udc = mEp->udc;
  1264. unsigned i;
  1265. int ret = 0;
  1266. unsigned length = mReq->req.length;
  1267. /* don't queue twice */
  1268. if (mReq->req.status == -EALREADY)
  1269. return -EALREADY;
  1270. mReq->req.status = -EALREADY;
  1271. if (length && mReq->req.dma == DMA_ADDR_INVALID) {
  1272. mReq->req.dma = \
  1273. dma_map_single(mEp->device, mReq->req.buf,
  1274. length, mEp->dir ? DMA_TO_DEVICE :
  1275. DMA_FROM_DEVICE);
  1276. if (mReq->req.dma == 0)
  1277. return -ENOMEM;
  1278. mReq->map = 1;
  1279. }
  1280. if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
  1281. mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
  1282. &mReq->zdma);
  1283. if (mReq->zptr == NULL) {
  1284. if (mReq->map) {
  1285. dma_unmap_single(mEp->device, mReq->req.dma,
  1286. length, mEp->dir ? DMA_TO_DEVICE :
  1287. DMA_FROM_DEVICE);
  1288. mReq->req.dma = DMA_ADDR_INVALID;
  1289. mReq->map = 0;
  1290. }
  1291. return -ENOMEM;
  1292. }
  1293. memset(mReq->zptr, 0, sizeof(*mReq->zptr));
  1294. mReq->zptr->next = TD_TERMINATE;
  1295. mReq->zptr->token = TD_STATUS_ACTIVE;
  1296. if (!mReq->req.no_interrupt)
  1297. mReq->zptr->token |= TD_IOC;
  1298. }
  1299. /*
  1300. * TD configuration
  1301. * TODO - handle requests which spawns into several TDs
  1302. */
  1303. memset(mReq->ptr, 0, sizeof(*mReq->ptr));
  1304. mReq->ptr->token = length << ffs_nr(TD_TOTAL_BYTES);
  1305. mReq->ptr->token &= TD_TOTAL_BYTES;
  1306. mReq->ptr->token |= TD_STATUS_ACTIVE;
  1307. if (mReq->zptr) {
  1308. mReq->ptr->next = mReq->zdma;
  1309. } else {
  1310. mReq->ptr->next = TD_TERMINATE;
  1311. if (!mReq->req.no_interrupt)
  1312. mReq->ptr->token |= TD_IOC;
  1313. }
  1314. mReq->ptr->page[0] = mReq->req.dma;
  1315. for (i = 1; i < 5; i++)
  1316. mReq->ptr->page[i] =
  1317. (mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
  1318. if (!list_empty(&mEp->qh.queue)) {
  1319. struct ci13xxx_req *mReqPrev;
  1320. int n = hw_ep_bit(mEp->num, mEp->dir);
  1321. int tmp_stat;
  1322. mReqPrev = list_entry(mEp->qh.queue.prev,
  1323. struct ci13xxx_req, queue);
  1324. if (mReqPrev->zptr)
  1325. mReqPrev->zptr->next = mReq->dma & TD_ADDR_MASK;
  1326. else
  1327. mReqPrev->ptr->next = mReq->dma & TD_ADDR_MASK;
  1328. wmb();
  1329. if (hw_read(udc, OP_ENDPTPRIME, BIT(n)))
  1330. goto done;
  1331. do {
  1332. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  1333. tmp_stat = hw_read(udc, OP_ENDPTSTAT, BIT(n));
  1334. } while (!hw_read(udc, OP_USBCMD, USBCMD_ATDTW));
  1335. hw_write(udc, OP_USBCMD, USBCMD_ATDTW, 0);
  1336. if (tmp_stat)
  1337. goto done;
  1338. }
  1339. /* QH configuration */
  1340. mEp->qh.ptr->td.next = mReq->dma; /* TERMINATE = 0 */
  1341. mEp->qh.ptr->td.token &= ~TD_STATUS; /* clear status */
  1342. mEp->qh.ptr->cap |= QH_ZLT;
  1343. wmb(); /* synchronize before ep prime */
  1344. ret = hw_ep_prime(udc, mEp->num, mEp->dir,
  1345. mEp->type == USB_ENDPOINT_XFER_CONTROL);
  1346. done:
  1347. return ret;
  1348. }
  1349. /**
  1350. * _hardware_dequeue: handles a request at hardware level
  1351. * @gadget: gadget
  1352. * @mEp: endpoint
  1353. *
  1354. * This function returns an error code
  1355. */
  1356. static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
  1357. {
  1358. if (mReq->req.status != -EALREADY)
  1359. return -EINVAL;
  1360. if ((TD_STATUS_ACTIVE & mReq->ptr->token) != 0)
  1361. return -EBUSY;
  1362. if (mReq->zptr) {
  1363. if ((TD_STATUS_ACTIVE & mReq->zptr->token) != 0)
  1364. return -EBUSY;
  1365. dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
  1366. mReq->zptr = NULL;
  1367. }
  1368. mReq->req.status = 0;
  1369. if (mReq->map) {
  1370. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1371. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1372. mReq->req.dma = DMA_ADDR_INVALID;
  1373. mReq->map = 0;
  1374. }
  1375. mReq->req.status = mReq->ptr->token & TD_STATUS;
  1376. if ((TD_STATUS_HALTED & mReq->req.status) != 0)
  1377. mReq->req.status = -1;
  1378. else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
  1379. mReq->req.status = -1;
  1380. else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
  1381. mReq->req.status = -1;
  1382. mReq->req.actual = mReq->ptr->token & TD_TOTAL_BYTES;
  1383. mReq->req.actual >>= ffs_nr(TD_TOTAL_BYTES);
  1384. mReq->req.actual = mReq->req.length - mReq->req.actual;
  1385. mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
  1386. return mReq->req.actual;
  1387. }
  1388. /**
  1389. * _ep_nuke: dequeues all endpoint requests
  1390. * @mEp: endpoint
  1391. *
  1392. * This function returns an error code
  1393. * Caller must hold lock
  1394. */
  1395. static int _ep_nuke(struct ci13xxx_ep *mEp)
  1396. __releases(mEp->lock)
  1397. __acquires(mEp->lock)
  1398. {
  1399. if (mEp == NULL)
  1400. return -EINVAL;
  1401. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  1402. while (!list_empty(&mEp->qh.queue)) {
  1403. /* pop oldest request */
  1404. struct ci13xxx_req *mReq = \
  1405. list_entry(mEp->qh.queue.next,
  1406. struct ci13xxx_req, queue);
  1407. list_del_init(&mReq->queue);
  1408. mReq->req.status = -ESHUTDOWN;
  1409. if (mReq->req.complete != NULL) {
  1410. spin_unlock(mEp->lock);
  1411. mReq->req.complete(&mEp->ep, &mReq->req);
  1412. spin_lock(mEp->lock);
  1413. }
  1414. }
  1415. return 0;
  1416. }
  1417. /**
  1418. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  1419. * @gadget: gadget
  1420. *
  1421. * This function returns an error code
  1422. */
  1423. static int _gadget_stop_activity(struct usb_gadget *gadget)
  1424. {
  1425. struct usb_ep *ep;
  1426. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  1427. unsigned long flags;
  1428. if (gadget == NULL)
  1429. return -EINVAL;
  1430. spin_lock_irqsave(&udc->lock, flags);
  1431. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1432. udc->remote_wakeup = 0;
  1433. udc->suspended = 0;
  1434. spin_unlock_irqrestore(&udc->lock, flags);
  1435. /* flush all endpoints */
  1436. gadget_for_each_ep(ep, gadget) {
  1437. usb_ep_fifo_flush(ep);
  1438. }
  1439. usb_ep_fifo_flush(&udc->ep0out->ep);
  1440. usb_ep_fifo_flush(&udc->ep0in->ep);
  1441. if (udc->driver)
  1442. udc->driver->disconnect(gadget);
  1443. /* make sure to disable all endpoints */
  1444. gadget_for_each_ep(ep, gadget) {
  1445. usb_ep_disable(ep);
  1446. }
  1447. if (udc->status != NULL) {
  1448. usb_ep_free_request(&udc->ep0in->ep, udc->status);
  1449. udc->status = NULL;
  1450. }
  1451. return 0;
  1452. }
  1453. /******************************************************************************
  1454. * ISR block
  1455. *****************************************************************************/
  1456. /**
  1457. * isr_reset_handler: USB reset interrupt handler
  1458. * @udc: UDC device
  1459. *
  1460. * This function resets USB engine after a bus reset occurred
  1461. */
  1462. static void isr_reset_handler(struct ci13xxx *udc)
  1463. __releases(udc->lock)
  1464. __acquires(udc->lock)
  1465. {
  1466. int retval;
  1467. dbg_event(0xFF, "BUS RST", 0);
  1468. spin_unlock(&udc->lock);
  1469. retval = _gadget_stop_activity(&udc->gadget);
  1470. if (retval)
  1471. goto done;
  1472. retval = hw_usb_reset(udc);
  1473. if (retval)
  1474. goto done;
  1475. udc->status = usb_ep_alloc_request(&udc->ep0in->ep, GFP_ATOMIC);
  1476. if (udc->status == NULL)
  1477. retval = -ENOMEM;
  1478. spin_lock(&udc->lock);
  1479. done:
  1480. if (retval)
  1481. dev_err(udc->dev, "error: %i\n", retval);
  1482. }
  1483. /**
  1484. * isr_get_status_complete: get_status request complete function
  1485. * @ep: endpoint
  1486. * @req: request handled
  1487. *
  1488. * Caller must release lock
  1489. */
  1490. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  1491. {
  1492. if (ep == NULL || req == NULL)
  1493. return;
  1494. kfree(req->buf);
  1495. usb_ep_free_request(ep, req);
  1496. }
  1497. /**
  1498. * isr_get_status_response: get_status request response
  1499. * @udc: udc struct
  1500. * @setup: setup request packet
  1501. *
  1502. * This function returns an error code
  1503. */
  1504. static int isr_get_status_response(struct ci13xxx *udc,
  1505. struct usb_ctrlrequest *setup)
  1506. __releases(mEp->lock)
  1507. __acquires(mEp->lock)
  1508. {
  1509. struct ci13xxx_ep *mEp = udc->ep0in;
  1510. struct usb_request *req = NULL;
  1511. gfp_t gfp_flags = GFP_ATOMIC;
  1512. int dir, num, retval;
  1513. if (mEp == NULL || setup == NULL)
  1514. return -EINVAL;
  1515. spin_unlock(mEp->lock);
  1516. req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
  1517. spin_lock(mEp->lock);
  1518. if (req == NULL)
  1519. return -ENOMEM;
  1520. req->complete = isr_get_status_complete;
  1521. req->length = 2;
  1522. req->buf = kzalloc(req->length, gfp_flags);
  1523. if (req->buf == NULL) {
  1524. retval = -ENOMEM;
  1525. goto err_free_req;
  1526. }
  1527. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1528. /* Assume that device is bus powered for now. */
  1529. *(u16 *)req->buf = udc->remote_wakeup << 1;
  1530. retval = 0;
  1531. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  1532. == USB_RECIP_ENDPOINT) {
  1533. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  1534. TX : RX;
  1535. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  1536. *(u16 *)req->buf = hw_ep_get_halt(udc, num, dir);
  1537. }
  1538. /* else do nothing; reserved for future use */
  1539. spin_unlock(mEp->lock);
  1540. retval = usb_ep_queue(&mEp->ep, req, gfp_flags);
  1541. spin_lock(mEp->lock);
  1542. if (retval)
  1543. goto err_free_buf;
  1544. return 0;
  1545. err_free_buf:
  1546. kfree(req->buf);
  1547. err_free_req:
  1548. spin_unlock(mEp->lock);
  1549. usb_ep_free_request(&mEp->ep, req);
  1550. spin_lock(mEp->lock);
  1551. return retval;
  1552. }
  1553. /**
  1554. * isr_setup_status_complete: setup_status request complete function
  1555. * @ep: endpoint
  1556. * @req: request handled
  1557. *
  1558. * Caller must release lock. Put the port in test mode if test mode
  1559. * feature is selected.
  1560. */
  1561. static void
  1562. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  1563. {
  1564. struct ci13xxx *udc = req->context;
  1565. unsigned long flags;
  1566. spin_lock_irqsave(&udc->lock, flags);
  1567. if (udc->test_mode)
  1568. hw_port_test_set(udc, udc->test_mode);
  1569. spin_unlock_irqrestore(&udc->lock, flags);
  1570. }
  1571. /**
  1572. * isr_setup_status_phase: queues the status phase of a setup transation
  1573. * @udc: udc struct
  1574. *
  1575. * This function returns an error code
  1576. */
  1577. static int isr_setup_status_phase(struct ci13xxx *udc)
  1578. __releases(mEp->lock)
  1579. __acquires(mEp->lock)
  1580. {
  1581. int retval;
  1582. struct ci13xxx_ep *mEp;
  1583. mEp = (udc->ep0_dir == TX) ? udc->ep0out : udc->ep0in;
  1584. udc->status->context = udc;
  1585. udc->status->complete = isr_setup_status_complete;
  1586. spin_unlock(mEp->lock);
  1587. retval = usb_ep_queue(&mEp->ep, udc->status, GFP_ATOMIC);
  1588. spin_lock(mEp->lock);
  1589. return retval;
  1590. }
  1591. /**
  1592. * isr_tr_complete_low: transaction complete low level handler
  1593. * @mEp: endpoint
  1594. *
  1595. * This function returns an error code
  1596. * Caller must hold lock
  1597. */
  1598. static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
  1599. __releases(mEp->lock)
  1600. __acquires(mEp->lock)
  1601. {
  1602. struct ci13xxx_req *mReq, *mReqTemp;
  1603. struct ci13xxx_ep *mEpTemp = mEp;
  1604. int uninitialized_var(retval);
  1605. if (list_empty(&mEp->qh.queue))
  1606. return -EINVAL;
  1607. list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
  1608. queue) {
  1609. retval = _hardware_dequeue(mEp, mReq);
  1610. if (retval < 0)
  1611. break;
  1612. list_del_init(&mReq->queue);
  1613. dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
  1614. if (mReq->req.complete != NULL) {
  1615. spin_unlock(mEp->lock);
  1616. if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
  1617. mReq->req.length)
  1618. mEpTemp = mEp->udc->ep0in;
  1619. mReq->req.complete(&mEpTemp->ep, &mReq->req);
  1620. spin_lock(mEp->lock);
  1621. }
  1622. }
  1623. if (retval == -EBUSY)
  1624. retval = 0;
  1625. if (retval < 0)
  1626. dbg_event(_usb_addr(mEp), "DONE", retval);
  1627. return retval;
  1628. }
  1629. /**
  1630. * isr_tr_complete_handler: transaction complete interrupt handler
  1631. * @udc: UDC descriptor
  1632. *
  1633. * This function handles traffic events
  1634. */
  1635. static void isr_tr_complete_handler(struct ci13xxx *udc)
  1636. __releases(udc->lock)
  1637. __acquires(udc->lock)
  1638. {
  1639. unsigned i;
  1640. u8 tmode = 0;
  1641. for (i = 0; i < udc->hw_ep_max; i++) {
  1642. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  1643. int type, num, dir, err = -EINVAL;
  1644. struct usb_ctrlrequest req;
  1645. if (mEp->ep.desc == NULL)
  1646. continue; /* not configured */
  1647. if (hw_test_and_clear_complete(udc, i)) {
  1648. err = isr_tr_complete_low(mEp);
  1649. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1650. if (err > 0) /* needs status phase */
  1651. err = isr_setup_status_phase(udc);
  1652. if (err < 0) {
  1653. dbg_event(_usb_addr(mEp),
  1654. "ERROR", err);
  1655. spin_unlock(&udc->lock);
  1656. if (usb_ep_set_halt(&mEp->ep))
  1657. dev_err(udc->dev,
  1658. "error: ep_set_halt\n");
  1659. spin_lock(&udc->lock);
  1660. }
  1661. }
  1662. }
  1663. if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
  1664. !hw_test_and_clear_setup_status(udc, i))
  1665. continue;
  1666. if (i != 0) {
  1667. dev_warn(udc->dev, "ctrl traffic at endpoint %d\n", i);
  1668. continue;
  1669. }
  1670. /*
  1671. * Flush data and handshake transactions of previous
  1672. * setup packet.
  1673. */
  1674. _ep_nuke(udc->ep0out);
  1675. _ep_nuke(udc->ep0in);
  1676. /* read_setup_packet */
  1677. do {
  1678. hw_test_and_set_setup_guard(udc);
  1679. memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
  1680. } while (!hw_test_and_clear_setup_guard(udc));
  1681. type = req.bRequestType;
  1682. udc->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  1683. dbg_setup(_usb_addr(mEp), &req);
  1684. switch (req.bRequest) {
  1685. case USB_REQ_CLEAR_FEATURE:
  1686. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1687. le16_to_cpu(req.wValue) ==
  1688. USB_ENDPOINT_HALT) {
  1689. if (req.wLength != 0)
  1690. break;
  1691. num = le16_to_cpu(req.wIndex);
  1692. dir = num & USB_ENDPOINT_DIR_MASK;
  1693. num &= USB_ENDPOINT_NUMBER_MASK;
  1694. if (dir) /* TX */
  1695. num += udc->hw_ep_max/2;
  1696. if (!udc->ci13xxx_ep[num].wedge) {
  1697. spin_unlock(&udc->lock);
  1698. err = usb_ep_clear_halt(
  1699. &udc->ci13xxx_ep[num].ep);
  1700. spin_lock(&udc->lock);
  1701. if (err)
  1702. break;
  1703. }
  1704. err = isr_setup_status_phase(udc);
  1705. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  1706. le16_to_cpu(req.wValue) ==
  1707. USB_DEVICE_REMOTE_WAKEUP) {
  1708. if (req.wLength != 0)
  1709. break;
  1710. udc->remote_wakeup = 0;
  1711. err = isr_setup_status_phase(udc);
  1712. } else {
  1713. goto delegate;
  1714. }
  1715. break;
  1716. case USB_REQ_GET_STATUS:
  1717. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  1718. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  1719. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  1720. goto delegate;
  1721. if (le16_to_cpu(req.wLength) != 2 ||
  1722. le16_to_cpu(req.wValue) != 0)
  1723. break;
  1724. err = isr_get_status_response(udc, &req);
  1725. break;
  1726. case USB_REQ_SET_ADDRESS:
  1727. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  1728. goto delegate;
  1729. if (le16_to_cpu(req.wLength) != 0 ||
  1730. le16_to_cpu(req.wIndex) != 0)
  1731. break;
  1732. err = hw_usb_set_address(udc,
  1733. (u8)le16_to_cpu(req.wValue));
  1734. if (err)
  1735. break;
  1736. err = isr_setup_status_phase(udc);
  1737. break;
  1738. case USB_REQ_SET_FEATURE:
  1739. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  1740. le16_to_cpu(req.wValue) ==
  1741. USB_ENDPOINT_HALT) {
  1742. if (req.wLength != 0)
  1743. break;
  1744. num = le16_to_cpu(req.wIndex);
  1745. dir = num & USB_ENDPOINT_DIR_MASK;
  1746. num &= USB_ENDPOINT_NUMBER_MASK;
  1747. if (dir) /* TX */
  1748. num += udc->hw_ep_max/2;
  1749. spin_unlock(&udc->lock);
  1750. err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
  1751. spin_lock(&udc->lock);
  1752. if (!err)
  1753. isr_setup_status_phase(udc);
  1754. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  1755. if (req.wLength != 0)
  1756. break;
  1757. switch (le16_to_cpu(req.wValue)) {
  1758. case USB_DEVICE_REMOTE_WAKEUP:
  1759. udc->remote_wakeup = 1;
  1760. err = isr_setup_status_phase(udc);
  1761. break;
  1762. case USB_DEVICE_TEST_MODE:
  1763. tmode = le16_to_cpu(req.wIndex) >> 8;
  1764. switch (tmode) {
  1765. case TEST_J:
  1766. case TEST_K:
  1767. case TEST_SE0_NAK:
  1768. case TEST_PACKET:
  1769. case TEST_FORCE_EN:
  1770. udc->test_mode = tmode;
  1771. err = isr_setup_status_phase(
  1772. udc);
  1773. break;
  1774. default:
  1775. break;
  1776. }
  1777. default:
  1778. goto delegate;
  1779. }
  1780. } else {
  1781. goto delegate;
  1782. }
  1783. break;
  1784. default:
  1785. delegate:
  1786. if (req.wLength == 0) /* no data phase */
  1787. udc->ep0_dir = TX;
  1788. spin_unlock(&udc->lock);
  1789. err = udc->driver->setup(&udc->gadget, &req);
  1790. spin_lock(&udc->lock);
  1791. break;
  1792. }
  1793. if (err < 0) {
  1794. dbg_event(_usb_addr(mEp), "ERROR", err);
  1795. spin_unlock(&udc->lock);
  1796. if (usb_ep_set_halt(&mEp->ep))
  1797. dev_err(udc->dev, "error: ep_set_halt\n");
  1798. spin_lock(&udc->lock);
  1799. }
  1800. }
  1801. }
  1802. /******************************************************************************
  1803. * ENDPT block
  1804. *****************************************************************************/
  1805. /**
  1806. * ep_enable: configure endpoint, making it usable
  1807. *
  1808. * Check usb_ep_enable() at "usb_gadget.h" for details
  1809. */
  1810. static int ep_enable(struct usb_ep *ep,
  1811. const struct usb_endpoint_descriptor *desc)
  1812. {
  1813. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1814. int retval = 0;
  1815. unsigned long flags;
  1816. if (ep == NULL || desc == NULL)
  1817. return -EINVAL;
  1818. spin_lock_irqsave(mEp->lock, flags);
  1819. /* only internal SW should enable ctrl endpts */
  1820. mEp->ep.desc = desc;
  1821. if (!list_empty(&mEp->qh.queue))
  1822. dev_warn(mEp->udc->dev, "enabling a non-empty endpoint!\n");
  1823. mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1824. mEp->num = usb_endpoint_num(desc);
  1825. mEp->type = usb_endpoint_type(desc);
  1826. mEp->ep.maxpacket = usb_endpoint_maxp(desc);
  1827. dbg_event(_usb_addr(mEp), "ENABLE", 0);
  1828. mEp->qh.ptr->cap = 0;
  1829. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1830. mEp->qh.ptr->cap |= QH_IOS;
  1831. else if (mEp->type == USB_ENDPOINT_XFER_ISOC)
  1832. mEp->qh.ptr->cap &= ~QH_MULT;
  1833. else
  1834. mEp->qh.ptr->cap &= ~QH_ZLT;
  1835. mEp->qh.ptr->cap |=
  1836. (mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
  1837. mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
  1838. /*
  1839. * Enable endpoints in the HW other than ep0 as ep0
  1840. * is always enabled
  1841. */
  1842. if (mEp->num)
  1843. retval |= hw_ep_enable(mEp->udc, mEp->num, mEp->dir, mEp->type);
  1844. spin_unlock_irqrestore(mEp->lock, flags);
  1845. return retval;
  1846. }
  1847. /**
  1848. * ep_disable: endpoint is no longer usable
  1849. *
  1850. * Check usb_ep_disable() at "usb_gadget.h" for details
  1851. */
  1852. static int ep_disable(struct usb_ep *ep)
  1853. {
  1854. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1855. int direction, retval = 0;
  1856. unsigned long flags;
  1857. if (ep == NULL)
  1858. return -EINVAL;
  1859. else if (mEp->ep.desc == NULL)
  1860. return -EBUSY;
  1861. spin_lock_irqsave(mEp->lock, flags);
  1862. /* only internal SW should disable ctrl endpts */
  1863. direction = mEp->dir;
  1864. do {
  1865. dbg_event(_usb_addr(mEp), "DISABLE", 0);
  1866. retval |= _ep_nuke(mEp);
  1867. retval |= hw_ep_disable(mEp->udc, mEp->num, mEp->dir);
  1868. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  1869. mEp->dir = (mEp->dir == TX) ? RX : TX;
  1870. } while (mEp->dir != direction);
  1871. mEp->ep.desc = NULL;
  1872. spin_unlock_irqrestore(mEp->lock, flags);
  1873. return retval;
  1874. }
  1875. /**
  1876. * ep_alloc_request: allocate a request object to use with this endpoint
  1877. *
  1878. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1879. */
  1880. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1881. {
  1882. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1883. struct ci13xxx_req *mReq = NULL;
  1884. if (ep == NULL)
  1885. return NULL;
  1886. mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
  1887. if (mReq != NULL) {
  1888. INIT_LIST_HEAD(&mReq->queue);
  1889. mReq->req.dma = DMA_ADDR_INVALID;
  1890. mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
  1891. &mReq->dma);
  1892. if (mReq->ptr == NULL) {
  1893. kfree(mReq);
  1894. mReq = NULL;
  1895. }
  1896. }
  1897. dbg_event(_usb_addr(mEp), "ALLOC", mReq == NULL);
  1898. return (mReq == NULL) ? NULL : &mReq->req;
  1899. }
  1900. /**
  1901. * ep_free_request: frees a request object
  1902. *
  1903. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1904. */
  1905. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1906. {
  1907. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1908. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1909. unsigned long flags;
  1910. if (ep == NULL || req == NULL) {
  1911. return;
  1912. } else if (!list_empty(&mReq->queue)) {
  1913. dev_err(mEp->udc->dev, "freeing queued request\n");
  1914. return;
  1915. }
  1916. spin_lock_irqsave(mEp->lock, flags);
  1917. if (mReq->ptr)
  1918. dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
  1919. kfree(mReq);
  1920. dbg_event(_usb_addr(mEp), "FREE", 0);
  1921. spin_unlock_irqrestore(mEp->lock, flags);
  1922. }
  1923. /**
  1924. * ep_queue: queues (submits) an I/O request to an endpoint
  1925. *
  1926. * Check usb_ep_queue()* at usb_gadget.h" for details
  1927. */
  1928. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1929. gfp_t __maybe_unused gfp_flags)
  1930. {
  1931. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1932. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1933. struct ci13xxx *udc = mEp->udc;
  1934. int retval = 0;
  1935. unsigned long flags;
  1936. if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
  1937. return -EINVAL;
  1938. spin_lock_irqsave(mEp->lock, flags);
  1939. if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
  1940. if (req->length)
  1941. mEp = (udc->ep0_dir == RX) ?
  1942. udc->ep0out : udc->ep0in;
  1943. if (!list_empty(&mEp->qh.queue)) {
  1944. _ep_nuke(mEp);
  1945. retval = -EOVERFLOW;
  1946. dev_warn(mEp->udc->dev, "endpoint ctrl %X nuked\n",
  1947. _usb_addr(mEp));
  1948. }
  1949. }
  1950. /* first nuke then test link, e.g. previous status has not sent */
  1951. if (!list_empty(&mReq->queue)) {
  1952. retval = -EBUSY;
  1953. dev_err(mEp->udc->dev, "request already in queue\n");
  1954. goto done;
  1955. }
  1956. if (req->length > 4 * CI13XXX_PAGE_SIZE) {
  1957. req->length = 4 * CI13XXX_PAGE_SIZE;
  1958. retval = -EMSGSIZE;
  1959. dev_warn(mEp->udc->dev, "request length truncated\n");
  1960. }
  1961. dbg_queue(_usb_addr(mEp), req, retval);
  1962. /* push request */
  1963. mReq->req.status = -EINPROGRESS;
  1964. mReq->req.actual = 0;
  1965. retval = _hardware_enqueue(mEp, mReq);
  1966. if (retval == -EALREADY) {
  1967. dbg_event(_usb_addr(mEp), "QUEUE", retval);
  1968. retval = 0;
  1969. }
  1970. if (!retval)
  1971. list_add_tail(&mReq->queue, &mEp->qh.queue);
  1972. done:
  1973. spin_unlock_irqrestore(mEp->lock, flags);
  1974. return retval;
  1975. }
  1976. /**
  1977. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1978. *
  1979. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1980. */
  1981. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1982. {
  1983. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  1984. struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
  1985. unsigned long flags;
  1986. if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
  1987. mEp->ep.desc == NULL || list_empty(&mReq->queue) ||
  1988. list_empty(&mEp->qh.queue))
  1989. return -EINVAL;
  1990. spin_lock_irqsave(mEp->lock, flags);
  1991. dbg_event(_usb_addr(mEp), "DEQUEUE", 0);
  1992. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  1993. /* pop request */
  1994. list_del_init(&mReq->queue);
  1995. if (mReq->map) {
  1996. dma_unmap_single(mEp->device, mReq->req.dma, mReq->req.length,
  1997. mEp->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  1998. mReq->req.dma = DMA_ADDR_INVALID;
  1999. mReq->map = 0;
  2000. }
  2001. req->status = -ECONNRESET;
  2002. if (mReq->req.complete != NULL) {
  2003. spin_unlock(mEp->lock);
  2004. mReq->req.complete(&mEp->ep, &mReq->req);
  2005. spin_lock(mEp->lock);
  2006. }
  2007. spin_unlock_irqrestore(mEp->lock, flags);
  2008. return 0;
  2009. }
  2010. /**
  2011. * ep_set_halt: sets the endpoint halt feature
  2012. *
  2013. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  2014. */
  2015. static int ep_set_halt(struct usb_ep *ep, int value)
  2016. {
  2017. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2018. int direction, retval = 0;
  2019. unsigned long flags;
  2020. if (ep == NULL || mEp->ep.desc == NULL)
  2021. return -EINVAL;
  2022. spin_lock_irqsave(mEp->lock, flags);
  2023. #ifndef STALL_IN
  2024. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  2025. if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
  2026. !list_empty(&mEp->qh.queue)) {
  2027. spin_unlock_irqrestore(mEp->lock, flags);
  2028. return -EAGAIN;
  2029. }
  2030. #endif
  2031. direction = mEp->dir;
  2032. do {
  2033. dbg_event(_usb_addr(mEp), "HALT", value);
  2034. retval |= hw_ep_set_halt(mEp->udc, mEp->num, mEp->dir, value);
  2035. if (!value)
  2036. mEp->wedge = 0;
  2037. if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
  2038. mEp->dir = (mEp->dir == TX) ? RX : TX;
  2039. } while (mEp->dir != direction);
  2040. spin_unlock_irqrestore(mEp->lock, flags);
  2041. return retval;
  2042. }
  2043. /**
  2044. * ep_set_wedge: sets the halt feature and ignores clear requests
  2045. *
  2046. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  2047. */
  2048. static int ep_set_wedge(struct usb_ep *ep)
  2049. {
  2050. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2051. unsigned long flags;
  2052. if (ep == NULL || mEp->ep.desc == NULL)
  2053. return -EINVAL;
  2054. spin_lock_irqsave(mEp->lock, flags);
  2055. dbg_event(_usb_addr(mEp), "WEDGE", 0);
  2056. mEp->wedge = 1;
  2057. spin_unlock_irqrestore(mEp->lock, flags);
  2058. return usb_ep_set_halt(ep);
  2059. }
  2060. /**
  2061. * ep_fifo_flush: flushes contents of a fifo
  2062. *
  2063. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  2064. */
  2065. static void ep_fifo_flush(struct usb_ep *ep)
  2066. {
  2067. struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
  2068. unsigned long flags;
  2069. if (ep == NULL) {
  2070. dev_err(mEp->udc->dev, "%02X: -EINVAL\n", _usb_addr(mEp));
  2071. return;
  2072. }
  2073. spin_lock_irqsave(mEp->lock, flags);
  2074. dbg_event(_usb_addr(mEp), "FFLUSH", 0);
  2075. hw_ep_flush(mEp->udc, mEp->num, mEp->dir);
  2076. spin_unlock_irqrestore(mEp->lock, flags);
  2077. }
  2078. /**
  2079. * Endpoint-specific part of the API to the USB controller hardware
  2080. * Check "usb_gadget.h" for details
  2081. */
  2082. static const struct usb_ep_ops usb_ep_ops = {
  2083. .enable = ep_enable,
  2084. .disable = ep_disable,
  2085. .alloc_request = ep_alloc_request,
  2086. .free_request = ep_free_request,
  2087. .queue = ep_queue,
  2088. .dequeue = ep_dequeue,
  2089. .set_halt = ep_set_halt,
  2090. .set_wedge = ep_set_wedge,
  2091. .fifo_flush = ep_fifo_flush,
  2092. };
  2093. /******************************************************************************
  2094. * GADGET block
  2095. *****************************************************************************/
  2096. static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
  2097. {
  2098. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2099. unsigned long flags;
  2100. int gadget_ready = 0;
  2101. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS))
  2102. return -EOPNOTSUPP;
  2103. spin_lock_irqsave(&udc->lock, flags);
  2104. udc->vbus_active = is_active;
  2105. if (udc->driver)
  2106. gadget_ready = 1;
  2107. spin_unlock_irqrestore(&udc->lock, flags);
  2108. if (gadget_ready) {
  2109. if (is_active) {
  2110. pm_runtime_get_sync(&_gadget->dev);
  2111. hw_device_reset(udc);
  2112. hw_device_state(udc, udc->ep0out->qh.dma);
  2113. } else {
  2114. hw_device_state(udc, 0);
  2115. if (udc->udc_driver->notify_event)
  2116. udc->udc_driver->notify_event(udc,
  2117. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2118. _gadget_stop_activity(&udc->gadget);
  2119. pm_runtime_put_sync(&_gadget->dev);
  2120. }
  2121. }
  2122. return 0;
  2123. }
  2124. static int ci13xxx_wakeup(struct usb_gadget *_gadget)
  2125. {
  2126. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2127. unsigned long flags;
  2128. int ret = 0;
  2129. spin_lock_irqsave(&udc->lock, flags);
  2130. if (!udc->remote_wakeup) {
  2131. ret = -EOPNOTSUPP;
  2132. goto out;
  2133. }
  2134. if (!hw_read(udc, OP_PORTSC, PORTSC_SUSP)) {
  2135. ret = -EINVAL;
  2136. goto out;
  2137. }
  2138. hw_write(udc, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  2139. out:
  2140. spin_unlock_irqrestore(&udc->lock, flags);
  2141. return ret;
  2142. }
  2143. static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  2144. {
  2145. struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
  2146. if (udc->transceiver)
  2147. return usb_phy_set_power(udc->transceiver, mA);
  2148. return -ENOTSUPP;
  2149. }
  2150. static int ci13xxx_start(struct usb_gadget *gadget,
  2151. struct usb_gadget_driver *driver);
  2152. static int ci13xxx_stop(struct usb_gadget *gadget,
  2153. struct usb_gadget_driver *driver);
  2154. /**
  2155. * Device operations part of the API to the USB controller hardware,
  2156. * which don't involve endpoints (or i/o)
  2157. * Check "usb_gadget.h" for details
  2158. */
  2159. static const struct usb_gadget_ops usb_gadget_ops = {
  2160. .vbus_session = ci13xxx_vbus_session,
  2161. .wakeup = ci13xxx_wakeup,
  2162. .vbus_draw = ci13xxx_vbus_draw,
  2163. .udc_start = ci13xxx_start,
  2164. .udc_stop = ci13xxx_stop,
  2165. };
  2166. static int init_eps(struct ci13xxx *udc)
  2167. {
  2168. int retval = 0, i, j;
  2169. for (i = 0; i < udc->hw_ep_max/2; i++)
  2170. for (j = RX; j <= TX; j++) {
  2171. int k = i + j * udc->hw_ep_max/2;
  2172. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[k];
  2173. scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
  2174. (j == TX) ? "in" : "out");
  2175. mEp->udc = udc;
  2176. mEp->lock = &udc->lock;
  2177. mEp->device = &udc->gadget.dev;
  2178. mEp->td_pool = udc->td_pool;
  2179. mEp->ep.name = mEp->name;
  2180. mEp->ep.ops = &usb_ep_ops;
  2181. mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
  2182. INIT_LIST_HEAD(&mEp->qh.queue);
  2183. mEp->qh.ptr = dma_pool_alloc(udc->qh_pool, GFP_KERNEL,
  2184. &mEp->qh.dma);
  2185. if (mEp->qh.ptr == NULL)
  2186. retval = -ENOMEM;
  2187. else
  2188. memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
  2189. /*
  2190. * set up shorthands for ep0 out and in endpoints,
  2191. * don't add to gadget's ep_list
  2192. */
  2193. if (i == 0) {
  2194. if (j == RX)
  2195. udc->ep0out = mEp;
  2196. else
  2197. udc->ep0in = mEp;
  2198. continue;
  2199. }
  2200. list_add_tail(&mEp->ep.ep_list, &udc->gadget.ep_list);
  2201. }
  2202. return retval;
  2203. }
  2204. /**
  2205. * ci13xxx_start: register a gadget driver
  2206. * @gadget: our gadget
  2207. * @driver: the driver being registered
  2208. *
  2209. * Interrupts are enabled here.
  2210. */
  2211. static int ci13xxx_start(struct usb_gadget *gadget,
  2212. struct usb_gadget_driver *driver)
  2213. {
  2214. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  2215. unsigned long flags;
  2216. int retval = -ENOMEM;
  2217. if (driver->disconnect == NULL)
  2218. return -EINVAL;
  2219. udc->ep0out->ep.desc = &ctrl_endpt_out_desc;
  2220. retval = usb_ep_enable(&udc->ep0out->ep);
  2221. if (retval)
  2222. return retval;
  2223. udc->ep0in->ep.desc = &ctrl_endpt_in_desc;
  2224. retval = usb_ep_enable(&udc->ep0in->ep);
  2225. if (retval)
  2226. return retval;
  2227. spin_lock_irqsave(&udc->lock, flags);
  2228. udc->driver = driver;
  2229. pm_runtime_get_sync(&udc->gadget.dev);
  2230. if (udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) {
  2231. if (udc->vbus_active) {
  2232. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED)
  2233. hw_device_reset(udc);
  2234. } else {
  2235. pm_runtime_put_sync(&udc->gadget.dev);
  2236. goto done;
  2237. }
  2238. }
  2239. retval = hw_device_state(udc, udc->ep0out->qh.dma);
  2240. if (retval)
  2241. pm_runtime_put_sync(&udc->gadget.dev);
  2242. done:
  2243. spin_unlock_irqrestore(&udc->lock, flags);
  2244. return retval;
  2245. }
  2246. /**
  2247. * ci13xxx_stop: unregister a gadget driver
  2248. */
  2249. static int ci13xxx_stop(struct usb_gadget *gadget,
  2250. struct usb_gadget_driver *driver)
  2251. {
  2252. struct ci13xxx *udc = container_of(gadget, struct ci13xxx, gadget);
  2253. unsigned long flags;
  2254. spin_lock_irqsave(&udc->lock, flags);
  2255. if (!(udc->udc_driver->flags & CI13XXX_PULLUP_ON_VBUS) ||
  2256. udc->vbus_active) {
  2257. hw_device_state(udc, 0);
  2258. if (udc->udc_driver->notify_event)
  2259. udc->udc_driver->notify_event(udc,
  2260. CI13XXX_CONTROLLER_STOPPED_EVENT);
  2261. udc->driver = NULL;
  2262. spin_unlock_irqrestore(&udc->lock, flags);
  2263. _gadget_stop_activity(&udc->gadget);
  2264. spin_lock_irqsave(&udc->lock, flags);
  2265. pm_runtime_put(&udc->gadget.dev);
  2266. }
  2267. spin_unlock_irqrestore(&udc->lock, flags);
  2268. return 0;
  2269. }
  2270. /******************************************************************************
  2271. * BUS block
  2272. *****************************************************************************/
  2273. /**
  2274. * udc_irq: global interrupt handler
  2275. *
  2276. * This function returns IRQ_HANDLED if the IRQ has been handled
  2277. * It locks access to registers
  2278. */
  2279. static irqreturn_t udc_irq(int irq, void *data)
  2280. {
  2281. struct ci13xxx *udc = data;
  2282. irqreturn_t retval;
  2283. u32 intr;
  2284. if (udc == NULL)
  2285. return IRQ_HANDLED;
  2286. spin_lock(&udc->lock);
  2287. if (udc->udc_driver->flags & CI13XXX_REGS_SHARED) {
  2288. if (hw_read(udc, OP_USBMODE, USBMODE_CM) !=
  2289. USBMODE_CM_DEVICE) {
  2290. spin_unlock(&udc->lock);
  2291. return IRQ_NONE;
  2292. }
  2293. }
  2294. intr = hw_test_and_clear_intr_active(udc);
  2295. if (intr) {
  2296. isr_statistics.hndl.buf[isr_statistics.hndl.idx++] = intr;
  2297. isr_statistics.hndl.idx &= ISR_MASK;
  2298. isr_statistics.hndl.cnt++;
  2299. /* order defines priority - do NOT change it */
  2300. if (USBi_URI & intr) {
  2301. isr_statistics.uri++;
  2302. isr_reset_handler(udc);
  2303. }
  2304. if (USBi_PCI & intr) {
  2305. isr_statistics.pci++;
  2306. udc->gadget.speed = hw_port_is_high_speed(udc) ?
  2307. USB_SPEED_HIGH : USB_SPEED_FULL;
  2308. if (udc->suspended && udc->driver->resume) {
  2309. spin_unlock(&udc->lock);
  2310. udc->driver->resume(&udc->gadget);
  2311. spin_lock(&udc->lock);
  2312. udc->suspended = 0;
  2313. }
  2314. }
  2315. if (USBi_UEI & intr)
  2316. isr_statistics.uei++;
  2317. if (USBi_UI & intr) {
  2318. isr_statistics.ui++;
  2319. isr_tr_complete_handler(udc);
  2320. }
  2321. if (USBi_SLI & intr) {
  2322. if (udc->gadget.speed != USB_SPEED_UNKNOWN &&
  2323. udc->driver->suspend) {
  2324. udc->suspended = 1;
  2325. spin_unlock(&udc->lock);
  2326. udc->driver->suspend(&udc->gadget);
  2327. spin_lock(&udc->lock);
  2328. }
  2329. isr_statistics.sli++;
  2330. }
  2331. retval = IRQ_HANDLED;
  2332. } else {
  2333. isr_statistics.none++;
  2334. retval = IRQ_NONE;
  2335. }
  2336. spin_unlock(&udc->lock);
  2337. return retval;
  2338. }
  2339. /**
  2340. * udc_release: driver release function
  2341. * @dev: device
  2342. *
  2343. * Currently does nothing
  2344. */
  2345. static void udc_release(struct device *dev)
  2346. {
  2347. }
  2348. /**
  2349. * udc_probe: parent probe must call this to initialize UDC
  2350. * @dev: parent device
  2351. * @regs: registers base address
  2352. * @name: driver name
  2353. *
  2354. * This function returns an error code
  2355. * No interrupts active, the IRQ has not been requested yet
  2356. * Kernel assumes 32-bit DMA operations by default, no need to dma_set_mask
  2357. */
  2358. static int udc_probe(struct ci13xxx_udc_driver *driver, struct device *dev,
  2359. void __iomem *regs, struct ci13xxx **_udc)
  2360. {
  2361. struct ci13xxx *udc;
  2362. int retval = 0;
  2363. if (dev == NULL || regs == NULL || driver == NULL ||
  2364. driver->name == NULL)
  2365. return -EINVAL;
  2366. udc = kzalloc(sizeof(struct ci13xxx), GFP_KERNEL);
  2367. if (udc == NULL)
  2368. return -ENOMEM;
  2369. spin_lock_init(&udc->lock);
  2370. udc->regs = regs;
  2371. udc->udc_driver = driver;
  2372. udc->gadget.ops = &usb_gadget_ops;
  2373. udc->gadget.speed = USB_SPEED_UNKNOWN;
  2374. udc->gadget.max_speed = USB_SPEED_HIGH;
  2375. udc->gadget.is_otg = 0;
  2376. udc->gadget.name = driver->name;
  2377. INIT_LIST_HEAD(&udc->gadget.ep_list);
  2378. dev_set_name(&udc->gadget.dev, "gadget");
  2379. udc->gadget.dev.dma_mask = dev->dma_mask;
  2380. udc->gadget.dev.coherent_dma_mask = dev->coherent_dma_mask;
  2381. udc->gadget.dev.parent = dev;
  2382. udc->gadget.dev.release = udc_release;
  2383. udc->dev = dev;
  2384. /* alloc resources */
  2385. udc->qh_pool = dma_pool_create("ci13xxx_qh", dev,
  2386. sizeof(struct ci13xxx_qh),
  2387. 64, CI13XXX_PAGE_SIZE);
  2388. if (udc->qh_pool == NULL) {
  2389. retval = -ENOMEM;
  2390. goto free_udc;
  2391. }
  2392. udc->td_pool = dma_pool_create("ci13xxx_td", dev,
  2393. sizeof(struct ci13xxx_td),
  2394. 64, CI13XXX_PAGE_SIZE);
  2395. if (udc->td_pool == NULL) {
  2396. retval = -ENOMEM;
  2397. goto free_qh_pool;
  2398. }
  2399. retval = hw_device_init(udc, regs, driver->capoffset);
  2400. if (retval < 0)
  2401. goto free_pools;
  2402. retval = init_eps(udc);
  2403. if (retval)
  2404. goto free_pools;
  2405. udc->gadget.ep0 = &udc->ep0in->ep;
  2406. udc->transceiver = usb_get_transceiver();
  2407. if (udc->udc_driver->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
  2408. if (udc->transceiver == NULL) {
  2409. retval = -ENODEV;
  2410. goto free_pools;
  2411. }
  2412. }
  2413. if (!(udc->udc_driver->flags & CI13XXX_REGS_SHARED)) {
  2414. retval = hw_device_reset(udc);
  2415. if (retval)
  2416. goto put_transceiver;
  2417. }
  2418. retval = device_register(&udc->gadget.dev);
  2419. if (retval) {
  2420. put_device(&udc->gadget.dev);
  2421. goto put_transceiver;
  2422. }
  2423. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2424. retval = dbg_create_files(&udc->gadget.dev);
  2425. #endif
  2426. if (retval)
  2427. goto unreg_device;
  2428. if (udc->transceiver) {
  2429. retval = otg_set_peripheral(udc->transceiver->otg,
  2430. &udc->gadget);
  2431. if (retval)
  2432. goto remove_dbg;
  2433. }
  2434. retval = usb_add_gadget_udc(dev, &udc->gadget);
  2435. if (retval)
  2436. goto remove_trans;
  2437. pm_runtime_no_callbacks(&udc->gadget.dev);
  2438. pm_runtime_enable(&udc->gadget.dev);
  2439. *_udc = udc;
  2440. return retval;
  2441. remove_trans:
  2442. if (udc->transceiver) {
  2443. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  2444. usb_put_transceiver(udc->transceiver);
  2445. }
  2446. dev_err(dev, "error = %i\n", retval);
  2447. remove_dbg:
  2448. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2449. dbg_remove_files(&udc->gadget.dev);
  2450. #endif
  2451. unreg_device:
  2452. device_unregister(&udc->gadget.dev);
  2453. put_transceiver:
  2454. if (udc->transceiver)
  2455. usb_put_transceiver(udc->transceiver);
  2456. free_pools:
  2457. dma_pool_destroy(udc->td_pool);
  2458. free_qh_pool:
  2459. dma_pool_destroy(udc->qh_pool);
  2460. free_udc:
  2461. kfree(udc);
  2462. *_udc = NULL;
  2463. return retval;
  2464. }
  2465. /**
  2466. * udc_remove: parent remove must call this to remove UDC
  2467. *
  2468. * No interrupts active, the IRQ has been released
  2469. */
  2470. static void udc_remove(struct ci13xxx *udc)
  2471. {
  2472. int i;
  2473. if (udc == NULL)
  2474. return;
  2475. usb_del_gadget_udc(&udc->gadget);
  2476. for (i = 0; i < udc->hw_ep_max; i++) {
  2477. struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
  2478. dma_pool_free(udc->qh_pool, mEp->qh.ptr, mEp->qh.dma);
  2479. }
  2480. dma_pool_destroy(udc->td_pool);
  2481. dma_pool_destroy(udc->qh_pool);
  2482. if (udc->transceiver) {
  2483. otg_set_peripheral(udc->transceiver->otg, &udc->gadget);
  2484. usb_put_transceiver(udc->transceiver);
  2485. }
  2486. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2487. dbg_remove_files(&udc->gadget.dev);
  2488. #endif
  2489. device_unregister(&udc->gadget.dev);
  2490. kfree(udc->hw_bank.regmap);
  2491. kfree(udc);
  2492. }
  2493. static int __devinit ci_udc_probe(struct platform_device *pdev)
  2494. {
  2495. struct device *dev = &pdev->dev;
  2496. struct ci13xxx_udc_driver *driver = dev->platform_data;
  2497. struct ci13xxx *udc;
  2498. struct resource *res;
  2499. void __iomem *base;
  2500. int ret;
  2501. if (!driver) {
  2502. dev_err(dev, "platform data missing\n");
  2503. return -ENODEV;
  2504. }
  2505. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2506. if (!res) {
  2507. dev_err(dev, "missing resource\n");
  2508. return -ENODEV;
  2509. }
  2510. base = devm_request_and_ioremap(dev, res);
  2511. if (!res) {
  2512. dev_err(dev, "can't request and ioremap resource\n");
  2513. return -ENOMEM;
  2514. }
  2515. ret = udc_probe(driver, dev, base, &udc);
  2516. if (ret)
  2517. return ret;
  2518. udc->irq = platform_get_irq(pdev, 0);
  2519. if (udc->irq < 0) {
  2520. dev_err(dev, "missing IRQ\n");
  2521. ret = -ENODEV;
  2522. goto out;
  2523. }
  2524. platform_set_drvdata(pdev, udc);
  2525. ret = request_irq(udc->irq, udc_irq, IRQF_SHARED, driver->name, udc);
  2526. out:
  2527. if (ret)
  2528. udc_remove(udc);
  2529. return ret;
  2530. }
  2531. static int __devexit ci_udc_remove(struct platform_device *pdev)
  2532. {
  2533. struct ci13xxx *udc = platform_get_drvdata(pdev);
  2534. free_irq(udc->irq, udc);
  2535. udc_remove(udc);
  2536. return 0;
  2537. }
  2538. static struct platform_driver ci_udc_driver = {
  2539. .probe = ci_udc_probe,
  2540. .remove = __devexit_p(ci_udc_remove),
  2541. .driver = {
  2542. .name = "ci_udc",
  2543. },
  2544. };
  2545. module_platform_driver(ci_udc_driver);
  2546. MODULE_ALIAS("platform:ci_udc");
  2547. MODULE_ALIAS("platform:ci13xxx");
  2548. MODULE_LICENSE("GPL v2");
  2549. MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
  2550. MODULE_DESCRIPTION("ChipIdea UDC Driver");