iwl3945-base.c 237 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945.h"
  46. #include "iwl-helpers.h"
  47. #ifdef CONFIG_IWL3945_DEBUG
  48. u32 iwl3945_debug_level;
  49. #endif
  50. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  51. struct iwl3945_tx_queue *txq);
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /* module parameters */
  58. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  59. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  60. static int iwl3945_param_disable; /* def: 0 = enable radio */
  61. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  62. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  63. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  64. int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  65. /*
  66. * module name, copyright, version, etc.
  67. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  68. */
  69. #define DRV_DESCRIPTION \
  70. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  71. #ifdef CONFIG_IWL3945_DEBUG
  72. #define VD "d"
  73. #else
  74. #define VD
  75. #endif
  76. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  77. #define VS "s"
  78. #else
  79. #define VS
  80. #endif
  81. #define IWLWIFI_VERSION "1.2.26k" VD VS
  82. #define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
  83. #define DRV_VERSION IWLWIFI_VERSION
  84. /* Change firmware file name, using "-" and incrementing number,
  85. * *only* when uCode interface or architecture changes so that it
  86. * is not compatible with earlier drivers.
  87. * This number will also appear in << 8 position of 1st dword of uCode file */
  88. #define IWL3945_UCODE_API "-1"
  89. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  90. MODULE_VERSION(DRV_VERSION);
  91. MODULE_AUTHOR(DRV_COPYRIGHT);
  92. MODULE_LICENSE("GPL");
  93. static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
  94. {
  95. u16 fc = le16_to_cpu(hdr->frame_control);
  96. int hdr_len = ieee80211_get_hdrlen(fc);
  97. if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
  98. return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
  99. return NULL;
  100. }
  101. static const struct ieee80211_supported_band *iwl3945_get_band(
  102. struct iwl3945_priv *priv, enum ieee80211_band band)
  103. {
  104. return priv->hw->wiphy->bands[band];
  105. }
  106. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  107. {
  108. /* Single white space is for Linksys APs */
  109. if (essid_len == 1 && essid[0] == ' ')
  110. return 1;
  111. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  112. while (essid_len) {
  113. essid_len--;
  114. if (essid[essid_len] != '\0')
  115. return 0;
  116. }
  117. return 1;
  118. }
  119. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  120. {
  121. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  122. const char *s = essid;
  123. char *d = escaped;
  124. if (iwl3945_is_empty_essid(essid, essid_len)) {
  125. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  126. return escaped;
  127. }
  128. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  129. while (essid_len--) {
  130. if (*s == '\0') {
  131. *d++ = '\\';
  132. *d++ = '0';
  133. s++;
  134. } else
  135. *d++ = *s++;
  136. }
  137. *d = '\0';
  138. return escaped;
  139. }
  140. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  141. * DMA services
  142. *
  143. * Theory of operation
  144. *
  145. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  146. * of buffer descriptors, each of which points to one or more data buffers for
  147. * the device to read from or fill. Driver and device exchange status of each
  148. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  149. * entries in each circular buffer, to protect against confusing empty and full
  150. * queue states.
  151. *
  152. * The device reads or writes the data in the queues via the device's several
  153. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  154. *
  155. * For Tx queue, there are low mark and high mark limits. If, after queuing
  156. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  157. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  158. * Tx queue resumed.
  159. *
  160. * The 3945 operates with six queues: One receive queue, one transmit queue
  161. * (#4) for sending commands to the device firmware, and four transmit queues
  162. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  163. ***************************************************/
  164. static int iwl3945_queue_space(const struct iwl3945_queue *q)
  165. {
  166. int s = q->read_ptr - q->write_ptr;
  167. if (q->read_ptr > q->write_ptr)
  168. s -= q->n_bd;
  169. if (s <= 0)
  170. s += q->n_window;
  171. /* keep some reserve to not confuse empty and full situations */
  172. s -= 2;
  173. if (s < 0)
  174. s = 0;
  175. return s;
  176. }
  177. /**
  178. * iwl3945_queue_inc_wrap - increment queue index, wrap back to beginning
  179. * @index -- current index
  180. * @n_bd -- total number of entries in queue (must be power of 2)
  181. */
  182. static inline int iwl3945_queue_inc_wrap(int index, int n_bd)
  183. {
  184. return ++index & (n_bd - 1);
  185. }
  186. /**
  187. * iwl3945_queue_dec_wrap - increment queue index, wrap back to end
  188. * @index -- current index
  189. * @n_bd -- total number of entries in queue (must be power of 2)
  190. */
  191. static inline int iwl3945_queue_dec_wrap(int index, int n_bd)
  192. {
  193. return --index & (n_bd - 1);
  194. }
  195. static inline int x2_queue_used(const struct iwl3945_queue *q, int i)
  196. {
  197. return q->write_ptr > q->read_ptr ?
  198. (i >= q->read_ptr && i < q->write_ptr) :
  199. !(i < q->read_ptr && i >= q->write_ptr);
  200. }
  201. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  202. {
  203. /* This is for scan command, the big buffer at end of command array */
  204. if (is_huge)
  205. return q->n_window; /* must be power of 2 */
  206. /* Otherwise, use normal size buffers */
  207. return index & (q->n_window - 1);
  208. }
  209. /**
  210. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  211. */
  212. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  213. int count, int slots_num, u32 id)
  214. {
  215. q->n_bd = count;
  216. q->n_window = slots_num;
  217. q->id = id;
  218. /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap
  219. * and iwl3945_queue_dec_wrap are broken. */
  220. BUG_ON(!is_power_of_2(count));
  221. /* slots_num must be power-of-two size, otherwise
  222. * get_cmd_index is broken. */
  223. BUG_ON(!is_power_of_2(slots_num));
  224. q->low_mark = q->n_window / 4;
  225. if (q->low_mark < 4)
  226. q->low_mark = 4;
  227. q->high_mark = q->n_window / 8;
  228. if (q->high_mark < 2)
  229. q->high_mark = 2;
  230. q->write_ptr = q->read_ptr = 0;
  231. return 0;
  232. }
  233. /**
  234. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  235. */
  236. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  237. struct iwl3945_tx_queue *txq, u32 id)
  238. {
  239. struct pci_dev *dev = priv->pci_dev;
  240. /* Driver private data, only for Tx (not command) queues,
  241. * not shared with device. */
  242. if (id != IWL_CMD_QUEUE_NUM) {
  243. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  244. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  245. if (!txq->txb) {
  246. IWL_ERROR("kmalloc for auxiliary BD "
  247. "structures failed\n");
  248. goto error;
  249. }
  250. } else
  251. txq->txb = NULL;
  252. /* Circular buffer of transmit frame descriptors (TFDs),
  253. * shared with device */
  254. txq->bd = pci_alloc_consistent(dev,
  255. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  256. &txq->q.dma_addr);
  257. if (!txq->bd) {
  258. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  259. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  260. goto error;
  261. }
  262. txq->q.id = id;
  263. return 0;
  264. error:
  265. if (txq->txb) {
  266. kfree(txq->txb);
  267. txq->txb = NULL;
  268. }
  269. return -ENOMEM;
  270. }
  271. /**
  272. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  273. */
  274. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  275. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  276. {
  277. struct pci_dev *dev = priv->pci_dev;
  278. int len;
  279. int rc = 0;
  280. /*
  281. * Alloc buffer array for commands (Tx or other types of commands).
  282. * For the command queue (#4), allocate command space + one big
  283. * command for scan, since scan command is very huge; the system will
  284. * not have two scans at the same time, so only one is needed.
  285. * For data Tx queues (all other queues), no super-size command
  286. * space is needed.
  287. */
  288. len = sizeof(struct iwl3945_cmd) * slots_num;
  289. if (txq_id == IWL_CMD_QUEUE_NUM)
  290. len += IWL_MAX_SCAN_SIZE;
  291. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  292. if (!txq->cmd)
  293. return -ENOMEM;
  294. /* Alloc driver data array and TFD circular buffer */
  295. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  296. if (rc) {
  297. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  298. return -ENOMEM;
  299. }
  300. txq->need_update = 0;
  301. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  302. * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */
  303. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  304. /* Initialize queue high/low-water, head/tail indexes */
  305. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  306. /* Tell device where to find queue, enable DMA channel. */
  307. iwl3945_hw_tx_queue_init(priv, txq);
  308. return 0;
  309. }
  310. /**
  311. * iwl3945_tx_queue_free - Deallocate DMA queue.
  312. * @txq: Transmit queue to deallocate.
  313. *
  314. * Empty queue by removing and destroying all BD's.
  315. * Free all buffers.
  316. * 0-fill, but do not free "txq" descriptor structure.
  317. */
  318. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  319. {
  320. struct iwl3945_queue *q = &txq->q;
  321. struct pci_dev *dev = priv->pci_dev;
  322. int len;
  323. if (q->n_bd == 0)
  324. return;
  325. /* first, empty all BD's */
  326. for (; q->write_ptr != q->read_ptr;
  327. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd))
  328. iwl3945_hw_txq_free_tfd(priv, txq);
  329. len = sizeof(struct iwl3945_cmd) * q->n_window;
  330. if (q->id == IWL_CMD_QUEUE_NUM)
  331. len += IWL_MAX_SCAN_SIZE;
  332. /* De-alloc array of command/tx buffers */
  333. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  334. /* De-alloc circular buffer of TFDs */
  335. if (txq->q.n_bd)
  336. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  337. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  338. /* De-alloc array of per-TFD driver data */
  339. if (txq->txb) {
  340. kfree(txq->txb);
  341. txq->txb = NULL;
  342. }
  343. /* 0-fill queue descriptor structure */
  344. memset(txq, 0, sizeof(*txq));
  345. }
  346. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  347. /*************** STATION TABLE MANAGEMENT ****
  348. * mac80211 should be examined to determine if sta_info is duplicating
  349. * the functionality provided here
  350. */
  351. /**************************************************************/
  352. #if 0 /* temporary disable till we add real remove station */
  353. /**
  354. * iwl3945_remove_station - Remove driver's knowledge of station.
  355. *
  356. * NOTE: This does not remove station from device's station table.
  357. */
  358. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  359. {
  360. int index = IWL_INVALID_STATION;
  361. int i;
  362. unsigned long flags;
  363. spin_lock_irqsave(&priv->sta_lock, flags);
  364. if (is_ap)
  365. index = IWL_AP_ID;
  366. else if (is_broadcast_ether_addr(addr))
  367. index = priv->hw_setting.bcast_sta_id;
  368. else
  369. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  370. if (priv->stations[i].used &&
  371. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  372. addr)) {
  373. index = i;
  374. break;
  375. }
  376. if (unlikely(index == IWL_INVALID_STATION))
  377. goto out;
  378. if (priv->stations[index].used) {
  379. priv->stations[index].used = 0;
  380. priv->num_stations--;
  381. }
  382. BUG_ON(priv->num_stations < 0);
  383. out:
  384. spin_unlock_irqrestore(&priv->sta_lock, flags);
  385. return 0;
  386. }
  387. #endif
  388. /**
  389. * iwl3945_clear_stations_table - Clear the driver's station table
  390. *
  391. * NOTE: This does not clear or otherwise alter the device's station table.
  392. */
  393. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  394. {
  395. unsigned long flags;
  396. spin_lock_irqsave(&priv->sta_lock, flags);
  397. priv->num_stations = 0;
  398. memset(priv->stations, 0, sizeof(priv->stations));
  399. spin_unlock_irqrestore(&priv->sta_lock, flags);
  400. }
  401. /**
  402. * iwl3945_add_station - Add station to station tables in driver and device
  403. */
  404. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  405. {
  406. int i;
  407. int index = IWL_INVALID_STATION;
  408. struct iwl3945_station_entry *station;
  409. unsigned long flags_spin;
  410. DECLARE_MAC_BUF(mac);
  411. u8 rate;
  412. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  413. if (is_ap)
  414. index = IWL_AP_ID;
  415. else if (is_broadcast_ether_addr(addr))
  416. index = priv->hw_setting.bcast_sta_id;
  417. else
  418. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  419. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  420. addr)) {
  421. index = i;
  422. break;
  423. }
  424. if (!priv->stations[i].used &&
  425. index == IWL_INVALID_STATION)
  426. index = i;
  427. }
  428. /* These two conditions has the same outcome but keep them separate
  429. since they have different meaning */
  430. if (unlikely(index == IWL_INVALID_STATION)) {
  431. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  432. return index;
  433. }
  434. if (priv->stations[index].used &&
  435. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  436. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  437. return index;
  438. }
  439. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  440. station = &priv->stations[index];
  441. station->used = 1;
  442. priv->num_stations++;
  443. /* Set up the REPLY_ADD_STA command to send to device */
  444. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  445. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  446. station->sta.mode = 0;
  447. station->sta.sta.sta_id = index;
  448. station->sta.station_flags = 0;
  449. if (priv->band == IEEE80211_BAND_5GHZ)
  450. rate = IWL_RATE_6M_PLCP;
  451. else
  452. rate = IWL_RATE_1M_PLCP;
  453. /* Turn on both antennas for the station... */
  454. station->sta.rate_n_flags =
  455. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  456. station->current_rate.rate_n_flags =
  457. le16_to_cpu(station->sta.rate_n_flags);
  458. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  459. /* Add station to device's station table */
  460. iwl3945_send_add_station(priv, &station->sta, flags);
  461. return index;
  462. }
  463. /*************** DRIVER STATUS FUNCTIONS *****/
  464. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  465. {
  466. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  467. * set but EXIT_PENDING is not */
  468. return test_bit(STATUS_READY, &priv->status) &&
  469. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  470. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  471. }
  472. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  473. {
  474. return test_bit(STATUS_ALIVE, &priv->status);
  475. }
  476. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  477. {
  478. return test_bit(STATUS_INIT, &priv->status);
  479. }
  480. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  481. {
  482. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  483. test_bit(STATUS_RF_KILL_SW, &priv->status);
  484. }
  485. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  486. {
  487. if (iwl3945_is_rfkill(priv))
  488. return 0;
  489. return iwl3945_is_ready(priv);
  490. }
  491. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  492. #define IWL_CMD(x) case x : return #x
  493. static const char *get_cmd_string(u8 cmd)
  494. {
  495. switch (cmd) {
  496. IWL_CMD(REPLY_ALIVE);
  497. IWL_CMD(REPLY_ERROR);
  498. IWL_CMD(REPLY_RXON);
  499. IWL_CMD(REPLY_RXON_ASSOC);
  500. IWL_CMD(REPLY_QOS_PARAM);
  501. IWL_CMD(REPLY_RXON_TIMING);
  502. IWL_CMD(REPLY_ADD_STA);
  503. IWL_CMD(REPLY_REMOVE_STA);
  504. IWL_CMD(REPLY_REMOVE_ALL_STA);
  505. IWL_CMD(REPLY_3945_RX);
  506. IWL_CMD(REPLY_TX);
  507. IWL_CMD(REPLY_RATE_SCALE);
  508. IWL_CMD(REPLY_LEDS_CMD);
  509. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  510. IWL_CMD(RADAR_NOTIFICATION);
  511. IWL_CMD(REPLY_QUIET_CMD);
  512. IWL_CMD(REPLY_CHANNEL_SWITCH);
  513. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  514. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  515. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  516. IWL_CMD(POWER_TABLE_CMD);
  517. IWL_CMD(PM_SLEEP_NOTIFICATION);
  518. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  519. IWL_CMD(REPLY_SCAN_CMD);
  520. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  521. IWL_CMD(SCAN_START_NOTIFICATION);
  522. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  523. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  524. IWL_CMD(BEACON_NOTIFICATION);
  525. IWL_CMD(REPLY_TX_BEACON);
  526. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  527. IWL_CMD(QUIET_NOTIFICATION);
  528. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  529. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  530. IWL_CMD(REPLY_BT_CONFIG);
  531. IWL_CMD(REPLY_STATISTICS_CMD);
  532. IWL_CMD(STATISTICS_NOTIFICATION);
  533. IWL_CMD(REPLY_CARD_STATE_CMD);
  534. IWL_CMD(CARD_STATE_NOTIFICATION);
  535. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  536. default:
  537. return "UNKNOWN";
  538. }
  539. }
  540. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  541. /**
  542. * iwl3945_enqueue_hcmd - enqueue a uCode command
  543. * @priv: device private data point
  544. * @cmd: a point to the ucode command structure
  545. *
  546. * The function returns < 0 values to indicate the operation is
  547. * failed. On success, it turns the index (> 0) of command in the
  548. * command queue.
  549. */
  550. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  551. {
  552. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  553. struct iwl3945_queue *q = &txq->q;
  554. struct iwl3945_tfd_frame *tfd;
  555. u32 *control_flags;
  556. struct iwl3945_cmd *out_cmd;
  557. u32 idx;
  558. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  559. dma_addr_t phys_addr;
  560. int pad;
  561. u16 count;
  562. int ret;
  563. unsigned long flags;
  564. /* If any of the command structures end up being larger than
  565. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  566. * we will need to increase the size of the TFD entries */
  567. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  568. !(cmd->meta.flags & CMD_SIZE_HUGE));
  569. if (iwl3945_is_rfkill(priv)) {
  570. IWL_DEBUG_INFO("Not sending command - RF KILL");
  571. return -EIO;
  572. }
  573. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  574. IWL_ERROR("No space for Tx\n");
  575. return -ENOSPC;
  576. }
  577. spin_lock_irqsave(&priv->hcmd_lock, flags);
  578. tfd = &txq->bd[q->write_ptr];
  579. memset(tfd, 0, sizeof(*tfd));
  580. control_flags = (u32 *) tfd;
  581. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  582. out_cmd = &txq->cmd[idx];
  583. out_cmd->hdr.cmd = cmd->id;
  584. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  585. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  586. /* At this point, the out_cmd now has all of the incoming cmd
  587. * information */
  588. out_cmd->hdr.flags = 0;
  589. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  590. INDEX_TO_SEQ(q->write_ptr));
  591. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  592. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  593. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  594. offsetof(struct iwl3945_cmd, hdr);
  595. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  596. pad = U32_PAD(cmd->len);
  597. count = TFD_CTL_COUNT_GET(*control_flags);
  598. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  599. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  600. "%d bytes at %d[%d]:%d\n",
  601. get_cmd_string(out_cmd->hdr.cmd),
  602. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  603. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  604. txq->need_update = 1;
  605. /* Increment and update queue's write index */
  606. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  607. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  608. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  609. return ret ? ret : idx;
  610. }
  611. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  612. {
  613. int ret;
  614. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  615. /* An asynchronous command can not expect an SKB to be set. */
  616. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  617. /* An asynchronous command MUST have a callback. */
  618. BUG_ON(!cmd->meta.u.callback);
  619. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  620. return -EBUSY;
  621. ret = iwl3945_enqueue_hcmd(priv, cmd);
  622. if (ret < 0) {
  623. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  624. get_cmd_string(cmd->id), ret);
  625. return ret;
  626. }
  627. return 0;
  628. }
  629. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  630. {
  631. int cmd_idx;
  632. int ret;
  633. static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
  634. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  635. /* A synchronous command can not have a callback set. */
  636. BUG_ON(cmd->meta.u.callback != NULL);
  637. if (atomic_xchg(&entry, 1)) {
  638. IWL_ERROR("Error sending %s: Already sending a host command\n",
  639. get_cmd_string(cmd->id));
  640. return -EBUSY;
  641. }
  642. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  643. if (cmd->meta.flags & CMD_WANT_SKB)
  644. cmd->meta.source = &cmd->meta;
  645. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  646. if (cmd_idx < 0) {
  647. ret = cmd_idx;
  648. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  649. get_cmd_string(cmd->id), ret);
  650. goto out;
  651. }
  652. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  653. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  654. HOST_COMPLETE_TIMEOUT);
  655. if (!ret) {
  656. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  657. IWL_ERROR("Error sending %s: time out after %dms.\n",
  658. get_cmd_string(cmd->id),
  659. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  660. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  661. ret = -ETIMEDOUT;
  662. goto cancel;
  663. }
  664. }
  665. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  666. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  667. get_cmd_string(cmd->id));
  668. ret = -ECANCELED;
  669. goto fail;
  670. }
  671. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  672. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  673. get_cmd_string(cmd->id));
  674. ret = -EIO;
  675. goto fail;
  676. }
  677. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  678. IWL_ERROR("Error: Response NULL in '%s'\n",
  679. get_cmd_string(cmd->id));
  680. ret = -EIO;
  681. goto out;
  682. }
  683. ret = 0;
  684. goto out;
  685. cancel:
  686. if (cmd->meta.flags & CMD_WANT_SKB) {
  687. struct iwl3945_cmd *qcmd;
  688. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  689. * TX cmd queue. Otherwise in case the cmd comes
  690. * in later, it will possibly set an invalid
  691. * address (cmd->meta.source). */
  692. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  693. qcmd->meta.flags &= ~CMD_WANT_SKB;
  694. }
  695. fail:
  696. if (cmd->meta.u.skb) {
  697. dev_kfree_skb_any(cmd->meta.u.skb);
  698. cmd->meta.u.skb = NULL;
  699. }
  700. out:
  701. atomic_set(&entry, 0);
  702. return ret;
  703. }
  704. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  705. {
  706. if (cmd->meta.flags & CMD_ASYNC)
  707. return iwl3945_send_cmd_async(priv, cmd);
  708. return iwl3945_send_cmd_sync(priv, cmd);
  709. }
  710. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  711. {
  712. struct iwl3945_host_cmd cmd = {
  713. .id = id,
  714. .len = len,
  715. .data = data,
  716. };
  717. return iwl3945_send_cmd_sync(priv, &cmd);
  718. }
  719. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  720. {
  721. struct iwl3945_host_cmd cmd = {
  722. .id = id,
  723. .len = sizeof(val),
  724. .data = &val,
  725. };
  726. return iwl3945_send_cmd_sync(priv, &cmd);
  727. }
  728. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  729. {
  730. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  731. }
  732. /**
  733. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  734. * @band: 2.4 or 5 GHz band
  735. * @channel: Any channel valid for the requested band
  736. * In addition to setting the staging RXON, priv->band is also set.
  737. *
  738. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  739. * in the staging RXON flag structure based on the band
  740. */
  741. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  742. enum ieee80211_band band,
  743. u16 channel)
  744. {
  745. if (!iwl3945_get_channel_info(priv, band, channel)) {
  746. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  747. channel, band);
  748. return -EINVAL;
  749. }
  750. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  751. (priv->band == band))
  752. return 0;
  753. priv->staging_rxon.channel = cpu_to_le16(channel);
  754. if (band == IEEE80211_BAND_5GHZ)
  755. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  756. else
  757. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  758. priv->band = band;
  759. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  760. return 0;
  761. }
  762. /**
  763. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  764. *
  765. * NOTE: This is really only useful during development and can eventually
  766. * be #ifdef'd out once the driver is stable and folks aren't actively
  767. * making changes
  768. */
  769. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  770. {
  771. int error = 0;
  772. int counter = 1;
  773. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  774. error |= le32_to_cpu(rxon->flags &
  775. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  776. RXON_FLG_RADAR_DETECT_MSK));
  777. if (error)
  778. IWL_WARNING("check 24G fields %d | %d\n",
  779. counter++, error);
  780. } else {
  781. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  782. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  783. if (error)
  784. IWL_WARNING("check 52 fields %d | %d\n",
  785. counter++, error);
  786. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  787. if (error)
  788. IWL_WARNING("check 52 CCK %d | %d\n",
  789. counter++, error);
  790. }
  791. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  792. if (error)
  793. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  794. /* make sure basic rates 6Mbps and 1Mbps are supported */
  795. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  796. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  797. if (error)
  798. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  799. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  800. if (error)
  801. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  802. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  803. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  804. if (error)
  805. IWL_WARNING("check CCK and short slot %d | %d\n",
  806. counter++, error);
  807. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  808. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  809. if (error)
  810. IWL_WARNING("check CCK & auto detect %d | %d\n",
  811. counter++, error);
  812. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  813. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  814. if (error)
  815. IWL_WARNING("check TGG and auto detect %d | %d\n",
  816. counter++, error);
  817. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  818. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  819. RXON_FLG_ANT_A_MSK)) == 0);
  820. if (error)
  821. IWL_WARNING("check antenna %d %d\n", counter++, error);
  822. if (error)
  823. IWL_WARNING("Tuning to channel %d\n",
  824. le16_to_cpu(rxon->channel));
  825. if (error) {
  826. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  827. return -1;
  828. }
  829. return 0;
  830. }
  831. /**
  832. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  833. * @priv: staging_rxon is compared to active_rxon
  834. *
  835. * If the RXON structure is changing enough to require a new tune,
  836. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  837. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  838. */
  839. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  840. {
  841. /* These items are only settable from the full RXON command */
  842. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  843. compare_ether_addr(priv->staging_rxon.bssid_addr,
  844. priv->active_rxon.bssid_addr) ||
  845. compare_ether_addr(priv->staging_rxon.node_addr,
  846. priv->active_rxon.node_addr) ||
  847. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  848. priv->active_rxon.wlap_bssid_addr) ||
  849. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  850. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  851. (priv->staging_rxon.air_propagation !=
  852. priv->active_rxon.air_propagation) ||
  853. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  854. return 1;
  855. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  856. * be updated with the RXON_ASSOC command -- however only some
  857. * flag transitions are allowed using RXON_ASSOC */
  858. /* Check if we are not switching bands */
  859. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  860. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  861. return 1;
  862. /* Check if we are switching association toggle */
  863. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  864. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  865. return 1;
  866. return 0;
  867. }
  868. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  869. {
  870. int rc = 0;
  871. struct iwl3945_rx_packet *res = NULL;
  872. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  873. struct iwl3945_host_cmd cmd = {
  874. .id = REPLY_RXON_ASSOC,
  875. .len = sizeof(rxon_assoc),
  876. .meta.flags = CMD_WANT_SKB,
  877. .data = &rxon_assoc,
  878. };
  879. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  880. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  881. if ((rxon1->flags == rxon2->flags) &&
  882. (rxon1->filter_flags == rxon2->filter_flags) &&
  883. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  884. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  885. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  886. return 0;
  887. }
  888. rxon_assoc.flags = priv->staging_rxon.flags;
  889. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  890. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  891. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  892. rxon_assoc.reserved = 0;
  893. rc = iwl3945_send_cmd_sync(priv, &cmd);
  894. if (rc)
  895. return rc;
  896. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  897. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  898. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  899. rc = -EIO;
  900. }
  901. priv->alloc_rxb_skb--;
  902. dev_kfree_skb_any(cmd.meta.u.skb);
  903. return rc;
  904. }
  905. /**
  906. * iwl3945_commit_rxon - commit staging_rxon to hardware
  907. *
  908. * The RXON command in staging_rxon is committed to the hardware and
  909. * the active_rxon structure is updated with the new data. This
  910. * function correctly transitions out of the RXON_ASSOC_MSK state if
  911. * a HW tune is required based on the RXON structure changes.
  912. */
  913. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  914. {
  915. /* cast away the const for active_rxon in this function */
  916. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  917. int rc = 0;
  918. DECLARE_MAC_BUF(mac);
  919. if (!iwl3945_is_alive(priv))
  920. return -1;
  921. /* always get timestamp with Rx frame */
  922. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  923. /* select antenna */
  924. priv->staging_rxon.flags &=
  925. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  926. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  927. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  928. if (rc) {
  929. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  930. return -EINVAL;
  931. }
  932. /* If we don't need to send a full RXON, we can use
  933. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  934. * and other flags for the current radio configuration. */
  935. if (!iwl3945_full_rxon_required(priv)) {
  936. rc = iwl3945_send_rxon_assoc(priv);
  937. if (rc) {
  938. IWL_ERROR("Error setting RXON_ASSOC "
  939. "configuration (%d).\n", rc);
  940. return rc;
  941. }
  942. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  943. return 0;
  944. }
  945. /* If we are currently associated and the new config requires
  946. * an RXON_ASSOC and the new config wants the associated mask enabled,
  947. * we must clear the associated from the active configuration
  948. * before we apply the new config */
  949. if (iwl3945_is_associated(priv) &&
  950. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  951. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  952. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  953. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  954. sizeof(struct iwl3945_rxon_cmd),
  955. &priv->active_rxon);
  956. /* If the mask clearing failed then we set
  957. * active_rxon back to what it was previously */
  958. if (rc) {
  959. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  960. IWL_ERROR("Error clearing ASSOC_MSK on current "
  961. "configuration (%d).\n", rc);
  962. return rc;
  963. }
  964. }
  965. IWL_DEBUG_INFO("Sending RXON\n"
  966. "* with%s RXON_FILTER_ASSOC_MSK\n"
  967. "* channel = %d\n"
  968. "* bssid = %s\n",
  969. ((priv->staging_rxon.filter_flags &
  970. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  971. le16_to_cpu(priv->staging_rxon.channel),
  972. print_mac(mac, priv->staging_rxon.bssid_addr));
  973. /* Apply the new configuration */
  974. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  975. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  976. if (rc) {
  977. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  978. return rc;
  979. }
  980. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  981. iwl3945_clear_stations_table(priv);
  982. /* If we issue a new RXON command which required a tune then we must
  983. * send a new TXPOWER command or we won't be able to Tx any frames */
  984. rc = iwl3945_hw_reg_send_txpower(priv);
  985. if (rc) {
  986. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  987. return rc;
  988. }
  989. /* Add the broadcast address so we can send broadcast frames */
  990. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  991. IWL_INVALID_STATION) {
  992. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  993. return -EIO;
  994. }
  995. /* If we have set the ASSOC_MSK and we are in BSS mode then
  996. * add the IWL_AP_ID to the station rate table */
  997. if (iwl3945_is_associated(priv) &&
  998. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  999. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  1000. == IWL_INVALID_STATION) {
  1001. IWL_ERROR("Error adding AP address for transmit.\n");
  1002. return -EIO;
  1003. }
  1004. /* Init the hardware's rate fallback order based on the band */
  1005. rc = iwl3945_init_hw_rate_table(priv);
  1006. if (rc) {
  1007. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  1008. return -EIO;
  1009. }
  1010. return 0;
  1011. }
  1012. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  1013. {
  1014. struct iwl3945_bt_cmd bt_cmd = {
  1015. .flags = 3,
  1016. .lead_time = 0xAA,
  1017. .max_kill = 1,
  1018. .kill_ack_mask = 0,
  1019. .kill_cts_mask = 0,
  1020. };
  1021. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1022. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  1023. }
  1024. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  1025. {
  1026. int rc = 0;
  1027. struct iwl3945_rx_packet *res;
  1028. struct iwl3945_host_cmd cmd = {
  1029. .id = REPLY_SCAN_ABORT_CMD,
  1030. .meta.flags = CMD_WANT_SKB,
  1031. };
  1032. /* If there isn't a scan actively going on in the hardware
  1033. * then we are in between scan bands and not actually
  1034. * actively scanning, so don't send the abort command */
  1035. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1036. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1037. return 0;
  1038. }
  1039. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1040. if (rc) {
  1041. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1042. return rc;
  1043. }
  1044. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1045. if (res->u.status != CAN_ABORT_STATUS) {
  1046. /* The scan abort will return 1 for success or
  1047. * 2 for "failure". A failure condition can be
  1048. * due to simply not being in an active scan which
  1049. * can occur if we send the scan abort before we
  1050. * the microcode has notified us that a scan is
  1051. * completed. */
  1052. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1053. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1054. clear_bit(STATUS_SCAN_HW, &priv->status);
  1055. }
  1056. dev_kfree_skb_any(cmd.meta.u.skb);
  1057. return rc;
  1058. }
  1059. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1060. struct iwl3945_cmd *cmd,
  1061. struct sk_buff *skb)
  1062. {
  1063. return 1;
  1064. }
  1065. /*
  1066. * CARD_STATE_CMD
  1067. *
  1068. * Use: Sets the device's internal card state to enable, disable, or halt
  1069. *
  1070. * When in the 'enable' state the card operates as normal.
  1071. * When in the 'disable' state, the card enters into a low power mode.
  1072. * When in the 'halt' state, the card is shut down and must be fully
  1073. * restarted to come back on.
  1074. */
  1075. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1076. {
  1077. struct iwl3945_host_cmd cmd = {
  1078. .id = REPLY_CARD_STATE_CMD,
  1079. .len = sizeof(u32),
  1080. .data = &flags,
  1081. .meta.flags = meta_flag,
  1082. };
  1083. if (meta_flag & CMD_ASYNC)
  1084. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1085. return iwl3945_send_cmd(priv, &cmd);
  1086. }
  1087. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1088. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1089. {
  1090. struct iwl3945_rx_packet *res = NULL;
  1091. if (!skb) {
  1092. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1093. return 1;
  1094. }
  1095. res = (struct iwl3945_rx_packet *)skb->data;
  1096. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1097. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1098. res->hdr.flags);
  1099. return 1;
  1100. }
  1101. switch (res->u.add_sta.status) {
  1102. case ADD_STA_SUCCESS_MSK:
  1103. break;
  1104. default:
  1105. break;
  1106. }
  1107. /* We didn't cache the SKB; let the caller free it */
  1108. return 1;
  1109. }
  1110. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1111. struct iwl3945_addsta_cmd *sta, u8 flags)
  1112. {
  1113. struct iwl3945_rx_packet *res = NULL;
  1114. int rc = 0;
  1115. struct iwl3945_host_cmd cmd = {
  1116. .id = REPLY_ADD_STA,
  1117. .len = sizeof(struct iwl3945_addsta_cmd),
  1118. .meta.flags = flags,
  1119. .data = sta,
  1120. };
  1121. if (flags & CMD_ASYNC)
  1122. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1123. else
  1124. cmd.meta.flags |= CMD_WANT_SKB;
  1125. rc = iwl3945_send_cmd(priv, &cmd);
  1126. if (rc || (flags & CMD_ASYNC))
  1127. return rc;
  1128. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1129. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1130. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1131. res->hdr.flags);
  1132. rc = -EIO;
  1133. }
  1134. if (rc == 0) {
  1135. switch (res->u.add_sta.status) {
  1136. case ADD_STA_SUCCESS_MSK:
  1137. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1138. break;
  1139. default:
  1140. rc = -EIO;
  1141. IWL_WARNING("REPLY_ADD_STA failed\n");
  1142. break;
  1143. }
  1144. }
  1145. priv->alloc_rxb_skb--;
  1146. dev_kfree_skb_any(cmd.meta.u.skb);
  1147. return rc;
  1148. }
  1149. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1150. struct ieee80211_key_conf *keyconf,
  1151. u8 sta_id)
  1152. {
  1153. unsigned long flags;
  1154. __le16 key_flags = 0;
  1155. switch (keyconf->alg) {
  1156. case ALG_CCMP:
  1157. key_flags |= STA_KEY_FLG_CCMP;
  1158. key_flags |= cpu_to_le16(
  1159. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1160. key_flags &= ~STA_KEY_FLG_INVALID;
  1161. break;
  1162. case ALG_TKIP:
  1163. case ALG_WEP:
  1164. default:
  1165. return -EINVAL;
  1166. }
  1167. spin_lock_irqsave(&priv->sta_lock, flags);
  1168. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1169. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1170. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1171. keyconf->keylen);
  1172. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1173. keyconf->keylen);
  1174. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1175. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1176. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1177. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1178. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1179. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1180. return 0;
  1181. }
  1182. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1183. {
  1184. unsigned long flags;
  1185. spin_lock_irqsave(&priv->sta_lock, flags);
  1186. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1187. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1188. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1189. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1190. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1191. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1192. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1193. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1194. return 0;
  1195. }
  1196. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1197. {
  1198. struct list_head *element;
  1199. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1200. priv->frames_count);
  1201. while (!list_empty(&priv->free_frames)) {
  1202. element = priv->free_frames.next;
  1203. list_del(element);
  1204. kfree(list_entry(element, struct iwl3945_frame, list));
  1205. priv->frames_count--;
  1206. }
  1207. if (priv->frames_count) {
  1208. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1209. priv->frames_count);
  1210. priv->frames_count = 0;
  1211. }
  1212. }
  1213. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1214. {
  1215. struct iwl3945_frame *frame;
  1216. struct list_head *element;
  1217. if (list_empty(&priv->free_frames)) {
  1218. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1219. if (!frame) {
  1220. IWL_ERROR("Could not allocate frame!\n");
  1221. return NULL;
  1222. }
  1223. priv->frames_count++;
  1224. return frame;
  1225. }
  1226. element = priv->free_frames.next;
  1227. list_del(element);
  1228. return list_entry(element, struct iwl3945_frame, list);
  1229. }
  1230. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1231. {
  1232. memset(frame, 0, sizeof(*frame));
  1233. list_add(&frame->list, &priv->free_frames);
  1234. }
  1235. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1236. struct ieee80211_hdr *hdr,
  1237. const u8 *dest, int left)
  1238. {
  1239. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1240. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1241. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1242. return 0;
  1243. if (priv->ibss_beacon->len > left)
  1244. return 0;
  1245. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1246. return priv->ibss_beacon->len;
  1247. }
  1248. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1249. {
  1250. u8 i;
  1251. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1252. i = iwl3945_rates[i].next_ieee) {
  1253. if (rate_mask & (1 << i))
  1254. return iwl3945_rates[i].plcp;
  1255. }
  1256. return IWL_RATE_INVALID;
  1257. }
  1258. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1259. {
  1260. struct iwl3945_frame *frame;
  1261. unsigned int frame_size;
  1262. int rc;
  1263. u8 rate;
  1264. frame = iwl3945_get_free_frame(priv);
  1265. if (!frame) {
  1266. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1267. "command.\n");
  1268. return -ENOMEM;
  1269. }
  1270. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1271. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1272. 0xFF0);
  1273. if (rate == IWL_INVALID_RATE)
  1274. rate = IWL_RATE_6M_PLCP;
  1275. } else {
  1276. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1277. if (rate == IWL_INVALID_RATE)
  1278. rate = IWL_RATE_1M_PLCP;
  1279. }
  1280. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1281. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1282. &frame->u.cmd[0]);
  1283. iwl3945_free_frame(priv, frame);
  1284. return rc;
  1285. }
  1286. /******************************************************************************
  1287. *
  1288. * EEPROM related functions
  1289. *
  1290. ******************************************************************************/
  1291. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1292. {
  1293. memcpy(mac, priv->eeprom.mac_address, 6);
  1294. }
  1295. /*
  1296. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1297. * embedded controller) as EEPROM reader; each read is a series of pulses
  1298. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1299. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1300. * simply claims ownership, which should be safe when this function is called
  1301. * (i.e. before loading uCode!).
  1302. */
  1303. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1304. {
  1305. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1306. return 0;
  1307. }
  1308. /**
  1309. * iwl3945_eeprom_init - read EEPROM contents
  1310. *
  1311. * Load the EEPROM contents from adapter into priv->eeprom
  1312. *
  1313. * NOTE: This routine uses the non-debug IO access functions.
  1314. */
  1315. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1316. {
  1317. u16 *e = (u16 *)&priv->eeprom;
  1318. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1319. u32 r;
  1320. int sz = sizeof(priv->eeprom);
  1321. int rc;
  1322. int i;
  1323. u16 addr;
  1324. /* The EEPROM structure has several padding buffers within it
  1325. * and when adding new EEPROM maps is subject to programmer errors
  1326. * which may be very difficult to identify without explicitly
  1327. * checking the resulting size of the eeprom map. */
  1328. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1329. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1330. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1331. return -ENOENT;
  1332. }
  1333. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1334. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1335. if (rc < 0) {
  1336. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1337. return -ENOENT;
  1338. }
  1339. /* eeprom is an array of 16bit values */
  1340. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1341. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1342. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1343. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1344. i += IWL_EEPROM_ACCESS_DELAY) {
  1345. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1346. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1347. break;
  1348. udelay(IWL_EEPROM_ACCESS_DELAY);
  1349. }
  1350. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1351. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1352. return -ETIMEDOUT;
  1353. }
  1354. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1355. }
  1356. return 0;
  1357. }
  1358. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1359. {
  1360. if (priv->hw_setting.shared_virt)
  1361. pci_free_consistent(priv->pci_dev,
  1362. sizeof(struct iwl3945_shared),
  1363. priv->hw_setting.shared_virt,
  1364. priv->hw_setting.shared_phys);
  1365. }
  1366. /**
  1367. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1368. *
  1369. * return : set the bit for each supported rate insert in ie
  1370. */
  1371. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1372. u16 basic_rate, int *left)
  1373. {
  1374. u16 ret_rates = 0, bit;
  1375. int i;
  1376. u8 *cnt = ie;
  1377. u8 *rates = ie + 1;
  1378. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1379. if (bit & supported_rate) {
  1380. ret_rates |= bit;
  1381. rates[*cnt] = iwl3945_rates[i].ieee |
  1382. ((bit & basic_rate) ? 0x80 : 0x00);
  1383. (*cnt)++;
  1384. (*left)--;
  1385. if ((*left <= 0) ||
  1386. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1387. break;
  1388. }
  1389. }
  1390. return ret_rates;
  1391. }
  1392. /**
  1393. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1394. */
  1395. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1396. struct ieee80211_mgmt *frame,
  1397. int left, int is_direct)
  1398. {
  1399. int len = 0;
  1400. u8 *pos = NULL;
  1401. u16 active_rates, ret_rates, cck_rates;
  1402. /* Make sure there is enough space for the probe request,
  1403. * two mandatory IEs and the data */
  1404. left -= 24;
  1405. if (left < 0)
  1406. return 0;
  1407. len += 24;
  1408. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1409. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1410. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1411. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1412. frame->seq_ctrl = 0;
  1413. /* fill in our indirect SSID IE */
  1414. /* ...next IE... */
  1415. left -= 2;
  1416. if (left < 0)
  1417. return 0;
  1418. len += 2;
  1419. pos = &(frame->u.probe_req.variable[0]);
  1420. *pos++ = WLAN_EID_SSID;
  1421. *pos++ = 0;
  1422. /* fill in our direct SSID IE... */
  1423. if (is_direct) {
  1424. /* ...next IE... */
  1425. left -= 2 + priv->essid_len;
  1426. if (left < 0)
  1427. return 0;
  1428. /* ... fill it in... */
  1429. *pos++ = WLAN_EID_SSID;
  1430. *pos++ = priv->essid_len;
  1431. memcpy(pos, priv->essid, priv->essid_len);
  1432. pos += priv->essid_len;
  1433. len += 2 + priv->essid_len;
  1434. }
  1435. /* fill in supported rate */
  1436. /* ...next IE... */
  1437. left -= 2;
  1438. if (left < 0)
  1439. return 0;
  1440. /* ... fill it in... */
  1441. *pos++ = WLAN_EID_SUPP_RATES;
  1442. *pos = 0;
  1443. priv->active_rate = priv->rates_mask;
  1444. active_rates = priv->active_rate;
  1445. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1446. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1447. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1448. priv->active_rate_basic, &left);
  1449. active_rates &= ~ret_rates;
  1450. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1451. priv->active_rate_basic, &left);
  1452. active_rates &= ~ret_rates;
  1453. len += 2 + *pos;
  1454. pos += (*pos) + 1;
  1455. if (active_rates == 0)
  1456. goto fill_end;
  1457. /* fill in supported extended rate */
  1458. /* ...next IE... */
  1459. left -= 2;
  1460. if (left < 0)
  1461. return 0;
  1462. /* ... fill it in... */
  1463. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1464. *pos = 0;
  1465. iwl3945_supported_rate_to_ie(pos, active_rates,
  1466. priv->active_rate_basic, &left);
  1467. if (*pos > 0)
  1468. len += 2 + *pos;
  1469. fill_end:
  1470. return (u16)len;
  1471. }
  1472. /*
  1473. * QoS support
  1474. */
  1475. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1476. struct iwl3945_qosparam_cmd *qos)
  1477. {
  1478. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1479. sizeof(struct iwl3945_qosparam_cmd), qos);
  1480. }
  1481. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1482. {
  1483. u16 cw_min = 15;
  1484. u16 cw_max = 1023;
  1485. u8 aifs = 2;
  1486. u8 is_legacy = 0;
  1487. unsigned long flags;
  1488. int i;
  1489. spin_lock_irqsave(&priv->lock, flags);
  1490. priv->qos_data.qos_active = 0;
  1491. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1492. if (priv->qos_data.qos_enable)
  1493. priv->qos_data.qos_active = 1;
  1494. if (!(priv->active_rate & 0xfff0)) {
  1495. cw_min = 31;
  1496. is_legacy = 1;
  1497. }
  1498. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1499. if (priv->qos_data.qos_enable)
  1500. priv->qos_data.qos_active = 1;
  1501. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1502. cw_min = 31;
  1503. is_legacy = 1;
  1504. }
  1505. if (priv->qos_data.qos_active)
  1506. aifs = 3;
  1507. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1508. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1509. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1510. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1511. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1512. if (priv->qos_data.qos_active) {
  1513. i = 1;
  1514. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1515. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1516. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1517. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1518. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1519. i = 2;
  1520. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1521. cpu_to_le16((cw_min + 1) / 2 - 1);
  1522. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1523. cpu_to_le16(cw_max);
  1524. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1525. if (is_legacy)
  1526. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1527. cpu_to_le16(6016);
  1528. else
  1529. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1530. cpu_to_le16(3008);
  1531. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1532. i = 3;
  1533. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1534. cpu_to_le16((cw_min + 1) / 4 - 1);
  1535. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1536. cpu_to_le16((cw_max + 1) / 2 - 1);
  1537. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1538. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1539. if (is_legacy)
  1540. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1541. cpu_to_le16(3264);
  1542. else
  1543. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1544. cpu_to_le16(1504);
  1545. } else {
  1546. for (i = 1; i < 4; i++) {
  1547. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1548. cpu_to_le16(cw_min);
  1549. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1550. cpu_to_le16(cw_max);
  1551. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1552. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1553. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1554. }
  1555. }
  1556. IWL_DEBUG_QOS("set QoS to default \n");
  1557. spin_unlock_irqrestore(&priv->lock, flags);
  1558. }
  1559. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1560. {
  1561. unsigned long flags;
  1562. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1563. return;
  1564. if (!priv->qos_data.qos_enable)
  1565. return;
  1566. spin_lock_irqsave(&priv->lock, flags);
  1567. priv->qos_data.def_qos_parm.qos_flags = 0;
  1568. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1569. !priv->qos_data.qos_cap.q_AP.txop_request)
  1570. priv->qos_data.def_qos_parm.qos_flags |=
  1571. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1572. if (priv->qos_data.qos_active)
  1573. priv->qos_data.def_qos_parm.qos_flags |=
  1574. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1575. spin_unlock_irqrestore(&priv->lock, flags);
  1576. if (force || iwl3945_is_associated(priv)) {
  1577. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1578. priv->qos_data.qos_active);
  1579. iwl3945_send_qos_params_command(priv,
  1580. &(priv->qos_data.def_qos_parm));
  1581. }
  1582. }
  1583. /*
  1584. * Power management (not Tx power!) functions
  1585. */
  1586. #define MSEC_TO_USEC 1024
  1587. #define NOSLP __constant_cpu_to_le32(0)
  1588. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1589. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1590. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1591. __constant_cpu_to_le32(X1), \
  1592. __constant_cpu_to_le32(X2), \
  1593. __constant_cpu_to_le32(X3), \
  1594. __constant_cpu_to_le32(X4)}
  1595. /* default power management (not Tx power) table values */
  1596. /* for tim 0-10 */
  1597. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1598. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1599. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1600. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1601. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1602. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1603. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1604. };
  1605. /* for tim > 10 */
  1606. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1607. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1608. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1609. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1610. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1611. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1612. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1613. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1614. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1615. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1616. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1617. };
  1618. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1619. {
  1620. int rc = 0, i;
  1621. struct iwl3945_power_mgr *pow_data;
  1622. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1623. u16 pci_pm;
  1624. IWL_DEBUG_POWER("Initialize power \n");
  1625. pow_data = &(priv->power_data);
  1626. memset(pow_data, 0, sizeof(*pow_data));
  1627. pow_data->active_index = IWL_POWER_RANGE_0;
  1628. pow_data->dtim_val = 0xffff;
  1629. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1630. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1631. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1632. if (rc != 0)
  1633. return 0;
  1634. else {
  1635. struct iwl3945_powertable_cmd *cmd;
  1636. IWL_DEBUG_POWER("adjust power command flags\n");
  1637. for (i = 0; i < IWL_POWER_AC; i++) {
  1638. cmd = &pow_data->pwr_range_0[i].cmd;
  1639. if (pci_pm & 0x1)
  1640. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1641. else
  1642. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1643. }
  1644. }
  1645. return rc;
  1646. }
  1647. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1648. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1649. {
  1650. int rc = 0, i;
  1651. u8 skip;
  1652. u32 max_sleep = 0;
  1653. struct iwl3945_power_vec_entry *range;
  1654. u8 period = 0;
  1655. struct iwl3945_power_mgr *pow_data;
  1656. if (mode > IWL_POWER_INDEX_5) {
  1657. IWL_DEBUG_POWER("Error invalid power mode \n");
  1658. return -1;
  1659. }
  1660. pow_data = &(priv->power_data);
  1661. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1662. range = &pow_data->pwr_range_0[0];
  1663. else
  1664. range = &pow_data->pwr_range_1[1];
  1665. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1666. #ifdef IWL_MAC80211_DISABLE
  1667. if (priv->assoc_network != NULL) {
  1668. unsigned long flags;
  1669. period = priv->assoc_network->tim.tim_period;
  1670. }
  1671. #endif /*IWL_MAC80211_DISABLE */
  1672. skip = range[mode].no_dtim;
  1673. if (period == 0) {
  1674. period = 1;
  1675. skip = 0;
  1676. }
  1677. if (skip == 0) {
  1678. max_sleep = period;
  1679. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1680. } else {
  1681. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1682. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1683. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1684. }
  1685. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1686. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1687. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1688. }
  1689. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1690. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1691. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1692. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1693. le32_to_cpu(cmd->sleep_interval[0]),
  1694. le32_to_cpu(cmd->sleep_interval[1]),
  1695. le32_to_cpu(cmd->sleep_interval[2]),
  1696. le32_to_cpu(cmd->sleep_interval[3]),
  1697. le32_to_cpu(cmd->sleep_interval[4]));
  1698. return rc;
  1699. }
  1700. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1701. {
  1702. u32 uninitialized_var(final_mode);
  1703. int rc;
  1704. struct iwl3945_powertable_cmd cmd;
  1705. /* If on battery, set to 3,
  1706. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1707. * else user level */
  1708. switch (mode) {
  1709. case IWL_POWER_BATTERY:
  1710. final_mode = IWL_POWER_INDEX_3;
  1711. break;
  1712. case IWL_POWER_AC:
  1713. final_mode = IWL_POWER_MODE_CAM;
  1714. break;
  1715. default:
  1716. final_mode = mode;
  1717. break;
  1718. }
  1719. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1720. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1721. if (final_mode == IWL_POWER_MODE_CAM)
  1722. clear_bit(STATUS_POWER_PMI, &priv->status);
  1723. else
  1724. set_bit(STATUS_POWER_PMI, &priv->status);
  1725. return rc;
  1726. }
  1727. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1728. {
  1729. /* Filter incoming packets to determine if they are targeted toward
  1730. * this network, discarding packets coming from ourselves */
  1731. switch (priv->iw_mode) {
  1732. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1733. /* packets from our adapter are dropped (echo) */
  1734. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1735. return 0;
  1736. /* {broad,multi}cast packets to our IBSS go through */
  1737. if (is_multicast_ether_addr(header->addr1))
  1738. return !compare_ether_addr(header->addr3, priv->bssid);
  1739. /* packets to our adapter go through */
  1740. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1741. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1742. /* packets from our adapter are dropped (echo) */
  1743. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1744. return 0;
  1745. /* {broad,multi}cast packets to our BSS go through */
  1746. if (is_multicast_ether_addr(header->addr1))
  1747. return !compare_ether_addr(header->addr2, priv->bssid);
  1748. /* packets to our adapter go through */
  1749. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1750. }
  1751. return 1;
  1752. }
  1753. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  1754. static const char *iwl3945_get_tx_fail_reason(u32 status)
  1755. {
  1756. switch (status & TX_STATUS_MSK) {
  1757. case TX_STATUS_SUCCESS:
  1758. return "SUCCESS";
  1759. TX_STATUS_ENTRY(SHORT_LIMIT);
  1760. TX_STATUS_ENTRY(LONG_LIMIT);
  1761. TX_STATUS_ENTRY(FIFO_UNDERRUN);
  1762. TX_STATUS_ENTRY(MGMNT_ABORT);
  1763. TX_STATUS_ENTRY(NEXT_FRAG);
  1764. TX_STATUS_ENTRY(LIFE_EXPIRE);
  1765. TX_STATUS_ENTRY(DEST_PS);
  1766. TX_STATUS_ENTRY(ABORTED);
  1767. TX_STATUS_ENTRY(BT_RETRY);
  1768. TX_STATUS_ENTRY(STA_INVALID);
  1769. TX_STATUS_ENTRY(FRAG_DROPPED);
  1770. TX_STATUS_ENTRY(TID_DISABLE);
  1771. TX_STATUS_ENTRY(FRAME_FLUSHED);
  1772. TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
  1773. TX_STATUS_ENTRY(TX_LOCKED);
  1774. TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
  1775. }
  1776. return "UNKNOWN";
  1777. }
  1778. /**
  1779. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1780. *
  1781. * NOTE: priv->mutex is not required before calling this function
  1782. */
  1783. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1784. {
  1785. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1786. clear_bit(STATUS_SCANNING, &priv->status);
  1787. return 0;
  1788. }
  1789. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1790. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1791. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1792. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1793. queue_work(priv->workqueue, &priv->abort_scan);
  1794. } else
  1795. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1796. return test_bit(STATUS_SCANNING, &priv->status);
  1797. }
  1798. return 0;
  1799. }
  1800. /**
  1801. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1802. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1803. *
  1804. * NOTE: priv->mutex must be held before calling this function
  1805. */
  1806. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1807. {
  1808. unsigned long now = jiffies;
  1809. int ret;
  1810. ret = iwl3945_scan_cancel(priv);
  1811. if (ret && ms) {
  1812. mutex_unlock(&priv->mutex);
  1813. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1814. test_bit(STATUS_SCANNING, &priv->status))
  1815. msleep(1);
  1816. mutex_lock(&priv->mutex);
  1817. return test_bit(STATUS_SCANNING, &priv->status);
  1818. }
  1819. return ret;
  1820. }
  1821. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1822. {
  1823. /* Reset ieee stats */
  1824. /* We don't reset the net_device_stats (ieee->stats) on
  1825. * re-association */
  1826. priv->last_seq_num = -1;
  1827. priv->last_frag_num = -1;
  1828. priv->last_packet_time = 0;
  1829. iwl3945_scan_cancel(priv);
  1830. }
  1831. #define MAX_UCODE_BEACON_INTERVAL 1024
  1832. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1833. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1834. {
  1835. u16 new_val = 0;
  1836. u16 beacon_factor = 0;
  1837. beacon_factor =
  1838. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1839. / MAX_UCODE_BEACON_INTERVAL;
  1840. new_val = beacon_val / beacon_factor;
  1841. return cpu_to_le16(new_val);
  1842. }
  1843. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1844. {
  1845. u64 interval_tm_unit;
  1846. u64 tsf, result;
  1847. unsigned long flags;
  1848. struct ieee80211_conf *conf = NULL;
  1849. u16 beacon_int = 0;
  1850. conf = ieee80211_get_hw_conf(priv->hw);
  1851. spin_lock_irqsave(&priv->lock, flags);
  1852. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1853. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1854. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1855. tsf = priv->timestamp1;
  1856. tsf = ((tsf << 32) | priv->timestamp0);
  1857. beacon_int = priv->beacon_int;
  1858. spin_unlock_irqrestore(&priv->lock, flags);
  1859. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  1860. if (beacon_int == 0) {
  1861. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1862. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1863. } else {
  1864. priv->rxon_timing.beacon_interval =
  1865. cpu_to_le16(beacon_int);
  1866. priv->rxon_timing.beacon_interval =
  1867. iwl3945_adjust_beacon_interval(
  1868. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1869. }
  1870. priv->rxon_timing.atim_window = 0;
  1871. } else {
  1872. priv->rxon_timing.beacon_interval =
  1873. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1874. /* TODO: we need to get atim_window from upper stack
  1875. * for now we set to 0 */
  1876. priv->rxon_timing.atim_window = 0;
  1877. }
  1878. interval_tm_unit =
  1879. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1880. result = do_div(tsf, interval_tm_unit);
  1881. priv->rxon_timing.beacon_init_val =
  1882. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1883. IWL_DEBUG_ASSOC
  1884. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1885. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1886. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1887. le16_to_cpu(priv->rxon_timing.atim_window));
  1888. }
  1889. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1890. {
  1891. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1892. IWL_ERROR("APs don't scan.\n");
  1893. return 0;
  1894. }
  1895. if (!iwl3945_is_ready_rf(priv)) {
  1896. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1897. return -EIO;
  1898. }
  1899. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1900. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1901. return -EAGAIN;
  1902. }
  1903. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1904. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1905. "Queuing.\n");
  1906. return -EAGAIN;
  1907. }
  1908. IWL_DEBUG_INFO("Starting scan...\n");
  1909. priv->scan_bands = 2;
  1910. set_bit(STATUS_SCANNING, &priv->status);
  1911. priv->scan_start = jiffies;
  1912. priv->scan_pass_start = priv->scan_start;
  1913. queue_work(priv->workqueue, &priv->request_scan);
  1914. return 0;
  1915. }
  1916. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1917. {
  1918. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1919. if (hw_decrypt)
  1920. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1921. else
  1922. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1923. return 0;
  1924. }
  1925. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1926. enum ieee80211_band band)
  1927. {
  1928. if (band == IEEE80211_BAND_5GHZ) {
  1929. priv->staging_rxon.flags &=
  1930. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1931. | RXON_FLG_CCK_MSK);
  1932. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1933. } else {
  1934. /* Copied from iwl3945_bg_post_associate() */
  1935. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1936. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1937. else
  1938. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1939. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  1940. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1941. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1942. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1943. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1944. }
  1945. }
  1946. /*
  1947. * initialize rxon structure with default values from eeprom
  1948. */
  1949. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  1950. {
  1951. const struct iwl3945_channel_info *ch_info;
  1952. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1953. switch (priv->iw_mode) {
  1954. case IEEE80211_IF_TYPE_AP:
  1955. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1956. break;
  1957. case IEEE80211_IF_TYPE_STA:
  1958. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1959. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1960. break;
  1961. case IEEE80211_IF_TYPE_IBSS:
  1962. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1963. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1964. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1965. RXON_FILTER_ACCEPT_GRP_MSK;
  1966. break;
  1967. case IEEE80211_IF_TYPE_MNTR:
  1968. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1969. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1970. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1971. break;
  1972. }
  1973. #if 0
  1974. /* TODO: Figure out when short_preamble would be set and cache from
  1975. * that */
  1976. if (!hw_to_local(priv->hw)->short_preamble)
  1977. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1978. else
  1979. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1980. #endif
  1981. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1982. le16_to_cpu(priv->staging_rxon.channel));
  1983. if (!ch_info)
  1984. ch_info = &priv->channel_info[0];
  1985. /*
  1986. * in some case A channels are all non IBSS
  1987. * in this case force B/G channel
  1988. */
  1989. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  1990. !(is_channel_ibss(ch_info)))
  1991. ch_info = &priv->channel_info[0];
  1992. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1993. if (is_channel_a_band(ch_info))
  1994. priv->band = IEEE80211_BAND_5GHZ;
  1995. else
  1996. priv->band = IEEE80211_BAND_2GHZ;
  1997. iwl3945_set_flags_for_phymode(priv, priv->band);
  1998. priv->staging_rxon.ofdm_basic_rates =
  1999. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2000. priv->staging_rxon.cck_basic_rates =
  2001. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2002. }
  2003. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  2004. {
  2005. if (mode == IEEE80211_IF_TYPE_IBSS) {
  2006. const struct iwl3945_channel_info *ch_info;
  2007. ch_info = iwl3945_get_channel_info(priv,
  2008. priv->band,
  2009. le16_to_cpu(priv->staging_rxon.channel));
  2010. if (!ch_info || !is_channel_ibss(ch_info)) {
  2011. IWL_ERROR("channel %d not IBSS channel\n",
  2012. le16_to_cpu(priv->staging_rxon.channel));
  2013. return -EINVAL;
  2014. }
  2015. }
  2016. priv->iw_mode = mode;
  2017. iwl3945_connection_init_rx_config(priv);
  2018. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2019. iwl3945_clear_stations_table(priv);
  2020. /* dont commit rxon if rf-kill is on*/
  2021. if (!iwl3945_is_ready_rf(priv))
  2022. return -EAGAIN;
  2023. cancel_delayed_work(&priv->scan_check);
  2024. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  2025. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  2026. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  2027. return -EAGAIN;
  2028. }
  2029. iwl3945_commit_rxon(priv);
  2030. return 0;
  2031. }
  2032. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  2033. struct ieee80211_tx_control *ctl,
  2034. struct iwl3945_cmd *cmd,
  2035. struct sk_buff *skb_frag,
  2036. int last_frag)
  2037. {
  2038. struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
  2039. switch (keyinfo->alg) {
  2040. case ALG_CCMP:
  2041. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  2042. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  2043. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  2044. break;
  2045. case ALG_TKIP:
  2046. #if 0
  2047. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2048. if (last_frag)
  2049. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2050. 8);
  2051. else
  2052. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2053. #endif
  2054. break;
  2055. case ALG_WEP:
  2056. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2057. (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2058. if (keyinfo->keylen == 13)
  2059. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2060. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2061. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2062. "with key %d\n", ctl->key_idx);
  2063. break;
  2064. default:
  2065. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2066. break;
  2067. }
  2068. }
  2069. /*
  2070. * handle build REPLY_TX command notification.
  2071. */
  2072. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2073. struct iwl3945_cmd *cmd,
  2074. struct ieee80211_tx_control *ctrl,
  2075. struct ieee80211_hdr *hdr,
  2076. int is_unicast, u8 std_id)
  2077. {
  2078. __le16 *qc;
  2079. u16 fc = le16_to_cpu(hdr->frame_control);
  2080. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2081. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2082. if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
  2083. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2084. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  2085. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2086. if (ieee80211_is_probe_response(fc) &&
  2087. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2088. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2089. } else {
  2090. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2091. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2092. }
  2093. cmd->cmd.tx.sta_id = std_id;
  2094. if (ieee80211_get_morefrag(hdr))
  2095. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2096. qc = ieee80211_get_qos_ctrl(hdr);
  2097. if (qc) {
  2098. cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
  2099. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2100. } else
  2101. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2102. if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
  2103. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2104. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2105. } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
  2106. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2107. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2108. }
  2109. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2110. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2111. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2112. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2113. if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
  2114. (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
  2115. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2116. else
  2117. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2118. } else
  2119. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2120. cmd->cmd.tx.driver_txop = 0;
  2121. cmd->cmd.tx.tx_flags = tx_flags;
  2122. cmd->cmd.tx.next_frame_len = 0;
  2123. }
  2124. /**
  2125. * iwl3945_get_sta_id - Find station's index within station table
  2126. */
  2127. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2128. {
  2129. int sta_id;
  2130. u16 fc = le16_to_cpu(hdr->frame_control);
  2131. /* If this frame is broadcast or management, use broadcast station id */
  2132. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2133. is_multicast_ether_addr(hdr->addr1))
  2134. return priv->hw_setting.bcast_sta_id;
  2135. switch (priv->iw_mode) {
  2136. /* If we are a client station in a BSS network, use the special
  2137. * AP station entry (that's the only station we communicate with) */
  2138. case IEEE80211_IF_TYPE_STA:
  2139. return IWL_AP_ID;
  2140. /* If we are an AP, then find the station, or use BCAST */
  2141. case IEEE80211_IF_TYPE_AP:
  2142. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2143. if (sta_id != IWL_INVALID_STATION)
  2144. return sta_id;
  2145. return priv->hw_setting.bcast_sta_id;
  2146. /* If this frame is going out to an IBSS network, find the station,
  2147. * or create a new station table entry */
  2148. case IEEE80211_IF_TYPE_IBSS: {
  2149. DECLARE_MAC_BUF(mac);
  2150. /* Create new station table entry */
  2151. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2152. if (sta_id != IWL_INVALID_STATION)
  2153. return sta_id;
  2154. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2155. if (sta_id != IWL_INVALID_STATION)
  2156. return sta_id;
  2157. IWL_DEBUG_DROP("Station %s not in station map. "
  2158. "Defaulting to broadcast...\n",
  2159. print_mac(mac, hdr->addr1));
  2160. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2161. return priv->hw_setting.bcast_sta_id;
  2162. }
  2163. default:
  2164. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2165. return priv->hw_setting.bcast_sta_id;
  2166. }
  2167. }
  2168. /*
  2169. * start REPLY_TX command process
  2170. */
  2171. static int iwl3945_tx_skb(struct iwl3945_priv *priv,
  2172. struct sk_buff *skb, struct ieee80211_tx_control *ctl)
  2173. {
  2174. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2175. struct iwl3945_tfd_frame *tfd;
  2176. u32 *control_flags;
  2177. int txq_id = ctl->queue;
  2178. struct iwl3945_tx_queue *txq = NULL;
  2179. struct iwl3945_queue *q = NULL;
  2180. dma_addr_t phys_addr;
  2181. dma_addr_t txcmd_phys;
  2182. struct iwl3945_cmd *out_cmd = NULL;
  2183. u16 len, idx, len_org;
  2184. u8 id, hdr_len, unicast;
  2185. u8 sta_id;
  2186. u16 seq_number = 0;
  2187. u16 fc;
  2188. __le16 *qc;
  2189. u8 wait_write_ptr = 0;
  2190. unsigned long flags;
  2191. int rc;
  2192. spin_lock_irqsave(&priv->lock, flags);
  2193. if (iwl3945_is_rfkill(priv)) {
  2194. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2195. goto drop_unlock;
  2196. }
  2197. if (!priv->vif) {
  2198. IWL_DEBUG_DROP("Dropping - !priv->vif\n");
  2199. goto drop_unlock;
  2200. }
  2201. if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2202. IWL_ERROR("ERROR: No TX rate available.\n");
  2203. goto drop_unlock;
  2204. }
  2205. unicast = !is_multicast_ether_addr(hdr->addr1);
  2206. id = 0;
  2207. fc = le16_to_cpu(hdr->frame_control);
  2208. #ifdef CONFIG_IWL3945_DEBUG
  2209. if (ieee80211_is_auth(fc))
  2210. IWL_DEBUG_TX("Sending AUTH frame\n");
  2211. else if (ieee80211_is_assoc_request(fc))
  2212. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2213. else if (ieee80211_is_reassoc_request(fc))
  2214. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2215. #endif
  2216. /* drop all data frame if we are not associated */
  2217. if ((!iwl3945_is_associated(priv) ||
  2218. ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
  2219. ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
  2220. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2221. goto drop_unlock;
  2222. }
  2223. spin_unlock_irqrestore(&priv->lock, flags);
  2224. hdr_len = ieee80211_get_hdrlen(fc);
  2225. /* Find (or create) index into station table for destination station */
  2226. sta_id = iwl3945_get_sta_id(priv, hdr);
  2227. if (sta_id == IWL_INVALID_STATION) {
  2228. DECLARE_MAC_BUF(mac);
  2229. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2230. print_mac(mac, hdr->addr1));
  2231. goto drop;
  2232. }
  2233. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2234. qc = ieee80211_get_qos_ctrl(hdr);
  2235. if (qc) {
  2236. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2237. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2238. IEEE80211_SCTL_SEQ;
  2239. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2240. (hdr->seq_ctrl &
  2241. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2242. seq_number += 0x10;
  2243. }
  2244. /* Descriptor for chosen Tx queue */
  2245. txq = &priv->txq[txq_id];
  2246. q = &txq->q;
  2247. spin_lock_irqsave(&priv->lock, flags);
  2248. /* Set up first empty TFD within this queue's circular TFD buffer */
  2249. tfd = &txq->bd[q->write_ptr];
  2250. memset(tfd, 0, sizeof(*tfd));
  2251. control_flags = (u32 *) tfd;
  2252. idx = get_cmd_index(q, q->write_ptr, 0);
  2253. /* Set up driver data for this TFD */
  2254. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2255. txq->txb[q->write_ptr].skb[0] = skb;
  2256. memcpy(&(txq->txb[q->write_ptr].status.control),
  2257. ctl, sizeof(struct ieee80211_tx_control));
  2258. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2259. out_cmd = &txq->cmd[idx];
  2260. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2261. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2262. /*
  2263. * Set up the Tx-command (not MAC!) header.
  2264. * Store the chosen Tx queue and TFD index within the sequence field;
  2265. * after Tx, uCode's Tx response will return this value so driver can
  2266. * locate the frame within the tx queue and do post-tx processing.
  2267. */
  2268. out_cmd->hdr.cmd = REPLY_TX;
  2269. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2270. INDEX_TO_SEQ(q->write_ptr)));
  2271. /* Copy MAC header from skb into command buffer */
  2272. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2273. /*
  2274. * Use the first empty entry in this queue's command buffer array
  2275. * to contain the Tx command and MAC header concatenated together
  2276. * (payload data will be in another buffer).
  2277. * Size of this varies, due to varying MAC header length.
  2278. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2279. * of the MAC header (device reads on dword boundaries).
  2280. * We'll tell device about this padding later.
  2281. */
  2282. len = priv->hw_setting.tx_cmd_len +
  2283. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2284. len_org = len;
  2285. len = (len + 3) & ~3;
  2286. if (len_org != len)
  2287. len_org = 1;
  2288. else
  2289. len_org = 0;
  2290. /* Physical address of this Tx command's header (not MAC header!),
  2291. * within command buffer array. */
  2292. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2293. offsetof(struct iwl3945_cmd, hdr);
  2294. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2295. * first entry */
  2296. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2297. if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
  2298. iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
  2299. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2300. * if any (802.11 null frames have no payload). */
  2301. len = skb->len - hdr_len;
  2302. if (len) {
  2303. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2304. len, PCI_DMA_TODEVICE);
  2305. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2306. }
  2307. if (!len)
  2308. /* If there is no payload, then we use only one Tx buffer */
  2309. *control_flags = TFD_CTL_COUNT_SET(1);
  2310. else
  2311. /* Else use 2 buffers.
  2312. * Tell 3945 about any padding after MAC header */
  2313. *control_flags = TFD_CTL_COUNT_SET(2) |
  2314. TFD_CTL_PAD_SET(U32_PAD(len));
  2315. /* Total # bytes to be transmitted */
  2316. len = (u16)skb->len;
  2317. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2318. /* TODO need this for burst mode later on */
  2319. iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
  2320. /* set is_hcca to 0; it probably will never be implemented */
  2321. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
  2322. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2323. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2324. if (!ieee80211_get_morefrag(hdr)) {
  2325. txq->need_update = 1;
  2326. if (qc) {
  2327. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2328. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2329. }
  2330. } else {
  2331. wait_write_ptr = 1;
  2332. txq->need_update = 0;
  2333. }
  2334. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2335. sizeof(out_cmd->cmd.tx));
  2336. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2337. ieee80211_get_hdrlen(fc));
  2338. /* Tell device the write index *just past* this latest filled TFD */
  2339. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  2340. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2341. spin_unlock_irqrestore(&priv->lock, flags);
  2342. if (rc)
  2343. return rc;
  2344. if ((iwl3945_queue_space(q) < q->high_mark)
  2345. && priv->mac80211_registered) {
  2346. if (wait_write_ptr) {
  2347. spin_lock_irqsave(&priv->lock, flags);
  2348. txq->need_update = 1;
  2349. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2350. spin_unlock_irqrestore(&priv->lock, flags);
  2351. }
  2352. ieee80211_stop_queue(priv->hw, ctl->queue);
  2353. }
  2354. return 0;
  2355. drop_unlock:
  2356. spin_unlock_irqrestore(&priv->lock, flags);
  2357. drop:
  2358. return -1;
  2359. }
  2360. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2361. {
  2362. const struct ieee80211_supported_band *sband = NULL;
  2363. struct ieee80211_rate *rate;
  2364. int i;
  2365. sband = iwl3945_get_band(priv, priv->band);
  2366. if (!sband) {
  2367. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2368. return;
  2369. }
  2370. priv->active_rate = 0;
  2371. priv->active_rate_basic = 0;
  2372. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2373. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2374. for (i = 0; i < sband->n_bitrates; i++) {
  2375. rate = &sband->bitrates[i];
  2376. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2377. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2378. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2379. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2380. priv->active_rate |= (1 << rate->hw_value);
  2381. }
  2382. }
  2383. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2384. priv->active_rate, priv->active_rate_basic);
  2385. /*
  2386. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2387. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2388. * OFDM
  2389. */
  2390. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2391. priv->staging_rxon.cck_basic_rates =
  2392. ((priv->active_rate_basic &
  2393. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2394. else
  2395. priv->staging_rxon.cck_basic_rates =
  2396. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2397. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2398. priv->staging_rxon.ofdm_basic_rates =
  2399. ((priv->active_rate_basic &
  2400. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2401. IWL_FIRST_OFDM_RATE) & 0xFF;
  2402. else
  2403. priv->staging_rxon.ofdm_basic_rates =
  2404. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2405. }
  2406. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2407. {
  2408. unsigned long flags;
  2409. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2410. return;
  2411. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2412. disable_radio ? "OFF" : "ON");
  2413. if (disable_radio) {
  2414. iwl3945_scan_cancel(priv);
  2415. /* FIXME: This is a workaround for AP */
  2416. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2417. spin_lock_irqsave(&priv->lock, flags);
  2418. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2419. CSR_UCODE_SW_BIT_RFKILL);
  2420. spin_unlock_irqrestore(&priv->lock, flags);
  2421. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2422. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2423. }
  2424. return;
  2425. }
  2426. spin_lock_irqsave(&priv->lock, flags);
  2427. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2428. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2429. spin_unlock_irqrestore(&priv->lock, flags);
  2430. /* wake up ucode */
  2431. msleep(10);
  2432. spin_lock_irqsave(&priv->lock, flags);
  2433. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2434. if (!iwl3945_grab_nic_access(priv))
  2435. iwl3945_release_nic_access(priv);
  2436. spin_unlock_irqrestore(&priv->lock, flags);
  2437. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2438. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2439. "disabled by HW switch\n");
  2440. return;
  2441. }
  2442. queue_work(priv->workqueue, &priv->restart);
  2443. return;
  2444. }
  2445. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2446. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2447. {
  2448. u16 fc =
  2449. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2450. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2451. return;
  2452. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2453. return;
  2454. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2455. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2456. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2457. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2458. RX_RES_STATUS_BAD_ICV_MIC)
  2459. stats->flag |= RX_FLAG_MMIC_ERROR;
  2460. case RX_RES_STATUS_SEC_TYPE_WEP:
  2461. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2462. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2463. RX_RES_STATUS_DECRYPT_OK) {
  2464. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2465. stats->flag |= RX_FLAG_DECRYPTED;
  2466. }
  2467. break;
  2468. default:
  2469. break;
  2470. }
  2471. }
  2472. #define IWL_PACKET_RETRY_TIME HZ
  2473. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2474. {
  2475. u16 sc = le16_to_cpu(header->seq_ctrl);
  2476. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2477. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2478. u16 *last_seq, *last_frag;
  2479. unsigned long *last_time;
  2480. switch (priv->iw_mode) {
  2481. case IEEE80211_IF_TYPE_IBSS:{
  2482. struct list_head *p;
  2483. struct iwl3945_ibss_seq *entry = NULL;
  2484. u8 *mac = header->addr2;
  2485. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2486. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2487. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2488. if (!compare_ether_addr(entry->mac, mac))
  2489. break;
  2490. }
  2491. if (p == &priv->ibss_mac_hash[index]) {
  2492. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2493. if (!entry) {
  2494. IWL_ERROR("Cannot malloc new mac entry\n");
  2495. return 0;
  2496. }
  2497. memcpy(entry->mac, mac, ETH_ALEN);
  2498. entry->seq_num = seq;
  2499. entry->frag_num = frag;
  2500. entry->packet_time = jiffies;
  2501. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2502. return 0;
  2503. }
  2504. last_seq = &entry->seq_num;
  2505. last_frag = &entry->frag_num;
  2506. last_time = &entry->packet_time;
  2507. break;
  2508. }
  2509. case IEEE80211_IF_TYPE_STA:
  2510. last_seq = &priv->last_seq_num;
  2511. last_frag = &priv->last_frag_num;
  2512. last_time = &priv->last_packet_time;
  2513. break;
  2514. default:
  2515. return 0;
  2516. }
  2517. if ((*last_seq == seq) &&
  2518. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2519. if (*last_frag == frag)
  2520. goto drop;
  2521. if (*last_frag + 1 != frag)
  2522. /* out-of-order fragment */
  2523. goto drop;
  2524. } else
  2525. *last_seq = seq;
  2526. *last_frag = frag;
  2527. *last_time = jiffies;
  2528. return 0;
  2529. drop:
  2530. return 1;
  2531. }
  2532. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2533. #include "iwl-spectrum.h"
  2534. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2535. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2536. #define TIME_UNIT 1024
  2537. /*
  2538. * extended beacon time format
  2539. * time in usec will be changed into a 32-bit value in 8:24 format
  2540. * the high 1 byte is the beacon counts
  2541. * the lower 3 bytes is the time in usec within one beacon interval
  2542. */
  2543. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2544. {
  2545. u32 quot;
  2546. u32 rem;
  2547. u32 interval = beacon_interval * 1024;
  2548. if (!interval || !usec)
  2549. return 0;
  2550. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2551. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2552. return (quot << 24) + rem;
  2553. }
  2554. /* base is usually what we get from ucode with each received frame,
  2555. * the same as HW timer counter counting down
  2556. */
  2557. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2558. {
  2559. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2560. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2561. u32 interval = beacon_interval * TIME_UNIT;
  2562. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2563. (addon & BEACON_TIME_MASK_HIGH);
  2564. if (base_low > addon_low)
  2565. res += base_low - addon_low;
  2566. else if (base_low < addon_low) {
  2567. res += interval + base_low - addon_low;
  2568. res += (1 << 24);
  2569. } else
  2570. res += (1 << 24);
  2571. return cpu_to_le32(res);
  2572. }
  2573. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2574. struct ieee80211_measurement_params *params,
  2575. u8 type)
  2576. {
  2577. struct iwl3945_spectrum_cmd spectrum;
  2578. struct iwl3945_rx_packet *res;
  2579. struct iwl3945_host_cmd cmd = {
  2580. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2581. .data = (void *)&spectrum,
  2582. .meta.flags = CMD_WANT_SKB,
  2583. };
  2584. u32 add_time = le64_to_cpu(params->start_time);
  2585. int rc;
  2586. int spectrum_resp_status;
  2587. int duration = le16_to_cpu(params->duration);
  2588. if (iwl3945_is_associated(priv))
  2589. add_time =
  2590. iwl3945_usecs_to_beacons(
  2591. le64_to_cpu(params->start_time) - priv->last_tsf,
  2592. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2593. memset(&spectrum, 0, sizeof(spectrum));
  2594. spectrum.channel_count = cpu_to_le16(1);
  2595. spectrum.flags =
  2596. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2597. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2598. cmd.len = sizeof(spectrum);
  2599. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2600. if (iwl3945_is_associated(priv))
  2601. spectrum.start_time =
  2602. iwl3945_add_beacon_time(priv->last_beacon_time,
  2603. add_time,
  2604. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2605. else
  2606. spectrum.start_time = 0;
  2607. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2608. spectrum.channels[0].channel = params->channel;
  2609. spectrum.channels[0].type = type;
  2610. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2611. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2612. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2613. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2614. if (rc)
  2615. return rc;
  2616. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2617. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2618. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2619. rc = -EIO;
  2620. }
  2621. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2622. switch (spectrum_resp_status) {
  2623. case 0: /* Command will be handled */
  2624. if (res->u.spectrum.id != 0xff) {
  2625. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2626. res->u.spectrum.id);
  2627. priv->measurement_status &= ~MEASUREMENT_READY;
  2628. }
  2629. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2630. rc = 0;
  2631. break;
  2632. case 1: /* Command will not be handled */
  2633. rc = -EAGAIN;
  2634. break;
  2635. }
  2636. dev_kfree_skb_any(cmd.meta.u.skb);
  2637. return rc;
  2638. }
  2639. #endif
  2640. static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
  2641. struct iwl3945_tx_info *tx_sta)
  2642. {
  2643. tx_sta->status.ack_signal = 0;
  2644. tx_sta->status.excessive_retries = 0;
  2645. tx_sta->status.queue_length = 0;
  2646. tx_sta->status.queue_number = 0;
  2647. if (in_interrupt())
  2648. ieee80211_tx_status_irqsafe(priv->hw,
  2649. tx_sta->skb[0], &(tx_sta->status));
  2650. else
  2651. ieee80211_tx_status(priv->hw,
  2652. tx_sta->skb[0], &(tx_sta->status));
  2653. tx_sta->skb[0] = NULL;
  2654. }
  2655. /**
  2656. * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
  2657. *
  2658. * When FW advances 'R' index, all entries between old and new 'R' index
  2659. * need to be reclaimed. As result, some free space forms. If there is
  2660. * enough free space (> low mark), wake the stack that feeds us.
  2661. */
  2662. static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
  2663. {
  2664. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2665. struct iwl3945_queue *q = &txq->q;
  2666. int nfreed = 0;
  2667. if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
  2668. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2669. "is out of range [0-%d] %d %d.\n", txq_id,
  2670. index, q->n_bd, q->write_ptr, q->read_ptr);
  2671. return 0;
  2672. }
  2673. for (index = iwl3945_queue_inc_wrap(index, q->n_bd);
  2674. q->read_ptr != index;
  2675. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2676. if (txq_id != IWL_CMD_QUEUE_NUM) {
  2677. iwl3945_txstatus_to_ieee(priv,
  2678. &(txq->txb[txq->q.read_ptr]));
  2679. iwl3945_hw_txq_free_tfd(priv, txq);
  2680. } else if (nfreed > 1) {
  2681. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2682. q->write_ptr, q->read_ptr);
  2683. queue_work(priv->workqueue, &priv->restart);
  2684. }
  2685. nfreed++;
  2686. }
  2687. if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
  2688. (txq_id != IWL_CMD_QUEUE_NUM) &&
  2689. priv->mac80211_registered)
  2690. ieee80211_wake_queue(priv->hw, txq_id);
  2691. return nfreed;
  2692. }
  2693. static int iwl3945_is_tx_success(u32 status)
  2694. {
  2695. return (status & 0xFF) == 0x1;
  2696. }
  2697. /******************************************************************************
  2698. *
  2699. * Generic RX handler implementations
  2700. *
  2701. ******************************************************************************/
  2702. /**
  2703. * iwl3945_rx_reply_tx - Handle Tx response
  2704. */
  2705. static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
  2706. struct iwl3945_rx_mem_buffer *rxb)
  2707. {
  2708. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2709. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2710. int txq_id = SEQ_TO_QUEUE(sequence);
  2711. int index = SEQ_TO_INDEX(sequence);
  2712. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2713. struct ieee80211_tx_status *tx_status;
  2714. struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  2715. u32 status = le32_to_cpu(tx_resp->status);
  2716. if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
  2717. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  2718. "is out of range [0-%d] %d %d\n", txq_id,
  2719. index, txq->q.n_bd, txq->q.write_ptr,
  2720. txq->q.read_ptr);
  2721. return;
  2722. }
  2723. tx_status = &(txq->txb[txq->q.read_ptr].status);
  2724. tx_status->retry_count = tx_resp->failure_frame;
  2725. tx_status->queue_number = status;
  2726. tx_status->queue_length = tx_resp->bt_kill_count;
  2727. tx_status->queue_length |= tx_resp->failure_rts;
  2728. tx_status->flags =
  2729. iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
  2730. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
  2731. txq_id, iwl3945_get_tx_fail_reason(status), status,
  2732. tx_resp->rate, tx_resp->failure_frame);
  2733. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  2734. if (index != -1)
  2735. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  2736. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  2737. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  2738. }
  2739. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2740. struct iwl3945_rx_mem_buffer *rxb)
  2741. {
  2742. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2743. struct iwl3945_alive_resp *palive;
  2744. struct delayed_work *pwork;
  2745. palive = &pkt->u.alive_frame;
  2746. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2747. "0x%01X 0x%01X\n",
  2748. palive->is_valid, palive->ver_type,
  2749. palive->ver_subtype);
  2750. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2751. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2752. memcpy(&priv->card_alive_init,
  2753. &pkt->u.alive_frame,
  2754. sizeof(struct iwl3945_init_alive_resp));
  2755. pwork = &priv->init_alive_start;
  2756. } else {
  2757. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2758. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2759. sizeof(struct iwl3945_alive_resp));
  2760. pwork = &priv->alive_start;
  2761. iwl3945_disable_events(priv);
  2762. }
  2763. /* We delay the ALIVE response by 5ms to
  2764. * give the HW RF Kill time to activate... */
  2765. if (palive->is_valid == UCODE_VALID_OK)
  2766. queue_delayed_work(priv->workqueue, pwork,
  2767. msecs_to_jiffies(5));
  2768. else
  2769. IWL_WARNING("uCode did not respond OK.\n");
  2770. }
  2771. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2772. struct iwl3945_rx_mem_buffer *rxb)
  2773. {
  2774. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2775. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2776. return;
  2777. }
  2778. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2779. struct iwl3945_rx_mem_buffer *rxb)
  2780. {
  2781. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2782. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2783. "seq 0x%04X ser 0x%08X\n",
  2784. le32_to_cpu(pkt->u.err_resp.error_type),
  2785. get_cmd_string(pkt->u.err_resp.cmd_id),
  2786. pkt->u.err_resp.cmd_id,
  2787. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2788. le32_to_cpu(pkt->u.err_resp.error_info));
  2789. }
  2790. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2791. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2792. {
  2793. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2794. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2795. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2796. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2797. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2798. rxon->channel = csa->channel;
  2799. priv->staging_rxon.channel = csa->channel;
  2800. }
  2801. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2802. struct iwl3945_rx_mem_buffer *rxb)
  2803. {
  2804. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2805. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2806. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2807. if (!report->state) {
  2808. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2809. "Spectrum Measure Notification: Start\n");
  2810. return;
  2811. }
  2812. memcpy(&priv->measure_report, report, sizeof(*report));
  2813. priv->measurement_status |= MEASUREMENT_READY;
  2814. #endif
  2815. }
  2816. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2817. struct iwl3945_rx_mem_buffer *rxb)
  2818. {
  2819. #ifdef CONFIG_IWL3945_DEBUG
  2820. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2821. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2822. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2823. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2824. #endif
  2825. }
  2826. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2827. struct iwl3945_rx_mem_buffer *rxb)
  2828. {
  2829. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2830. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2831. "notification for %s:\n",
  2832. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2833. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2834. }
  2835. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2836. {
  2837. struct iwl3945_priv *priv =
  2838. container_of(work, struct iwl3945_priv, beacon_update);
  2839. struct sk_buff *beacon;
  2840. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2841. beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
  2842. if (!beacon) {
  2843. IWL_ERROR("update beacon failed\n");
  2844. return;
  2845. }
  2846. mutex_lock(&priv->mutex);
  2847. /* new beacon skb is allocated every time; dispose previous.*/
  2848. if (priv->ibss_beacon)
  2849. dev_kfree_skb(priv->ibss_beacon);
  2850. priv->ibss_beacon = beacon;
  2851. mutex_unlock(&priv->mutex);
  2852. iwl3945_send_beacon_cmd(priv);
  2853. }
  2854. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2855. struct iwl3945_rx_mem_buffer *rxb)
  2856. {
  2857. #ifdef CONFIG_IWL3945_DEBUG
  2858. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2859. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2860. u8 rate = beacon->beacon_notify_hdr.rate;
  2861. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2862. "tsf %d %d rate %d\n",
  2863. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2864. beacon->beacon_notify_hdr.failure_frame,
  2865. le32_to_cpu(beacon->ibss_mgr_status),
  2866. le32_to_cpu(beacon->high_tsf),
  2867. le32_to_cpu(beacon->low_tsf), rate);
  2868. #endif
  2869. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  2870. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2871. queue_work(priv->workqueue, &priv->beacon_update);
  2872. }
  2873. /* Service response to REPLY_SCAN_CMD (0x80) */
  2874. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2875. struct iwl3945_rx_mem_buffer *rxb)
  2876. {
  2877. #ifdef CONFIG_IWL3945_DEBUG
  2878. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2879. struct iwl3945_scanreq_notification *notif =
  2880. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  2881. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2882. #endif
  2883. }
  2884. /* Service SCAN_START_NOTIFICATION (0x82) */
  2885. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2886. struct iwl3945_rx_mem_buffer *rxb)
  2887. {
  2888. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2889. struct iwl3945_scanstart_notification *notif =
  2890. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  2891. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2892. IWL_DEBUG_SCAN("Scan start: "
  2893. "%d [802.11%s] "
  2894. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2895. notif->channel,
  2896. notif->band ? "bg" : "a",
  2897. notif->tsf_high,
  2898. notif->tsf_low, notif->status, notif->beacon_timer);
  2899. }
  2900. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2901. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2902. struct iwl3945_rx_mem_buffer *rxb)
  2903. {
  2904. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2905. struct iwl3945_scanresults_notification *notif =
  2906. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  2907. IWL_DEBUG_SCAN("Scan ch.res: "
  2908. "%d [802.11%s] "
  2909. "(TSF: 0x%08X:%08X) - %d "
  2910. "elapsed=%lu usec (%dms since last)\n",
  2911. notif->channel,
  2912. notif->band ? "bg" : "a",
  2913. le32_to_cpu(notif->tsf_high),
  2914. le32_to_cpu(notif->tsf_low),
  2915. le32_to_cpu(notif->statistics[0]),
  2916. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2917. jiffies_to_msecs(elapsed_jiffies
  2918. (priv->last_scan_jiffies, jiffies)));
  2919. priv->last_scan_jiffies = jiffies;
  2920. priv->next_scan_jiffies = 0;
  2921. }
  2922. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2923. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2924. struct iwl3945_rx_mem_buffer *rxb)
  2925. {
  2926. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2927. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2928. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2929. scan_notif->scanned_channels,
  2930. scan_notif->tsf_low,
  2931. scan_notif->tsf_high, scan_notif->status);
  2932. /* The HW is no longer scanning */
  2933. clear_bit(STATUS_SCAN_HW, &priv->status);
  2934. /* The scan completion notification came in, so kill that timer... */
  2935. cancel_delayed_work(&priv->scan_check);
  2936. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2937. (priv->scan_bands == 2) ? "2.4" : "5.2",
  2938. jiffies_to_msecs(elapsed_jiffies
  2939. (priv->scan_pass_start, jiffies)));
  2940. /* Remove this scanned band from the list
  2941. * of pending bands to scan */
  2942. priv->scan_bands--;
  2943. /* If a request to abort was given, or the scan did not succeed
  2944. * then we reset the scan state machine and terminate,
  2945. * re-queuing another scan if one has been requested */
  2946. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2947. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2948. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2949. } else {
  2950. /* If there are more bands on this scan pass reschedule */
  2951. if (priv->scan_bands > 0)
  2952. goto reschedule;
  2953. }
  2954. priv->last_scan_jiffies = jiffies;
  2955. priv->next_scan_jiffies = 0;
  2956. IWL_DEBUG_INFO("Setting scan to off\n");
  2957. clear_bit(STATUS_SCANNING, &priv->status);
  2958. IWL_DEBUG_INFO("Scan took %dms\n",
  2959. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2960. queue_work(priv->workqueue, &priv->scan_completed);
  2961. return;
  2962. reschedule:
  2963. priv->scan_pass_start = jiffies;
  2964. queue_work(priv->workqueue, &priv->request_scan);
  2965. }
  2966. /* Handle notification from uCode that card's power state is changing
  2967. * due to software, hardware, or critical temperature RFKILL */
  2968. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2969. struct iwl3945_rx_mem_buffer *rxb)
  2970. {
  2971. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2972. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2973. unsigned long status = priv->status;
  2974. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2975. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2976. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2977. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2978. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2979. if (flags & HW_CARD_DISABLED)
  2980. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2981. else
  2982. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2983. if (flags & SW_CARD_DISABLED)
  2984. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2985. else
  2986. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2987. iwl3945_scan_cancel(priv);
  2988. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2989. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2990. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2991. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2992. queue_work(priv->workqueue, &priv->rf_kill);
  2993. else
  2994. wake_up_interruptible(&priv->wait_command_queue);
  2995. }
  2996. /**
  2997. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2998. *
  2999. * Setup the RX handlers for each of the reply types sent from the uCode
  3000. * to the host.
  3001. *
  3002. * This function chains into the hardware specific files for them to setup
  3003. * any hardware specific handlers as well.
  3004. */
  3005. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  3006. {
  3007. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  3008. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  3009. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  3010. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  3011. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  3012. iwl3945_rx_spectrum_measure_notif;
  3013. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  3014. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  3015. iwl3945_rx_pm_debug_statistics_notif;
  3016. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  3017. /*
  3018. * The same handler is used for both the REPLY to a discrete
  3019. * statistics request from the host as well as for the periodic
  3020. * statistics notifications (after received beacons) from the uCode.
  3021. */
  3022. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  3023. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  3024. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  3025. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  3026. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  3027. iwl3945_rx_scan_results_notif;
  3028. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  3029. iwl3945_rx_scan_complete_notif;
  3030. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  3031. priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
  3032. /* Set up hardware specific Rx handlers */
  3033. iwl3945_hw_rx_handler_setup(priv);
  3034. }
  3035. /**
  3036. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  3037. * @rxb: Rx buffer to reclaim
  3038. *
  3039. * If an Rx buffer has an async callback associated with it the callback
  3040. * will be executed. The attached skb (if present) will only be freed
  3041. * if the callback returns 1
  3042. */
  3043. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  3044. struct iwl3945_rx_mem_buffer *rxb)
  3045. {
  3046. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3047. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  3048. int txq_id = SEQ_TO_QUEUE(sequence);
  3049. int index = SEQ_TO_INDEX(sequence);
  3050. int huge = sequence & SEQ_HUGE_FRAME;
  3051. int cmd_index;
  3052. struct iwl3945_cmd *cmd;
  3053. /* If a Tx command is being handled and it isn't in the actual
  3054. * command queue then there a command routing bug has been introduced
  3055. * in the queue management code. */
  3056. if (txq_id != IWL_CMD_QUEUE_NUM)
  3057. IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
  3058. txq_id, pkt->hdr.cmd);
  3059. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  3060. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  3061. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  3062. /* Input error checking is done when commands are added to queue. */
  3063. if (cmd->meta.flags & CMD_WANT_SKB) {
  3064. cmd->meta.source->u.skb = rxb->skb;
  3065. rxb->skb = NULL;
  3066. } else if (cmd->meta.u.callback &&
  3067. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  3068. rxb->skb = NULL;
  3069. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  3070. if (!(cmd->meta.flags & CMD_ASYNC)) {
  3071. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3072. wake_up_interruptible(&priv->wait_command_queue);
  3073. }
  3074. }
  3075. /************************** RX-FUNCTIONS ****************************/
  3076. /*
  3077. * Rx theory of operation
  3078. *
  3079. * The host allocates 32 DMA target addresses and passes the host address
  3080. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  3081. * 0 to 31
  3082. *
  3083. * Rx Queue Indexes
  3084. * The host/firmware share two index registers for managing the Rx buffers.
  3085. *
  3086. * The READ index maps to the first position that the firmware may be writing
  3087. * to -- the driver can read up to (but not including) this position and get
  3088. * good data.
  3089. * The READ index is managed by the firmware once the card is enabled.
  3090. *
  3091. * The WRITE index maps to the last position the driver has read from -- the
  3092. * position preceding WRITE is the last slot the firmware can place a packet.
  3093. *
  3094. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  3095. * WRITE = READ.
  3096. *
  3097. * During initialization, the host sets up the READ queue position to the first
  3098. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  3099. *
  3100. * When the firmware places a packet in a buffer, it will advance the READ index
  3101. * and fire the RX interrupt. The driver can then query the READ index and
  3102. * process as many packets as possible, moving the WRITE index forward as it
  3103. * resets the Rx queue buffers with new memory.
  3104. *
  3105. * The management in the driver is as follows:
  3106. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  3107. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  3108. * to replenish the iwl->rxq->rx_free.
  3109. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  3110. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  3111. * 'processed' and 'read' driver indexes as well)
  3112. * + A received packet is processed and handed to the kernel network stack,
  3113. * detached from the iwl->rxq. The driver 'processed' index is updated.
  3114. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  3115. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3116. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3117. * were enough free buffers and RX_STALLED is set it is cleared.
  3118. *
  3119. *
  3120. * Driver sequence:
  3121. *
  3122. * iwl3945_rx_queue_alloc() Allocates rx_free
  3123. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3124. * iwl3945_rx_queue_restock
  3125. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3126. * queue, updates firmware pointers, and updates
  3127. * the WRITE index. If insufficient rx_free buffers
  3128. * are available, schedules iwl3945_rx_replenish
  3129. *
  3130. * -- enable interrupts --
  3131. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3132. * READ INDEX, detaching the SKB from the pool.
  3133. * Moves the packet buffer from queue to rx_used.
  3134. * Calls iwl3945_rx_queue_restock to refill any empty
  3135. * slots.
  3136. * ...
  3137. *
  3138. */
  3139. /**
  3140. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3141. */
  3142. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3143. {
  3144. int s = q->read - q->write;
  3145. if (s <= 0)
  3146. s += RX_QUEUE_SIZE;
  3147. /* keep some buffer to not confuse full and empty queue */
  3148. s -= 2;
  3149. if (s < 0)
  3150. s = 0;
  3151. return s;
  3152. }
  3153. /**
  3154. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3155. */
  3156. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3157. {
  3158. u32 reg = 0;
  3159. int rc = 0;
  3160. unsigned long flags;
  3161. spin_lock_irqsave(&q->lock, flags);
  3162. if (q->need_update == 0)
  3163. goto exit_unlock;
  3164. /* If power-saving is in use, make sure device is awake */
  3165. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3166. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3167. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3168. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3169. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3170. goto exit_unlock;
  3171. }
  3172. rc = iwl3945_grab_nic_access(priv);
  3173. if (rc)
  3174. goto exit_unlock;
  3175. /* Device expects a multiple of 8 */
  3176. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3177. q->write & ~0x7);
  3178. iwl3945_release_nic_access(priv);
  3179. /* Else device is assumed to be awake */
  3180. } else
  3181. /* Device expects a multiple of 8 */
  3182. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3183. q->need_update = 0;
  3184. exit_unlock:
  3185. spin_unlock_irqrestore(&q->lock, flags);
  3186. return rc;
  3187. }
  3188. /**
  3189. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3190. */
  3191. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3192. dma_addr_t dma_addr)
  3193. {
  3194. return cpu_to_le32((u32)dma_addr);
  3195. }
  3196. /**
  3197. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3198. *
  3199. * If there are slots in the RX queue that need to be restocked,
  3200. * and we have free pre-allocated buffers, fill the ranks as much
  3201. * as we can, pulling from rx_free.
  3202. *
  3203. * This moves the 'write' index forward to catch up with 'processed', and
  3204. * also updates the memory address in the firmware to reference the new
  3205. * target buffer.
  3206. */
  3207. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3208. {
  3209. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3210. struct list_head *element;
  3211. struct iwl3945_rx_mem_buffer *rxb;
  3212. unsigned long flags;
  3213. int write, rc;
  3214. spin_lock_irqsave(&rxq->lock, flags);
  3215. write = rxq->write & ~0x7;
  3216. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3217. /* Get next free Rx buffer, remove from free list */
  3218. element = rxq->rx_free.next;
  3219. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3220. list_del(element);
  3221. /* Point to Rx buffer via next RBD in circular buffer */
  3222. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3223. rxq->queue[rxq->write] = rxb;
  3224. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3225. rxq->free_count--;
  3226. }
  3227. spin_unlock_irqrestore(&rxq->lock, flags);
  3228. /* If the pre-allocated buffer pool is dropping low, schedule to
  3229. * refill it */
  3230. if (rxq->free_count <= RX_LOW_WATERMARK)
  3231. queue_work(priv->workqueue, &priv->rx_replenish);
  3232. /* If we've added more space for the firmware to place data, tell it.
  3233. * Increment device's write pointer in multiples of 8. */
  3234. if ((write != (rxq->write & ~0x7))
  3235. || (abs(rxq->write - rxq->read) > 7)) {
  3236. spin_lock_irqsave(&rxq->lock, flags);
  3237. rxq->need_update = 1;
  3238. spin_unlock_irqrestore(&rxq->lock, flags);
  3239. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3240. if (rc)
  3241. return rc;
  3242. }
  3243. return 0;
  3244. }
  3245. /**
  3246. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3247. *
  3248. * When moving to rx_free an SKB is allocated for the slot.
  3249. *
  3250. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3251. * This is called as a scheduled work item (except for during initialization)
  3252. */
  3253. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3254. {
  3255. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3256. struct list_head *element;
  3257. struct iwl3945_rx_mem_buffer *rxb;
  3258. unsigned long flags;
  3259. spin_lock_irqsave(&rxq->lock, flags);
  3260. while (!list_empty(&rxq->rx_used)) {
  3261. element = rxq->rx_used.next;
  3262. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3263. /* Alloc a new receive buffer */
  3264. rxb->skb =
  3265. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3266. if (!rxb->skb) {
  3267. if (net_ratelimit())
  3268. printk(KERN_CRIT DRV_NAME
  3269. ": Can not allocate SKB buffers\n");
  3270. /* We don't reschedule replenish work here -- we will
  3271. * call the restock method and if it still needs
  3272. * more buffers it will schedule replenish */
  3273. break;
  3274. }
  3275. /* If radiotap head is required, reserve some headroom here.
  3276. * The physical head count is a variable rx_stats->phy_count.
  3277. * We reserve 4 bytes here. Plus these extra bytes, the
  3278. * headroom of the physical head should be enough for the
  3279. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3280. */
  3281. skb_reserve(rxb->skb, 4);
  3282. priv->alloc_rxb_skb++;
  3283. list_del(element);
  3284. /* Get physical address of RB/SKB */
  3285. rxb->dma_addr =
  3286. pci_map_single(priv->pci_dev, rxb->skb->data,
  3287. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3288. list_add_tail(&rxb->list, &rxq->rx_free);
  3289. rxq->free_count++;
  3290. }
  3291. spin_unlock_irqrestore(&rxq->lock, flags);
  3292. }
  3293. /*
  3294. * this should be called while priv->lock is locked
  3295. */
  3296. static void __iwl3945_rx_replenish(void *data)
  3297. {
  3298. struct iwl3945_priv *priv = data;
  3299. iwl3945_rx_allocate(priv);
  3300. iwl3945_rx_queue_restock(priv);
  3301. }
  3302. void iwl3945_rx_replenish(void *data)
  3303. {
  3304. struct iwl3945_priv *priv = data;
  3305. unsigned long flags;
  3306. iwl3945_rx_allocate(priv);
  3307. spin_lock_irqsave(&priv->lock, flags);
  3308. iwl3945_rx_queue_restock(priv);
  3309. spin_unlock_irqrestore(&priv->lock, flags);
  3310. }
  3311. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3312. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3313. * This free routine walks the list of POOL entries and if SKB is set to
  3314. * non NULL it is unmapped and freed
  3315. */
  3316. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3317. {
  3318. int i;
  3319. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3320. if (rxq->pool[i].skb != NULL) {
  3321. pci_unmap_single(priv->pci_dev,
  3322. rxq->pool[i].dma_addr,
  3323. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3324. dev_kfree_skb(rxq->pool[i].skb);
  3325. }
  3326. }
  3327. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3328. rxq->dma_addr);
  3329. rxq->bd = NULL;
  3330. }
  3331. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3332. {
  3333. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3334. struct pci_dev *dev = priv->pci_dev;
  3335. int i;
  3336. spin_lock_init(&rxq->lock);
  3337. INIT_LIST_HEAD(&rxq->rx_free);
  3338. INIT_LIST_HEAD(&rxq->rx_used);
  3339. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3340. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3341. if (!rxq->bd)
  3342. return -ENOMEM;
  3343. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3344. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3345. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3346. /* Set us so that we have processed and used all buffers, but have
  3347. * not restocked the Rx queue with fresh buffers */
  3348. rxq->read = rxq->write = 0;
  3349. rxq->free_count = 0;
  3350. rxq->need_update = 0;
  3351. return 0;
  3352. }
  3353. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3354. {
  3355. unsigned long flags;
  3356. int i;
  3357. spin_lock_irqsave(&rxq->lock, flags);
  3358. INIT_LIST_HEAD(&rxq->rx_free);
  3359. INIT_LIST_HEAD(&rxq->rx_used);
  3360. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3361. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3362. /* In the reset function, these buffers may have been allocated
  3363. * to an SKB, so we need to unmap and free potential storage */
  3364. if (rxq->pool[i].skb != NULL) {
  3365. pci_unmap_single(priv->pci_dev,
  3366. rxq->pool[i].dma_addr,
  3367. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3368. priv->alloc_rxb_skb--;
  3369. dev_kfree_skb(rxq->pool[i].skb);
  3370. rxq->pool[i].skb = NULL;
  3371. }
  3372. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3373. }
  3374. /* Set us so that we have processed and used all buffers, but have
  3375. * not restocked the Rx queue with fresh buffers */
  3376. rxq->read = rxq->write = 0;
  3377. rxq->free_count = 0;
  3378. spin_unlock_irqrestore(&rxq->lock, flags);
  3379. }
  3380. /* Convert linear signal-to-noise ratio into dB */
  3381. static u8 ratio2dB[100] = {
  3382. /* 0 1 2 3 4 5 6 7 8 9 */
  3383. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3384. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3385. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3386. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3387. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3388. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3389. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3390. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3391. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3392. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3393. };
  3394. /* Calculates a relative dB value from a ratio of linear
  3395. * (i.e. not dB) signal levels.
  3396. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3397. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3398. {
  3399. /* 1000:1 or higher just report as 60 dB */
  3400. if (sig_ratio >= 1000)
  3401. return 60;
  3402. /* 100:1 or higher, divide by 10 and use table,
  3403. * add 20 dB to make up for divide by 10 */
  3404. if (sig_ratio >= 100)
  3405. return (20 + (int)ratio2dB[sig_ratio/10]);
  3406. /* We shouldn't see this */
  3407. if (sig_ratio < 1)
  3408. return 0;
  3409. /* Use table for ratios 1:1 - 99:1 */
  3410. return (int)ratio2dB[sig_ratio];
  3411. }
  3412. #define PERFECT_RSSI (-20) /* dBm */
  3413. #define WORST_RSSI (-95) /* dBm */
  3414. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3415. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3416. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3417. * about formulas used below. */
  3418. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3419. {
  3420. int sig_qual;
  3421. int degradation = PERFECT_RSSI - rssi_dbm;
  3422. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3423. * as indicator; formula is (signal dbm - noise dbm).
  3424. * SNR at or above 40 is a great signal (100%).
  3425. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3426. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3427. if (noise_dbm) {
  3428. if (rssi_dbm - noise_dbm >= 40)
  3429. return 100;
  3430. else if (rssi_dbm < noise_dbm)
  3431. return 0;
  3432. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3433. /* Else use just the signal level.
  3434. * This formula is a least squares fit of data points collected and
  3435. * compared with a reference system that had a percentage (%) display
  3436. * for signal quality. */
  3437. } else
  3438. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3439. (15 * RSSI_RANGE + 62 * degradation)) /
  3440. (RSSI_RANGE * RSSI_RANGE);
  3441. if (sig_qual > 100)
  3442. sig_qual = 100;
  3443. else if (sig_qual < 1)
  3444. sig_qual = 0;
  3445. return sig_qual;
  3446. }
  3447. /**
  3448. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3449. *
  3450. * Uses the priv->rx_handlers callback function array to invoke
  3451. * the appropriate handlers, including command responses,
  3452. * frame-received notifications, and other notifications.
  3453. */
  3454. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3455. {
  3456. struct iwl3945_rx_mem_buffer *rxb;
  3457. struct iwl3945_rx_packet *pkt;
  3458. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3459. u32 r, i;
  3460. int reclaim;
  3461. unsigned long flags;
  3462. u8 fill_rx = 0;
  3463. u32 count = 8;
  3464. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3465. * buffer that the driver may process (last buffer filled by ucode). */
  3466. r = iwl3945_hw_get_rx_read(priv);
  3467. i = rxq->read;
  3468. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3469. fill_rx = 1;
  3470. /* Rx interrupt, but nothing sent from uCode */
  3471. if (i == r)
  3472. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3473. while (i != r) {
  3474. rxb = rxq->queue[i];
  3475. /* If an RXB doesn't have a Rx queue slot associated with it,
  3476. * then a bug has been introduced in the queue refilling
  3477. * routines -- catch it here */
  3478. BUG_ON(rxb == NULL);
  3479. rxq->queue[i] = NULL;
  3480. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3481. IWL_RX_BUF_SIZE,
  3482. PCI_DMA_FROMDEVICE);
  3483. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3484. /* Reclaim a command buffer only if this packet is a response
  3485. * to a (driver-originated) command.
  3486. * If the packet (e.g. Rx frame) originated from uCode,
  3487. * there is no command buffer to reclaim.
  3488. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3489. * but apparently a few don't get set; catch them here. */
  3490. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3491. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3492. (pkt->hdr.cmd != REPLY_TX);
  3493. /* Based on type of command response or notification,
  3494. * handle those that need handling via function in
  3495. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3496. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3497. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3498. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3499. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3500. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3501. } else {
  3502. /* No handling needed */
  3503. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3504. "r %d i %d No handler needed for %s, 0x%02x\n",
  3505. r, i, get_cmd_string(pkt->hdr.cmd),
  3506. pkt->hdr.cmd);
  3507. }
  3508. if (reclaim) {
  3509. /* Invoke any callbacks, transfer the skb to caller, and
  3510. * fire off the (possibly) blocking iwl3945_send_cmd()
  3511. * as we reclaim the driver command queue */
  3512. if (rxb && rxb->skb)
  3513. iwl3945_tx_cmd_complete(priv, rxb);
  3514. else
  3515. IWL_WARNING("Claim null rxb?\n");
  3516. }
  3517. /* For now we just don't re-use anything. We can tweak this
  3518. * later to try and re-use notification packets and SKBs that
  3519. * fail to Rx correctly */
  3520. if (rxb->skb != NULL) {
  3521. priv->alloc_rxb_skb--;
  3522. dev_kfree_skb_any(rxb->skb);
  3523. rxb->skb = NULL;
  3524. }
  3525. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3526. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3527. spin_lock_irqsave(&rxq->lock, flags);
  3528. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3529. spin_unlock_irqrestore(&rxq->lock, flags);
  3530. i = (i + 1) & RX_QUEUE_MASK;
  3531. /* If there are a lot of unused frames,
  3532. * restock the Rx queue so ucode won't assert. */
  3533. if (fill_rx) {
  3534. count++;
  3535. if (count >= 8) {
  3536. priv->rxq.read = i;
  3537. __iwl3945_rx_replenish(priv);
  3538. count = 0;
  3539. }
  3540. }
  3541. }
  3542. /* Backtrack one entry */
  3543. priv->rxq.read = i;
  3544. iwl3945_rx_queue_restock(priv);
  3545. }
  3546. /**
  3547. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3548. */
  3549. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3550. struct iwl3945_tx_queue *txq)
  3551. {
  3552. u32 reg = 0;
  3553. int rc = 0;
  3554. int txq_id = txq->q.id;
  3555. if (txq->need_update == 0)
  3556. return rc;
  3557. /* if we're trying to save power */
  3558. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3559. /* wake up nic if it's powered down ...
  3560. * uCode will wake up, and interrupt us again, so next
  3561. * time we'll skip this part. */
  3562. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3563. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3564. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3565. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3566. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3567. return rc;
  3568. }
  3569. /* restore this queue's parameters in nic hardware. */
  3570. rc = iwl3945_grab_nic_access(priv);
  3571. if (rc)
  3572. return rc;
  3573. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3574. txq->q.write_ptr | (txq_id << 8));
  3575. iwl3945_release_nic_access(priv);
  3576. /* else not in power-save mode, uCode will never sleep when we're
  3577. * trying to tx (during RFKILL, we're not trying to tx). */
  3578. } else
  3579. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3580. txq->q.write_ptr | (txq_id << 8));
  3581. txq->need_update = 0;
  3582. return rc;
  3583. }
  3584. #ifdef CONFIG_IWL3945_DEBUG
  3585. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3586. {
  3587. DECLARE_MAC_BUF(mac);
  3588. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3589. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3590. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3591. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3592. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3593. le32_to_cpu(rxon->filter_flags));
  3594. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3595. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3596. rxon->ofdm_basic_rates);
  3597. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3598. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3599. print_mac(mac, rxon->node_addr));
  3600. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3601. print_mac(mac, rxon->bssid_addr));
  3602. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3603. }
  3604. #endif
  3605. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3606. {
  3607. IWL_DEBUG_ISR("Enabling interrupts\n");
  3608. set_bit(STATUS_INT_ENABLED, &priv->status);
  3609. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3610. }
  3611. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3612. {
  3613. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3614. /* disable interrupts from uCode/NIC to host */
  3615. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3616. /* acknowledge/clear/reset any interrupts still pending
  3617. * from uCode or flow handler (Rx/Tx DMA) */
  3618. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3619. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3620. IWL_DEBUG_ISR("Disabled interrupts\n");
  3621. }
  3622. static const char *desc_lookup(int i)
  3623. {
  3624. switch (i) {
  3625. case 1:
  3626. return "FAIL";
  3627. case 2:
  3628. return "BAD_PARAM";
  3629. case 3:
  3630. return "BAD_CHECKSUM";
  3631. case 4:
  3632. return "NMI_INTERRUPT";
  3633. case 5:
  3634. return "SYSASSERT";
  3635. case 6:
  3636. return "FATAL_ERROR";
  3637. }
  3638. return "UNKNOWN";
  3639. }
  3640. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3641. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3642. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3643. {
  3644. u32 i;
  3645. u32 desc, time, count, base, data1;
  3646. u32 blink1, blink2, ilink1, ilink2;
  3647. int rc;
  3648. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3649. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3650. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3651. return;
  3652. }
  3653. rc = iwl3945_grab_nic_access(priv);
  3654. if (rc) {
  3655. IWL_WARNING("Can not read from adapter at this time.\n");
  3656. return;
  3657. }
  3658. count = iwl3945_read_targ_mem(priv, base);
  3659. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3660. IWL_ERROR("Start IWL Error Log Dump:\n");
  3661. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3662. }
  3663. IWL_ERROR("Desc Time asrtPC blink2 "
  3664. "ilink1 nmiPC Line\n");
  3665. for (i = ERROR_START_OFFSET;
  3666. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3667. i += ERROR_ELEM_SIZE) {
  3668. desc = iwl3945_read_targ_mem(priv, base + i);
  3669. time =
  3670. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3671. blink1 =
  3672. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3673. blink2 =
  3674. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3675. ilink1 =
  3676. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3677. ilink2 =
  3678. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3679. data1 =
  3680. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3681. IWL_ERROR
  3682. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3683. desc_lookup(desc), desc, time, blink1, blink2,
  3684. ilink1, ilink2, data1);
  3685. }
  3686. iwl3945_release_nic_access(priv);
  3687. }
  3688. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3689. /**
  3690. * iwl3945_print_event_log - Dump error event log to syslog
  3691. *
  3692. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3693. */
  3694. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3695. u32 num_events, u32 mode)
  3696. {
  3697. u32 i;
  3698. u32 base; /* SRAM byte address of event log header */
  3699. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3700. u32 ptr; /* SRAM byte address of log data */
  3701. u32 ev, time, data; /* event log data */
  3702. if (num_events == 0)
  3703. return;
  3704. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3705. if (mode == 0)
  3706. event_size = 2 * sizeof(u32);
  3707. else
  3708. event_size = 3 * sizeof(u32);
  3709. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3710. /* "time" is actually "data" for mode 0 (no timestamp).
  3711. * place event id # at far right for easier visual parsing. */
  3712. for (i = 0; i < num_events; i++) {
  3713. ev = iwl3945_read_targ_mem(priv, ptr);
  3714. ptr += sizeof(u32);
  3715. time = iwl3945_read_targ_mem(priv, ptr);
  3716. ptr += sizeof(u32);
  3717. if (mode == 0)
  3718. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3719. else {
  3720. data = iwl3945_read_targ_mem(priv, ptr);
  3721. ptr += sizeof(u32);
  3722. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3723. }
  3724. }
  3725. }
  3726. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3727. {
  3728. int rc;
  3729. u32 base; /* SRAM byte address of event log header */
  3730. u32 capacity; /* event log capacity in # entries */
  3731. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3732. u32 num_wraps; /* # times uCode wrapped to top of log */
  3733. u32 next_entry; /* index of next entry to be written by uCode */
  3734. u32 size; /* # entries that we'll print */
  3735. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3736. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3737. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3738. return;
  3739. }
  3740. rc = iwl3945_grab_nic_access(priv);
  3741. if (rc) {
  3742. IWL_WARNING("Can not read from adapter at this time.\n");
  3743. return;
  3744. }
  3745. /* event log header */
  3746. capacity = iwl3945_read_targ_mem(priv, base);
  3747. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3748. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3749. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3750. size = num_wraps ? capacity : next_entry;
  3751. /* bail out if nothing in log */
  3752. if (size == 0) {
  3753. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3754. iwl3945_release_nic_access(priv);
  3755. return;
  3756. }
  3757. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3758. size, num_wraps);
  3759. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3760. * i.e the next one that uCode would fill. */
  3761. if (num_wraps)
  3762. iwl3945_print_event_log(priv, next_entry,
  3763. capacity - next_entry, mode);
  3764. /* (then/else) start at top of log */
  3765. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3766. iwl3945_release_nic_access(priv);
  3767. }
  3768. /**
  3769. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3770. */
  3771. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3772. {
  3773. /* Set the FW error flag -- cleared on iwl3945_down */
  3774. set_bit(STATUS_FW_ERROR, &priv->status);
  3775. /* Cancel currently queued command. */
  3776. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3777. #ifdef CONFIG_IWL3945_DEBUG
  3778. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3779. iwl3945_dump_nic_error_log(priv);
  3780. iwl3945_dump_nic_event_log(priv);
  3781. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3782. }
  3783. #endif
  3784. wake_up_interruptible(&priv->wait_command_queue);
  3785. /* Keep the restart process from trying to send host
  3786. * commands by clearing the INIT status bit */
  3787. clear_bit(STATUS_READY, &priv->status);
  3788. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3789. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3790. "Restarting adapter due to uCode error.\n");
  3791. if (iwl3945_is_associated(priv)) {
  3792. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3793. sizeof(priv->recovery_rxon));
  3794. priv->error_recovering = 1;
  3795. }
  3796. queue_work(priv->workqueue, &priv->restart);
  3797. }
  3798. }
  3799. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3800. {
  3801. unsigned long flags;
  3802. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3803. sizeof(priv->staging_rxon));
  3804. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3805. iwl3945_commit_rxon(priv);
  3806. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3807. spin_lock_irqsave(&priv->lock, flags);
  3808. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3809. priv->error_recovering = 0;
  3810. spin_unlock_irqrestore(&priv->lock, flags);
  3811. }
  3812. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3813. {
  3814. u32 inta, handled = 0;
  3815. u32 inta_fh;
  3816. unsigned long flags;
  3817. #ifdef CONFIG_IWL3945_DEBUG
  3818. u32 inta_mask;
  3819. #endif
  3820. spin_lock_irqsave(&priv->lock, flags);
  3821. /* Ack/clear/reset pending uCode interrupts.
  3822. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3823. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3824. inta = iwl3945_read32(priv, CSR_INT);
  3825. iwl3945_write32(priv, CSR_INT, inta);
  3826. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3827. * Any new interrupts that happen after this, either while we're
  3828. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3829. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3830. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3831. #ifdef CONFIG_IWL3945_DEBUG
  3832. if (iwl3945_debug_level & IWL_DL_ISR) {
  3833. /* just for debug */
  3834. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3835. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3836. inta, inta_mask, inta_fh);
  3837. }
  3838. #endif
  3839. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3840. * atomic, make sure that inta covers all the interrupts that
  3841. * we've discovered, even if FH interrupt came in just after
  3842. * reading CSR_INT. */
  3843. if (inta_fh & CSR_FH_INT_RX_MASK)
  3844. inta |= CSR_INT_BIT_FH_RX;
  3845. if (inta_fh & CSR_FH_INT_TX_MASK)
  3846. inta |= CSR_INT_BIT_FH_TX;
  3847. /* Now service all interrupt bits discovered above. */
  3848. if (inta & CSR_INT_BIT_HW_ERR) {
  3849. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3850. /* Tell the device to stop sending interrupts */
  3851. iwl3945_disable_interrupts(priv);
  3852. iwl3945_irq_handle_error(priv);
  3853. handled |= CSR_INT_BIT_HW_ERR;
  3854. spin_unlock_irqrestore(&priv->lock, flags);
  3855. return;
  3856. }
  3857. #ifdef CONFIG_IWL3945_DEBUG
  3858. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3859. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3860. if (inta & CSR_INT_BIT_SCD)
  3861. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3862. "the frame/frames.\n");
  3863. /* Alive notification via Rx interrupt will do the real work */
  3864. if (inta & CSR_INT_BIT_ALIVE)
  3865. IWL_DEBUG_ISR("Alive interrupt\n");
  3866. }
  3867. #endif
  3868. /* Safely ignore these bits for debug checks below */
  3869. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3870. /* HW RF KILL switch toggled (4965 only) */
  3871. if (inta & CSR_INT_BIT_RF_KILL) {
  3872. int hw_rf_kill = 0;
  3873. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3874. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3875. hw_rf_kill = 1;
  3876. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3877. "RF_KILL bit toggled to %s.\n",
  3878. hw_rf_kill ? "disable radio":"enable radio");
  3879. /* Queue restart only if RF_KILL switch was set to "kill"
  3880. * when we loaded driver, and is now set to "enable".
  3881. * After we're Alive, RF_KILL gets handled by
  3882. * iwl3945_rx_card_state_notif() */
  3883. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3884. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3885. queue_work(priv->workqueue, &priv->restart);
  3886. }
  3887. handled |= CSR_INT_BIT_RF_KILL;
  3888. }
  3889. /* Chip got too hot and stopped itself (4965 only) */
  3890. if (inta & CSR_INT_BIT_CT_KILL) {
  3891. IWL_ERROR("Microcode CT kill error detected.\n");
  3892. handled |= CSR_INT_BIT_CT_KILL;
  3893. }
  3894. /* Error detected by uCode */
  3895. if (inta & CSR_INT_BIT_SW_ERR) {
  3896. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3897. inta);
  3898. iwl3945_irq_handle_error(priv);
  3899. handled |= CSR_INT_BIT_SW_ERR;
  3900. }
  3901. /* uCode wakes up after power-down sleep */
  3902. if (inta & CSR_INT_BIT_WAKEUP) {
  3903. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3904. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3905. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3906. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3907. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3908. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3909. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3910. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3911. handled |= CSR_INT_BIT_WAKEUP;
  3912. }
  3913. /* All uCode command responses, including Tx command responses,
  3914. * Rx "responses" (frame-received notification), and other
  3915. * notifications from uCode come through here*/
  3916. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3917. iwl3945_rx_handle(priv);
  3918. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3919. }
  3920. if (inta & CSR_INT_BIT_FH_TX) {
  3921. IWL_DEBUG_ISR("Tx interrupt\n");
  3922. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3923. if (!iwl3945_grab_nic_access(priv)) {
  3924. iwl3945_write_direct32(priv,
  3925. FH_TCSR_CREDIT
  3926. (ALM_FH_SRVC_CHNL), 0x0);
  3927. iwl3945_release_nic_access(priv);
  3928. }
  3929. handled |= CSR_INT_BIT_FH_TX;
  3930. }
  3931. if (inta & ~handled)
  3932. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3933. if (inta & ~CSR_INI_SET_MASK) {
  3934. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3935. inta & ~CSR_INI_SET_MASK);
  3936. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3937. }
  3938. /* Re-enable all interrupts */
  3939. iwl3945_enable_interrupts(priv);
  3940. #ifdef CONFIG_IWL3945_DEBUG
  3941. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3942. inta = iwl3945_read32(priv, CSR_INT);
  3943. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3944. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3945. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3946. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3947. }
  3948. #endif
  3949. spin_unlock_irqrestore(&priv->lock, flags);
  3950. }
  3951. static irqreturn_t iwl3945_isr(int irq, void *data)
  3952. {
  3953. struct iwl3945_priv *priv = data;
  3954. u32 inta, inta_mask;
  3955. u32 inta_fh;
  3956. if (!priv)
  3957. return IRQ_NONE;
  3958. spin_lock(&priv->lock);
  3959. /* Disable (but don't clear!) interrupts here to avoid
  3960. * back-to-back ISRs and sporadic interrupts from our NIC.
  3961. * If we have something to service, the tasklet will re-enable ints.
  3962. * If we *don't* have something, we'll re-enable before leaving here. */
  3963. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3964. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3965. /* Discover which interrupts are active/pending */
  3966. inta = iwl3945_read32(priv, CSR_INT);
  3967. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3968. /* Ignore interrupt if there's nothing in NIC to service.
  3969. * This may be due to IRQ shared with another device,
  3970. * or due to sporadic interrupts thrown from our NIC. */
  3971. if (!inta && !inta_fh) {
  3972. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3973. goto none;
  3974. }
  3975. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3976. /* Hardware disappeared */
  3977. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  3978. goto unplugged;
  3979. }
  3980. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3981. inta, inta_mask, inta_fh);
  3982. inta &= ~CSR_INT_BIT_SCD;
  3983. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3984. if (likely(inta || inta_fh))
  3985. tasklet_schedule(&priv->irq_tasklet);
  3986. unplugged:
  3987. spin_unlock(&priv->lock);
  3988. return IRQ_HANDLED;
  3989. none:
  3990. /* re-enable interrupts here since we don't have anything to service. */
  3991. iwl3945_enable_interrupts(priv);
  3992. spin_unlock(&priv->lock);
  3993. return IRQ_NONE;
  3994. }
  3995. /************************** EEPROM BANDS ****************************
  3996. *
  3997. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3998. * EEPROM contents to the specific channel number supported for each
  3999. * band.
  4000. *
  4001. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  4002. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  4003. * The specific geography and calibration information for that channel
  4004. * is contained in the eeprom map itself.
  4005. *
  4006. * During init, we copy the eeprom information and channel map
  4007. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  4008. *
  4009. * channel_map_24/52 provides the index in the channel_info array for a
  4010. * given channel. We have to have two separate maps as there is channel
  4011. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  4012. * band_2
  4013. *
  4014. * A value of 0xff stored in the channel_map indicates that the channel
  4015. * is not supported by the hardware at all.
  4016. *
  4017. * A value of 0xfe in the channel_map indicates that the channel is not
  4018. * valid for Tx with the current hardware. This means that
  4019. * while the system can tune and receive on a given channel, it may not
  4020. * be able to associate or transmit any frames on that
  4021. * channel. There is no corresponding channel information for that
  4022. * entry.
  4023. *
  4024. *********************************************************************/
  4025. /* 2.4 GHz */
  4026. static const u8 iwl3945_eeprom_band_1[14] = {
  4027. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  4028. };
  4029. /* 5.2 GHz bands */
  4030. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  4031. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  4032. };
  4033. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  4034. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  4035. };
  4036. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  4037. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  4038. };
  4039. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  4040. 145, 149, 153, 157, 161, 165
  4041. };
  4042. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  4043. int *eeprom_ch_count,
  4044. const struct iwl3945_eeprom_channel
  4045. **eeprom_ch_info,
  4046. const u8 **eeprom_ch_index)
  4047. {
  4048. switch (band) {
  4049. case 1: /* 2.4GHz band */
  4050. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  4051. *eeprom_ch_info = priv->eeprom.band_1_channels;
  4052. *eeprom_ch_index = iwl3945_eeprom_band_1;
  4053. break;
  4054. case 2: /* 4.9GHz band */
  4055. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  4056. *eeprom_ch_info = priv->eeprom.band_2_channels;
  4057. *eeprom_ch_index = iwl3945_eeprom_band_2;
  4058. break;
  4059. case 3: /* 5.2GHz band */
  4060. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  4061. *eeprom_ch_info = priv->eeprom.band_3_channels;
  4062. *eeprom_ch_index = iwl3945_eeprom_band_3;
  4063. break;
  4064. case 4: /* 5.5GHz band */
  4065. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  4066. *eeprom_ch_info = priv->eeprom.band_4_channels;
  4067. *eeprom_ch_index = iwl3945_eeprom_band_4;
  4068. break;
  4069. case 5: /* 5.7GHz band */
  4070. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  4071. *eeprom_ch_info = priv->eeprom.band_5_channels;
  4072. *eeprom_ch_index = iwl3945_eeprom_band_5;
  4073. break;
  4074. default:
  4075. BUG();
  4076. return;
  4077. }
  4078. }
  4079. /**
  4080. * iwl3945_get_channel_info - Find driver's private channel info
  4081. *
  4082. * Based on band and channel number.
  4083. */
  4084. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  4085. enum ieee80211_band band, u16 channel)
  4086. {
  4087. int i;
  4088. switch (band) {
  4089. case IEEE80211_BAND_5GHZ:
  4090. for (i = 14; i < priv->channel_count; i++) {
  4091. if (priv->channel_info[i].channel == channel)
  4092. return &priv->channel_info[i];
  4093. }
  4094. break;
  4095. case IEEE80211_BAND_2GHZ:
  4096. if (channel >= 1 && channel <= 14)
  4097. return &priv->channel_info[channel - 1];
  4098. break;
  4099. case IEEE80211_NUM_BANDS:
  4100. WARN_ON(1);
  4101. }
  4102. return NULL;
  4103. }
  4104. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4105. ? # x " " : "")
  4106. /**
  4107. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  4108. */
  4109. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  4110. {
  4111. int eeprom_ch_count = 0;
  4112. const u8 *eeprom_ch_index = NULL;
  4113. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4114. int band, ch;
  4115. struct iwl3945_channel_info *ch_info;
  4116. if (priv->channel_count) {
  4117. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4118. return 0;
  4119. }
  4120. if (priv->eeprom.version < 0x2f) {
  4121. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4122. priv->eeprom.version);
  4123. return -EINVAL;
  4124. }
  4125. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4126. priv->channel_count =
  4127. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4128. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4129. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4130. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4131. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4132. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4133. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4134. priv->channel_count, GFP_KERNEL);
  4135. if (!priv->channel_info) {
  4136. IWL_ERROR("Could not allocate channel_info\n");
  4137. priv->channel_count = 0;
  4138. return -ENOMEM;
  4139. }
  4140. ch_info = priv->channel_info;
  4141. /* Loop through the 5 EEPROM bands adding them in order to the
  4142. * channel map we maintain (that contains additional information than
  4143. * what just in the EEPROM) */
  4144. for (band = 1; band <= 5; band++) {
  4145. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4146. &eeprom_ch_info, &eeprom_ch_index);
  4147. /* Loop through each band adding each of the channels */
  4148. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4149. ch_info->channel = eeprom_ch_index[ch];
  4150. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  4151. IEEE80211_BAND_5GHZ;
  4152. /* permanently store EEPROM's channel regulatory flags
  4153. * and max power in channel info database. */
  4154. ch_info->eeprom = eeprom_ch_info[ch];
  4155. /* Copy the run-time flags so they are there even on
  4156. * invalid channels */
  4157. ch_info->flags = eeprom_ch_info[ch].flags;
  4158. if (!(is_channel_valid(ch_info))) {
  4159. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4160. "No traffic\n",
  4161. ch_info->channel,
  4162. ch_info->flags,
  4163. is_channel_a_band(ch_info) ?
  4164. "5.2" : "2.4");
  4165. ch_info++;
  4166. continue;
  4167. }
  4168. /* Initialize regulatory-based run-time data */
  4169. ch_info->max_power_avg = ch_info->curr_txpow =
  4170. eeprom_ch_info[ch].max_power_avg;
  4171. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4172. ch_info->min_power = 0;
  4173. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x"
  4174. " %ddBm): Ad-Hoc %ssupported\n",
  4175. ch_info->channel,
  4176. is_channel_a_band(ch_info) ?
  4177. "5.2" : "2.4",
  4178. CHECK_AND_PRINT(VALID),
  4179. CHECK_AND_PRINT(IBSS),
  4180. CHECK_AND_PRINT(ACTIVE),
  4181. CHECK_AND_PRINT(RADAR),
  4182. CHECK_AND_PRINT(WIDE),
  4183. CHECK_AND_PRINT(NARROW),
  4184. CHECK_AND_PRINT(DFS),
  4185. eeprom_ch_info[ch].flags,
  4186. eeprom_ch_info[ch].max_power_avg,
  4187. ((eeprom_ch_info[ch].
  4188. flags & EEPROM_CHANNEL_IBSS)
  4189. && !(eeprom_ch_info[ch].
  4190. flags & EEPROM_CHANNEL_RADAR))
  4191. ? "" : "not ");
  4192. /* Set the user_txpower_limit to the highest power
  4193. * supported by any channel */
  4194. if (eeprom_ch_info[ch].max_power_avg >
  4195. priv->user_txpower_limit)
  4196. priv->user_txpower_limit =
  4197. eeprom_ch_info[ch].max_power_avg;
  4198. ch_info++;
  4199. }
  4200. }
  4201. /* Set up txpower settings in driver for all channels */
  4202. if (iwl3945_txpower_set_from_eeprom(priv))
  4203. return -EIO;
  4204. return 0;
  4205. }
  4206. /*
  4207. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  4208. */
  4209. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  4210. {
  4211. kfree(priv->channel_info);
  4212. priv->channel_count = 0;
  4213. }
  4214. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4215. * sending probe req. This should be set long enough to hear probe responses
  4216. * from more than one AP. */
  4217. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4218. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4219. /* For faster active scanning, scan will move to the next channel if fewer than
  4220. * PLCP_QUIET_THRESH packets are heard on this channel within
  4221. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4222. * time if it's a quiet channel (nothing responded to our probe, and there's
  4223. * no other traffic).
  4224. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4225. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4226. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4227. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4228. * Must be set longer than active dwell time.
  4229. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4230. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4231. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4232. #define IWL_PASSIVE_DWELL_BASE (100)
  4233. #define IWL_CHANNEL_TUNE_TIME 5
  4234. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  4235. enum ieee80211_band band)
  4236. {
  4237. if (band == IEEE80211_BAND_5GHZ)
  4238. return IWL_ACTIVE_DWELL_TIME_52;
  4239. else
  4240. return IWL_ACTIVE_DWELL_TIME_24;
  4241. }
  4242. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  4243. enum ieee80211_band band)
  4244. {
  4245. u16 active = iwl3945_get_active_dwell_time(priv, band);
  4246. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  4247. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4248. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4249. if (iwl3945_is_associated(priv)) {
  4250. /* If we're associated, we clamp the maximum passive
  4251. * dwell time to be 98% of the beacon interval (minus
  4252. * 2 * channel tune time) */
  4253. passive = priv->beacon_int;
  4254. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4255. passive = IWL_PASSIVE_DWELL_BASE;
  4256. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4257. }
  4258. if (passive <= active)
  4259. passive = active + 1;
  4260. return passive;
  4261. }
  4262. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4263. enum ieee80211_band band,
  4264. u8 is_active, u8 direct_mask,
  4265. struct iwl3945_scan_channel *scan_ch)
  4266. {
  4267. const struct ieee80211_channel *channels = NULL;
  4268. const struct ieee80211_supported_band *sband;
  4269. const struct iwl3945_channel_info *ch_info;
  4270. u16 passive_dwell = 0;
  4271. u16 active_dwell = 0;
  4272. int added, i;
  4273. sband = iwl3945_get_band(priv, band);
  4274. if (!sband)
  4275. return 0;
  4276. channels = sband->channels;
  4277. active_dwell = iwl3945_get_active_dwell_time(priv, band);
  4278. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4279. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4280. if (channels[i].hw_value ==
  4281. le16_to_cpu(priv->active_rxon.channel)) {
  4282. if (iwl3945_is_associated(priv)) {
  4283. IWL_DEBUG_SCAN
  4284. ("Skipping current channel %d\n",
  4285. le16_to_cpu(priv->active_rxon.channel));
  4286. continue;
  4287. }
  4288. } else if (priv->only_active_channel)
  4289. continue;
  4290. scan_ch->channel = channels[i].hw_value;
  4291. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4292. if (!is_channel_valid(ch_info)) {
  4293. IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
  4294. scan_ch->channel);
  4295. continue;
  4296. }
  4297. if (!is_active || is_channel_passive(ch_info) ||
  4298. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4299. scan_ch->type = 0; /* passive */
  4300. else
  4301. scan_ch->type = 1; /* active */
  4302. if (scan_ch->type & 1)
  4303. scan_ch->type |= (direct_mask << 1);
  4304. if (is_channel_narrow(ch_info))
  4305. scan_ch->type |= (1 << 7);
  4306. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4307. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4308. /* Set txpower levels to defaults */
  4309. scan_ch->tpc.dsp_atten = 110;
  4310. /* scan_pwr_info->tpc.dsp_atten; */
  4311. /*scan_pwr_info->tpc.tx_gain; */
  4312. if (band == IEEE80211_BAND_5GHZ)
  4313. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4314. else {
  4315. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4316. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4317. * power level:
  4318. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4319. */
  4320. }
  4321. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4322. scan_ch->channel,
  4323. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4324. (scan_ch->type & 1) ?
  4325. active_dwell : passive_dwell);
  4326. scan_ch++;
  4327. added++;
  4328. }
  4329. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4330. return added;
  4331. }
  4332. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4333. struct ieee80211_rate *rates)
  4334. {
  4335. int i;
  4336. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4337. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4338. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4339. rates[i].hw_value_short = i;
  4340. rates[i].flags = 0;
  4341. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4342. /*
  4343. * If CCK != 1M then set short preamble rate flag.
  4344. */
  4345. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4346. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4347. }
  4348. }
  4349. }
  4350. /**
  4351. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4352. */
  4353. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4354. {
  4355. struct iwl3945_channel_info *ch;
  4356. struct ieee80211_supported_band *sband;
  4357. struct ieee80211_channel *channels;
  4358. struct ieee80211_channel *geo_ch;
  4359. struct ieee80211_rate *rates;
  4360. int i = 0;
  4361. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4362. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4363. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4364. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4365. return 0;
  4366. }
  4367. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4368. priv->channel_count, GFP_KERNEL);
  4369. if (!channels)
  4370. return -ENOMEM;
  4371. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4372. GFP_KERNEL);
  4373. if (!rates) {
  4374. kfree(channels);
  4375. return -ENOMEM;
  4376. }
  4377. /* 5.2GHz channels start after the 2.4GHz channels */
  4378. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4379. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4380. /* just OFDM */
  4381. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4382. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4383. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4384. sband->channels = channels;
  4385. /* OFDM & CCK */
  4386. sband->bitrates = rates;
  4387. sband->n_bitrates = IWL_RATE_COUNT;
  4388. priv->ieee_channels = channels;
  4389. priv->ieee_rates = rates;
  4390. iwl3945_init_hw_rates(priv, rates);
  4391. for (i = 0; i < priv->channel_count; i++) {
  4392. ch = &priv->channel_info[i];
  4393. /* FIXME: might be removed if scan is OK*/
  4394. if (!is_channel_valid(ch))
  4395. continue;
  4396. if (is_channel_a_band(ch))
  4397. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4398. else
  4399. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4400. geo_ch = &sband->channels[sband->n_channels++];
  4401. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4402. geo_ch->max_power = ch->max_power_avg;
  4403. geo_ch->max_antenna_gain = 0xff;
  4404. geo_ch->hw_value = ch->channel;
  4405. if (is_channel_valid(ch)) {
  4406. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4407. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4408. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4409. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4410. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4411. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4412. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4413. priv->max_channel_txpower_limit =
  4414. ch->max_power_avg;
  4415. } else {
  4416. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4417. }
  4418. /* Save flags for reg domain usage */
  4419. geo_ch->orig_flags = geo_ch->flags;
  4420. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4421. ch->channel, geo_ch->center_freq,
  4422. is_channel_a_band(ch) ? "5.2" : "2.4",
  4423. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4424. "restricted" : "valid",
  4425. geo_ch->flags);
  4426. }
  4427. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && priv->is_abg) {
  4428. printk(KERN_INFO DRV_NAME
  4429. ": Incorrectly detected BG card as ABG. Please send "
  4430. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4431. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4432. priv->is_abg = 0;
  4433. }
  4434. printk(KERN_INFO DRV_NAME
  4435. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4436. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4437. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4438. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->bands[IEEE80211_BAND_2GHZ];
  4439. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->bands[IEEE80211_BAND_5GHZ];
  4440. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4441. return 0;
  4442. }
  4443. /*
  4444. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4445. */
  4446. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4447. {
  4448. kfree(priv->ieee_channels);
  4449. kfree(priv->ieee_rates);
  4450. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4451. }
  4452. /******************************************************************************
  4453. *
  4454. * uCode download functions
  4455. *
  4456. ******************************************************************************/
  4457. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4458. {
  4459. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4460. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4461. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4462. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4463. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4464. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4465. }
  4466. /**
  4467. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4468. * looking at all data.
  4469. */
  4470. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4471. {
  4472. u32 val;
  4473. u32 save_len = len;
  4474. int rc = 0;
  4475. u32 errcnt;
  4476. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4477. rc = iwl3945_grab_nic_access(priv);
  4478. if (rc)
  4479. return rc;
  4480. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4481. errcnt = 0;
  4482. for (; len > 0; len -= sizeof(u32), image++) {
  4483. /* read data comes through single port, auto-incr addr */
  4484. /* NOTE: Use the debugless read so we don't flood kernel log
  4485. * if IWL_DL_IO is set */
  4486. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4487. if (val != le32_to_cpu(*image)) {
  4488. IWL_ERROR("uCode INST section is invalid at "
  4489. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4490. save_len - len, val, le32_to_cpu(*image));
  4491. rc = -EIO;
  4492. errcnt++;
  4493. if (errcnt >= 20)
  4494. break;
  4495. }
  4496. }
  4497. iwl3945_release_nic_access(priv);
  4498. if (!errcnt)
  4499. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4500. return rc;
  4501. }
  4502. /**
  4503. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4504. * using sample data 100 bytes apart. If these sample points are good,
  4505. * it's a pretty good bet that everything between them is good, too.
  4506. */
  4507. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4508. {
  4509. u32 val;
  4510. int rc = 0;
  4511. u32 errcnt = 0;
  4512. u32 i;
  4513. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4514. rc = iwl3945_grab_nic_access(priv);
  4515. if (rc)
  4516. return rc;
  4517. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4518. /* read data comes through single port, auto-incr addr */
  4519. /* NOTE: Use the debugless read so we don't flood kernel log
  4520. * if IWL_DL_IO is set */
  4521. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4522. i + RTC_INST_LOWER_BOUND);
  4523. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4524. if (val != le32_to_cpu(*image)) {
  4525. #if 0 /* Enable this if you want to see details */
  4526. IWL_ERROR("uCode INST section is invalid at "
  4527. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4528. i, val, *image);
  4529. #endif
  4530. rc = -EIO;
  4531. errcnt++;
  4532. if (errcnt >= 3)
  4533. break;
  4534. }
  4535. }
  4536. iwl3945_release_nic_access(priv);
  4537. return rc;
  4538. }
  4539. /**
  4540. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4541. * and verify its contents
  4542. */
  4543. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4544. {
  4545. __le32 *image;
  4546. u32 len;
  4547. int rc = 0;
  4548. /* Try bootstrap */
  4549. image = (__le32 *)priv->ucode_boot.v_addr;
  4550. len = priv->ucode_boot.len;
  4551. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4552. if (rc == 0) {
  4553. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4554. return 0;
  4555. }
  4556. /* Try initialize */
  4557. image = (__le32 *)priv->ucode_init.v_addr;
  4558. len = priv->ucode_init.len;
  4559. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4560. if (rc == 0) {
  4561. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4562. return 0;
  4563. }
  4564. /* Try runtime/protocol */
  4565. image = (__le32 *)priv->ucode_code.v_addr;
  4566. len = priv->ucode_code.len;
  4567. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4568. if (rc == 0) {
  4569. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4570. return 0;
  4571. }
  4572. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4573. /* Since nothing seems to match, show first several data entries in
  4574. * instruction SRAM, so maybe visual inspection will give a clue.
  4575. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4576. image = (__le32 *)priv->ucode_boot.v_addr;
  4577. len = priv->ucode_boot.len;
  4578. rc = iwl3945_verify_inst_full(priv, image, len);
  4579. return rc;
  4580. }
  4581. /* check contents of special bootstrap uCode SRAM */
  4582. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4583. {
  4584. __le32 *image = priv->ucode_boot.v_addr;
  4585. u32 len = priv->ucode_boot.len;
  4586. u32 reg;
  4587. u32 val;
  4588. IWL_DEBUG_INFO("Begin verify bsm\n");
  4589. /* verify BSM SRAM contents */
  4590. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4591. for (reg = BSM_SRAM_LOWER_BOUND;
  4592. reg < BSM_SRAM_LOWER_BOUND + len;
  4593. reg += sizeof(u32), image ++) {
  4594. val = iwl3945_read_prph(priv, reg);
  4595. if (val != le32_to_cpu(*image)) {
  4596. IWL_ERROR("BSM uCode verification failed at "
  4597. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4598. BSM_SRAM_LOWER_BOUND,
  4599. reg - BSM_SRAM_LOWER_BOUND, len,
  4600. val, le32_to_cpu(*image));
  4601. return -EIO;
  4602. }
  4603. }
  4604. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4605. return 0;
  4606. }
  4607. /**
  4608. * iwl3945_load_bsm - Load bootstrap instructions
  4609. *
  4610. * BSM operation:
  4611. *
  4612. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4613. * in special SRAM that does not power down during RFKILL. When powering back
  4614. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4615. * the bootstrap program into the on-board processor, and starts it.
  4616. *
  4617. * The bootstrap program loads (via DMA) instructions and data for a new
  4618. * program from host DRAM locations indicated by the host driver in the
  4619. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4620. * automatically.
  4621. *
  4622. * When initializing the NIC, the host driver points the BSM to the
  4623. * "initialize" uCode image. This uCode sets up some internal data, then
  4624. * notifies host via "initialize alive" that it is complete.
  4625. *
  4626. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4627. * normal runtime uCode instructions and a backup uCode data cache buffer
  4628. * (filled initially with starting data values for the on-board processor),
  4629. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4630. * which begins normal operation.
  4631. *
  4632. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4633. * the backup data cache in DRAM before SRAM is powered down.
  4634. *
  4635. * When powering back up, the BSM loads the bootstrap program. This reloads
  4636. * the runtime uCode instructions and the backup data cache into SRAM,
  4637. * and re-launches the runtime uCode from where it left off.
  4638. */
  4639. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4640. {
  4641. __le32 *image = priv->ucode_boot.v_addr;
  4642. u32 len = priv->ucode_boot.len;
  4643. dma_addr_t pinst;
  4644. dma_addr_t pdata;
  4645. u32 inst_len;
  4646. u32 data_len;
  4647. int rc;
  4648. int i;
  4649. u32 done;
  4650. u32 reg_offset;
  4651. IWL_DEBUG_INFO("Begin load bsm\n");
  4652. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4653. if (len > IWL_MAX_BSM_SIZE)
  4654. return -EINVAL;
  4655. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4656. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4657. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4658. * after the "initialize" uCode has run, to point to
  4659. * runtime/protocol instructions and backup data cache. */
  4660. pinst = priv->ucode_init.p_addr;
  4661. pdata = priv->ucode_init_data.p_addr;
  4662. inst_len = priv->ucode_init.len;
  4663. data_len = priv->ucode_init_data.len;
  4664. rc = iwl3945_grab_nic_access(priv);
  4665. if (rc)
  4666. return rc;
  4667. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4668. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4669. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4670. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4671. /* Fill BSM memory with bootstrap instructions */
  4672. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4673. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4674. reg_offset += sizeof(u32), image++)
  4675. _iwl3945_write_prph(priv, reg_offset,
  4676. le32_to_cpu(*image));
  4677. rc = iwl3945_verify_bsm(priv);
  4678. if (rc) {
  4679. iwl3945_release_nic_access(priv);
  4680. return rc;
  4681. }
  4682. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4683. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4684. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4685. RTC_INST_LOWER_BOUND);
  4686. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4687. /* Load bootstrap code into instruction SRAM now,
  4688. * to prepare to load "initialize" uCode */
  4689. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4690. BSM_WR_CTRL_REG_BIT_START);
  4691. /* Wait for load of bootstrap uCode to finish */
  4692. for (i = 0; i < 100; i++) {
  4693. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4694. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4695. break;
  4696. udelay(10);
  4697. }
  4698. if (i < 100)
  4699. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4700. else {
  4701. IWL_ERROR("BSM write did not complete!\n");
  4702. return -EIO;
  4703. }
  4704. /* Enable future boot loads whenever power management unit triggers it
  4705. * (e.g. when powering back up after power-save shutdown) */
  4706. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4707. BSM_WR_CTRL_REG_BIT_START_EN);
  4708. iwl3945_release_nic_access(priv);
  4709. return 0;
  4710. }
  4711. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4712. {
  4713. /* Remove all resets to allow NIC to operate */
  4714. iwl3945_write32(priv, CSR_RESET, 0);
  4715. }
  4716. /**
  4717. * iwl3945_read_ucode - Read uCode images from disk file.
  4718. *
  4719. * Copy into buffers for card to fetch via bus-mastering
  4720. */
  4721. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4722. {
  4723. struct iwl3945_ucode *ucode;
  4724. int ret = 0;
  4725. const struct firmware *ucode_raw;
  4726. /* firmware file name contains uCode/driver compatibility version */
  4727. const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode";
  4728. u8 *src;
  4729. size_t len;
  4730. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4731. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4732. * request_firmware() is synchronous, file is in memory on return. */
  4733. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4734. if (ret < 0) {
  4735. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4736. name, ret);
  4737. goto error;
  4738. }
  4739. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4740. name, ucode_raw->size);
  4741. /* Make sure that we got at least our header! */
  4742. if (ucode_raw->size < sizeof(*ucode)) {
  4743. IWL_ERROR("File size way too small!\n");
  4744. ret = -EINVAL;
  4745. goto err_release;
  4746. }
  4747. /* Data from ucode file: header followed by uCode images */
  4748. ucode = (void *)ucode_raw->data;
  4749. ver = le32_to_cpu(ucode->ver);
  4750. inst_size = le32_to_cpu(ucode->inst_size);
  4751. data_size = le32_to_cpu(ucode->data_size);
  4752. init_size = le32_to_cpu(ucode->init_size);
  4753. init_data_size = le32_to_cpu(ucode->init_data_size);
  4754. boot_size = le32_to_cpu(ucode->boot_size);
  4755. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4756. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4757. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4758. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4759. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4760. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4761. /* Verify size of file vs. image size info in file's header */
  4762. if (ucode_raw->size < sizeof(*ucode) +
  4763. inst_size + data_size + init_size +
  4764. init_data_size + boot_size) {
  4765. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4766. (int)ucode_raw->size);
  4767. ret = -EINVAL;
  4768. goto err_release;
  4769. }
  4770. /* Verify that uCode images will fit in card's SRAM */
  4771. if (inst_size > IWL_MAX_INST_SIZE) {
  4772. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4773. inst_size);
  4774. ret = -EINVAL;
  4775. goto err_release;
  4776. }
  4777. if (data_size > IWL_MAX_DATA_SIZE) {
  4778. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4779. data_size);
  4780. ret = -EINVAL;
  4781. goto err_release;
  4782. }
  4783. if (init_size > IWL_MAX_INST_SIZE) {
  4784. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4785. init_size);
  4786. ret = -EINVAL;
  4787. goto err_release;
  4788. }
  4789. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4790. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4791. init_data_size);
  4792. ret = -EINVAL;
  4793. goto err_release;
  4794. }
  4795. if (boot_size > IWL_MAX_BSM_SIZE) {
  4796. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4797. boot_size);
  4798. ret = -EINVAL;
  4799. goto err_release;
  4800. }
  4801. /* Allocate ucode buffers for card's bus-master loading ... */
  4802. /* Runtime instructions and 2 copies of data:
  4803. * 1) unmodified from disk
  4804. * 2) backup cache for save/restore during power-downs */
  4805. priv->ucode_code.len = inst_size;
  4806. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4807. priv->ucode_data.len = data_size;
  4808. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4809. priv->ucode_data_backup.len = data_size;
  4810. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4811. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4812. !priv->ucode_data_backup.v_addr)
  4813. goto err_pci_alloc;
  4814. /* Initialization instructions and data */
  4815. if (init_size && init_data_size) {
  4816. priv->ucode_init.len = init_size;
  4817. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4818. priv->ucode_init_data.len = init_data_size;
  4819. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4820. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4821. goto err_pci_alloc;
  4822. }
  4823. /* Bootstrap (instructions only, no data) */
  4824. if (boot_size) {
  4825. priv->ucode_boot.len = boot_size;
  4826. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4827. if (!priv->ucode_boot.v_addr)
  4828. goto err_pci_alloc;
  4829. }
  4830. /* Copy images into buffers for card's bus-master reads ... */
  4831. /* Runtime instructions (first block of data in file) */
  4832. src = &ucode->data[0];
  4833. len = priv->ucode_code.len;
  4834. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4835. memcpy(priv->ucode_code.v_addr, src, len);
  4836. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4837. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4838. /* Runtime data (2nd block)
  4839. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4840. src = &ucode->data[inst_size];
  4841. len = priv->ucode_data.len;
  4842. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4843. memcpy(priv->ucode_data.v_addr, src, len);
  4844. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4845. /* Initialization instructions (3rd block) */
  4846. if (init_size) {
  4847. src = &ucode->data[inst_size + data_size];
  4848. len = priv->ucode_init.len;
  4849. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4850. len);
  4851. memcpy(priv->ucode_init.v_addr, src, len);
  4852. }
  4853. /* Initialization data (4th block) */
  4854. if (init_data_size) {
  4855. src = &ucode->data[inst_size + data_size + init_size];
  4856. len = priv->ucode_init_data.len;
  4857. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4858. (int)len);
  4859. memcpy(priv->ucode_init_data.v_addr, src, len);
  4860. }
  4861. /* Bootstrap instructions (5th block) */
  4862. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4863. len = priv->ucode_boot.len;
  4864. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4865. (int)len);
  4866. memcpy(priv->ucode_boot.v_addr, src, len);
  4867. /* We have our copies now, allow OS release its copies */
  4868. release_firmware(ucode_raw);
  4869. return 0;
  4870. err_pci_alloc:
  4871. IWL_ERROR("failed to allocate pci memory\n");
  4872. ret = -ENOMEM;
  4873. iwl3945_dealloc_ucode_pci(priv);
  4874. err_release:
  4875. release_firmware(ucode_raw);
  4876. error:
  4877. return ret;
  4878. }
  4879. /**
  4880. * iwl3945_set_ucode_ptrs - Set uCode address location
  4881. *
  4882. * Tell initialization uCode where to find runtime uCode.
  4883. *
  4884. * BSM registers initially contain pointers to initialization uCode.
  4885. * We need to replace them to load runtime uCode inst and data,
  4886. * and to save runtime data when powering down.
  4887. */
  4888. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4889. {
  4890. dma_addr_t pinst;
  4891. dma_addr_t pdata;
  4892. int rc = 0;
  4893. unsigned long flags;
  4894. /* bits 31:0 for 3945 */
  4895. pinst = priv->ucode_code.p_addr;
  4896. pdata = priv->ucode_data_backup.p_addr;
  4897. spin_lock_irqsave(&priv->lock, flags);
  4898. rc = iwl3945_grab_nic_access(priv);
  4899. if (rc) {
  4900. spin_unlock_irqrestore(&priv->lock, flags);
  4901. return rc;
  4902. }
  4903. /* Tell bootstrap uCode where to find image to load */
  4904. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4905. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4906. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4907. priv->ucode_data.len);
  4908. /* Inst bytecount must be last to set up, bit 31 signals uCode
  4909. * that all new ptr/size info is in place */
  4910. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4911. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4912. iwl3945_release_nic_access(priv);
  4913. spin_unlock_irqrestore(&priv->lock, flags);
  4914. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4915. return rc;
  4916. }
  4917. /**
  4918. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4919. *
  4920. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4921. *
  4922. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4923. */
  4924. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4925. {
  4926. /* Check alive response for "valid" sign from uCode */
  4927. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4928. /* We had an error bringing up the hardware, so take it
  4929. * all the way back down so we can try again */
  4930. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4931. goto restart;
  4932. }
  4933. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4934. * This is a paranoid check, because we would not have gotten the
  4935. * "initialize" alive if code weren't properly loaded. */
  4936. if (iwl3945_verify_ucode(priv)) {
  4937. /* Runtime instruction load was bad;
  4938. * take it all the way back down so we can try again */
  4939. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4940. goto restart;
  4941. }
  4942. /* Send pointers to protocol/runtime uCode image ... init code will
  4943. * load and launch runtime uCode, which will send us another "Alive"
  4944. * notification. */
  4945. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4946. if (iwl3945_set_ucode_ptrs(priv)) {
  4947. /* Runtime instruction load won't happen;
  4948. * take it all the way back down so we can try again */
  4949. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4950. goto restart;
  4951. }
  4952. return;
  4953. restart:
  4954. queue_work(priv->workqueue, &priv->restart);
  4955. }
  4956. /**
  4957. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4958. * from protocol/runtime uCode (initialization uCode's
  4959. * Alive gets handled by iwl3945_init_alive_start()).
  4960. */
  4961. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4962. {
  4963. int rc = 0;
  4964. int thermal_spin = 0;
  4965. u32 rfkill;
  4966. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4967. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4968. /* We had an error bringing up the hardware, so take it
  4969. * all the way back down so we can try again */
  4970. IWL_DEBUG_INFO("Alive failed.\n");
  4971. goto restart;
  4972. }
  4973. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4974. * This is a paranoid check, because we would not have gotten the
  4975. * "runtime" alive if code weren't properly loaded. */
  4976. if (iwl3945_verify_ucode(priv)) {
  4977. /* Runtime instruction load was bad;
  4978. * take it all the way back down so we can try again */
  4979. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4980. goto restart;
  4981. }
  4982. iwl3945_clear_stations_table(priv);
  4983. rc = iwl3945_grab_nic_access(priv);
  4984. if (rc) {
  4985. IWL_WARNING("Can not read rfkill status from adapter\n");
  4986. return;
  4987. }
  4988. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4989. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4990. iwl3945_release_nic_access(priv);
  4991. if (rfkill & 0x1) {
  4992. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4993. /* if rfkill is not on, then wait for thermal
  4994. * sensor in adapter to kick in */
  4995. while (iwl3945_hw_get_temperature(priv) == 0) {
  4996. thermal_spin++;
  4997. udelay(10);
  4998. }
  4999. if (thermal_spin)
  5000. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  5001. thermal_spin * 10);
  5002. } else
  5003. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5004. /* After the ALIVE response, we can send commands to 3945 uCode */
  5005. set_bit(STATUS_ALIVE, &priv->status);
  5006. /* Clear out the uCode error bit if it is set */
  5007. clear_bit(STATUS_FW_ERROR, &priv->status);
  5008. if (iwl3945_is_rfkill(priv))
  5009. return;
  5010. ieee80211_start_queues(priv->hw);
  5011. priv->active_rate = priv->rates_mask;
  5012. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  5013. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  5014. if (iwl3945_is_associated(priv)) {
  5015. struct iwl3945_rxon_cmd *active_rxon =
  5016. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  5017. memcpy(&priv->staging_rxon, &priv->active_rxon,
  5018. sizeof(priv->staging_rxon));
  5019. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5020. } else {
  5021. /* Initialize our rx_config data */
  5022. iwl3945_connection_init_rx_config(priv);
  5023. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  5024. }
  5025. /* Configure Bluetooth device coexistence support */
  5026. iwl3945_send_bt_config(priv);
  5027. /* Configure the adapter for unassociated operation */
  5028. iwl3945_commit_rxon(priv);
  5029. /* At this point, the NIC is initialized and operational */
  5030. priv->notif_missed_beacons = 0;
  5031. set_bit(STATUS_READY, &priv->status);
  5032. iwl3945_reg_txpower_periodic(priv);
  5033. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  5034. wake_up_interruptible(&priv->wait_command_queue);
  5035. if (priv->error_recovering)
  5036. iwl3945_error_recovery(priv);
  5037. return;
  5038. restart:
  5039. queue_work(priv->workqueue, &priv->restart);
  5040. }
  5041. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  5042. static void __iwl3945_down(struct iwl3945_priv *priv)
  5043. {
  5044. unsigned long flags;
  5045. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  5046. struct ieee80211_conf *conf = NULL;
  5047. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  5048. conf = ieee80211_get_hw_conf(priv->hw);
  5049. if (!exit_pending)
  5050. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5051. iwl3945_clear_stations_table(priv);
  5052. /* Unblock any waiting calls */
  5053. wake_up_interruptible_all(&priv->wait_command_queue);
  5054. /* Wipe out the EXIT_PENDING status bit if we are not actually
  5055. * exiting the module */
  5056. if (!exit_pending)
  5057. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  5058. /* stop and reset the on-board processor */
  5059. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  5060. /* tell the device to stop sending interrupts */
  5061. iwl3945_disable_interrupts(priv);
  5062. if (priv->mac80211_registered)
  5063. ieee80211_stop_queues(priv->hw);
  5064. /* If we have not previously called iwl3945_init() then
  5065. * clear all bits but the RF Kill and SUSPEND bits and return */
  5066. if (!iwl3945_is_init(priv)) {
  5067. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5068. STATUS_RF_KILL_HW |
  5069. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5070. STATUS_RF_KILL_SW |
  5071. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  5072. STATUS_GEO_CONFIGURED |
  5073. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5074. STATUS_IN_SUSPEND;
  5075. goto exit;
  5076. }
  5077. /* ...otherwise clear out all the status bits but the RF Kill and
  5078. * SUSPEND bits and continue taking the NIC down. */
  5079. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5080. STATUS_RF_KILL_HW |
  5081. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5082. STATUS_RF_KILL_SW |
  5083. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  5084. STATUS_GEO_CONFIGURED |
  5085. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5086. STATUS_IN_SUSPEND |
  5087. test_bit(STATUS_FW_ERROR, &priv->status) <<
  5088. STATUS_FW_ERROR;
  5089. spin_lock_irqsave(&priv->lock, flags);
  5090. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  5091. spin_unlock_irqrestore(&priv->lock, flags);
  5092. iwl3945_hw_txq_ctx_stop(priv);
  5093. iwl3945_hw_rxq_stop(priv);
  5094. spin_lock_irqsave(&priv->lock, flags);
  5095. if (!iwl3945_grab_nic_access(priv)) {
  5096. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  5097. APMG_CLK_VAL_DMA_CLK_RQT);
  5098. iwl3945_release_nic_access(priv);
  5099. }
  5100. spin_unlock_irqrestore(&priv->lock, flags);
  5101. udelay(5);
  5102. iwl3945_hw_nic_stop_master(priv);
  5103. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  5104. iwl3945_hw_nic_reset(priv);
  5105. exit:
  5106. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  5107. if (priv->ibss_beacon)
  5108. dev_kfree_skb(priv->ibss_beacon);
  5109. priv->ibss_beacon = NULL;
  5110. /* clear out any free frames */
  5111. iwl3945_clear_free_frames(priv);
  5112. }
  5113. static void iwl3945_down(struct iwl3945_priv *priv)
  5114. {
  5115. mutex_lock(&priv->mutex);
  5116. __iwl3945_down(priv);
  5117. mutex_unlock(&priv->mutex);
  5118. iwl3945_cancel_deferred_work(priv);
  5119. }
  5120. #define MAX_HW_RESTARTS 5
  5121. static int __iwl3945_up(struct iwl3945_priv *priv)
  5122. {
  5123. int rc, i;
  5124. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5125. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5126. return -EIO;
  5127. }
  5128. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5129. IWL_WARNING("Radio disabled by SW RF kill (module "
  5130. "parameter)\n");
  5131. return -ENODEV;
  5132. }
  5133. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5134. IWL_ERROR("ucode not available for device bringup\n");
  5135. return -EIO;
  5136. }
  5137. /* If platform's RF_KILL switch is NOT set to KILL */
  5138. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  5139. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  5140. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5141. else {
  5142. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5143. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  5144. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  5145. return -ENODEV;
  5146. }
  5147. }
  5148. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5149. rc = iwl3945_hw_nic_init(priv);
  5150. if (rc) {
  5151. IWL_ERROR("Unable to int nic\n");
  5152. return rc;
  5153. }
  5154. /* make sure rfkill handshake bits are cleared */
  5155. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5156. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5157. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5158. /* clear (again), then enable host interrupts */
  5159. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5160. iwl3945_enable_interrupts(priv);
  5161. /* really make sure rfkill handshake bits are cleared */
  5162. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5163. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5164. /* Copy original ucode data image from disk into backup cache.
  5165. * This will be used to initialize the on-board processor's
  5166. * data SRAM for a clean start when the runtime program first loads. */
  5167. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5168. priv->ucode_data.len);
  5169. /* We return success when we resume from suspend and rf_kill is on. */
  5170. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  5171. return 0;
  5172. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5173. iwl3945_clear_stations_table(priv);
  5174. /* load bootstrap state machine,
  5175. * load bootstrap program into processor's memory,
  5176. * prepare to load the "initialize" uCode */
  5177. rc = iwl3945_load_bsm(priv);
  5178. if (rc) {
  5179. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5180. continue;
  5181. }
  5182. /* start card; "initialize" will load runtime ucode */
  5183. iwl3945_nic_start(priv);
  5184. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5185. return 0;
  5186. }
  5187. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5188. __iwl3945_down(priv);
  5189. /* tried to restart and config the device for as long as our
  5190. * patience could withstand */
  5191. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5192. return -EIO;
  5193. }
  5194. /*****************************************************************************
  5195. *
  5196. * Workqueue callbacks
  5197. *
  5198. *****************************************************************************/
  5199. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5200. {
  5201. struct iwl3945_priv *priv =
  5202. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5203. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5204. return;
  5205. mutex_lock(&priv->mutex);
  5206. iwl3945_init_alive_start(priv);
  5207. mutex_unlock(&priv->mutex);
  5208. }
  5209. static void iwl3945_bg_alive_start(struct work_struct *data)
  5210. {
  5211. struct iwl3945_priv *priv =
  5212. container_of(data, struct iwl3945_priv, alive_start.work);
  5213. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5214. return;
  5215. mutex_lock(&priv->mutex);
  5216. iwl3945_alive_start(priv);
  5217. mutex_unlock(&priv->mutex);
  5218. }
  5219. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5220. {
  5221. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5222. wake_up_interruptible(&priv->wait_command_queue);
  5223. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5224. return;
  5225. mutex_lock(&priv->mutex);
  5226. if (!iwl3945_is_rfkill(priv)) {
  5227. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5228. "HW and/or SW RF Kill no longer active, restarting "
  5229. "device\n");
  5230. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5231. queue_work(priv->workqueue, &priv->restart);
  5232. } else {
  5233. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5234. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5235. "disabled by SW switch\n");
  5236. else
  5237. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5238. "Kill switch must be turned off for "
  5239. "wireless networking to work.\n");
  5240. }
  5241. mutex_unlock(&priv->mutex);
  5242. }
  5243. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5244. static void iwl3945_bg_scan_check(struct work_struct *data)
  5245. {
  5246. struct iwl3945_priv *priv =
  5247. container_of(data, struct iwl3945_priv, scan_check.work);
  5248. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5249. return;
  5250. mutex_lock(&priv->mutex);
  5251. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5252. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5253. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5254. "Scan completion watchdog resetting adapter (%dms)\n",
  5255. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5256. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5257. iwl3945_send_scan_abort(priv);
  5258. }
  5259. mutex_unlock(&priv->mutex);
  5260. }
  5261. static void iwl3945_bg_request_scan(struct work_struct *data)
  5262. {
  5263. struct iwl3945_priv *priv =
  5264. container_of(data, struct iwl3945_priv, request_scan);
  5265. struct iwl3945_host_cmd cmd = {
  5266. .id = REPLY_SCAN_CMD,
  5267. .len = sizeof(struct iwl3945_scan_cmd),
  5268. .meta.flags = CMD_SIZE_HUGE,
  5269. };
  5270. int rc = 0;
  5271. struct iwl3945_scan_cmd *scan;
  5272. struct ieee80211_conf *conf = NULL;
  5273. u8 direct_mask;
  5274. enum ieee80211_band band;
  5275. conf = ieee80211_get_hw_conf(priv->hw);
  5276. mutex_lock(&priv->mutex);
  5277. if (!iwl3945_is_ready(priv)) {
  5278. IWL_WARNING("request scan called when driver not ready.\n");
  5279. goto done;
  5280. }
  5281. /* Make sure the scan wasn't cancelled before this queued work
  5282. * was given the chance to run... */
  5283. if (!test_bit(STATUS_SCANNING, &priv->status))
  5284. goto done;
  5285. /* This should never be called or scheduled if there is currently
  5286. * a scan active in the hardware. */
  5287. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5288. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5289. "Ignoring second request.\n");
  5290. rc = -EIO;
  5291. goto done;
  5292. }
  5293. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5294. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5295. goto done;
  5296. }
  5297. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5298. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5299. goto done;
  5300. }
  5301. if (iwl3945_is_rfkill(priv)) {
  5302. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5303. goto done;
  5304. }
  5305. if (!test_bit(STATUS_READY, &priv->status)) {
  5306. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5307. goto done;
  5308. }
  5309. if (!priv->scan_bands) {
  5310. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5311. goto done;
  5312. }
  5313. if (!priv->scan) {
  5314. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5315. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5316. if (!priv->scan) {
  5317. rc = -ENOMEM;
  5318. goto done;
  5319. }
  5320. }
  5321. scan = priv->scan;
  5322. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5323. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5324. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5325. if (iwl3945_is_associated(priv)) {
  5326. u16 interval = 0;
  5327. u32 extra;
  5328. u32 suspend_time = 100;
  5329. u32 scan_suspend_time = 100;
  5330. unsigned long flags;
  5331. IWL_DEBUG_INFO("Scanning while associated...\n");
  5332. spin_lock_irqsave(&priv->lock, flags);
  5333. interval = priv->beacon_int;
  5334. spin_unlock_irqrestore(&priv->lock, flags);
  5335. scan->suspend_time = 0;
  5336. scan->max_out_time = cpu_to_le32(200 * 1024);
  5337. if (!interval)
  5338. interval = suspend_time;
  5339. /*
  5340. * suspend time format:
  5341. * 0-19: beacon interval in usec (time before exec.)
  5342. * 20-23: 0
  5343. * 24-31: number of beacons (suspend between channels)
  5344. */
  5345. extra = (suspend_time / interval) << 24;
  5346. scan_suspend_time = 0xFF0FFFFF &
  5347. (extra | ((suspend_time % interval) * 1024));
  5348. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5349. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5350. scan_suspend_time, interval);
  5351. }
  5352. /* We should add the ability for user to lock to PASSIVE ONLY */
  5353. if (priv->one_direct_scan) {
  5354. IWL_DEBUG_SCAN
  5355. ("Kicking off one direct scan for '%s'\n",
  5356. iwl3945_escape_essid(priv->direct_ssid,
  5357. priv->direct_ssid_len));
  5358. scan->direct_scan[0].id = WLAN_EID_SSID;
  5359. scan->direct_scan[0].len = priv->direct_ssid_len;
  5360. memcpy(scan->direct_scan[0].ssid,
  5361. priv->direct_ssid, priv->direct_ssid_len);
  5362. direct_mask = 1;
  5363. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5364. scan->direct_scan[0].id = WLAN_EID_SSID;
  5365. scan->direct_scan[0].len = priv->essid_len;
  5366. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5367. direct_mask = 1;
  5368. } else
  5369. direct_mask = 0;
  5370. /* We don't build a direct scan probe request; the uCode will do
  5371. * that based on the direct_mask added to each channel entry */
  5372. scan->tx_cmd.len = cpu_to_le16(
  5373. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5374. IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
  5375. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5376. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5377. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5378. /* flags + rate selection */
  5379. switch (priv->scan_bands) {
  5380. case 2:
  5381. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5382. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5383. scan->good_CRC_th = 0;
  5384. band = IEEE80211_BAND_2GHZ;
  5385. break;
  5386. case 1:
  5387. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5388. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5389. band = IEEE80211_BAND_5GHZ;
  5390. break;
  5391. default:
  5392. IWL_WARNING("Invalid scan band count\n");
  5393. goto done;
  5394. }
  5395. /* select Rx antennas */
  5396. scan->flags |= iwl3945_get_antenna_flags(priv);
  5397. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5398. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5399. if (direct_mask)
  5400. IWL_DEBUG_SCAN
  5401. ("Initiating direct scan for %s.\n",
  5402. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5403. else
  5404. IWL_DEBUG_SCAN("Initiating indirect scan.\n");
  5405. scan->channel_count =
  5406. iwl3945_get_channels_for_scan(
  5407. priv, band, 1, /* active */
  5408. direct_mask,
  5409. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5410. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5411. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5412. cmd.data = scan;
  5413. scan->len = cpu_to_le16(cmd.len);
  5414. set_bit(STATUS_SCAN_HW, &priv->status);
  5415. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5416. if (rc)
  5417. goto done;
  5418. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5419. IWL_SCAN_CHECK_WATCHDOG);
  5420. mutex_unlock(&priv->mutex);
  5421. return;
  5422. done:
  5423. /* inform mac80211 scan aborted */
  5424. queue_work(priv->workqueue, &priv->scan_completed);
  5425. mutex_unlock(&priv->mutex);
  5426. }
  5427. static void iwl3945_bg_up(struct work_struct *data)
  5428. {
  5429. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5430. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5431. return;
  5432. mutex_lock(&priv->mutex);
  5433. __iwl3945_up(priv);
  5434. mutex_unlock(&priv->mutex);
  5435. }
  5436. static void iwl3945_bg_restart(struct work_struct *data)
  5437. {
  5438. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5439. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5440. return;
  5441. iwl3945_down(priv);
  5442. queue_work(priv->workqueue, &priv->up);
  5443. }
  5444. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5445. {
  5446. struct iwl3945_priv *priv =
  5447. container_of(data, struct iwl3945_priv, rx_replenish);
  5448. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5449. return;
  5450. mutex_lock(&priv->mutex);
  5451. iwl3945_rx_replenish(priv);
  5452. mutex_unlock(&priv->mutex);
  5453. }
  5454. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5455. static void iwl3945_bg_post_associate(struct work_struct *data)
  5456. {
  5457. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5458. post_associate.work);
  5459. int rc = 0;
  5460. struct ieee80211_conf *conf = NULL;
  5461. DECLARE_MAC_BUF(mac);
  5462. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5463. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5464. return;
  5465. }
  5466. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5467. priv->assoc_id,
  5468. print_mac(mac, priv->active_rxon.bssid_addr));
  5469. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5470. return;
  5471. mutex_lock(&priv->mutex);
  5472. if (!priv->vif || !priv->is_open) {
  5473. mutex_unlock(&priv->mutex);
  5474. return;
  5475. }
  5476. iwl3945_scan_cancel_timeout(priv, 200);
  5477. conf = ieee80211_get_hw_conf(priv->hw);
  5478. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5479. iwl3945_commit_rxon(priv);
  5480. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5481. iwl3945_setup_rxon_timing(priv);
  5482. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5483. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5484. if (rc)
  5485. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5486. "Attempting to continue.\n");
  5487. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5488. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5489. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5490. priv->assoc_id, priv->beacon_int);
  5491. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5492. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5493. else
  5494. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5495. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5496. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5497. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5498. else
  5499. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5500. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5501. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5502. }
  5503. iwl3945_commit_rxon(priv);
  5504. switch (priv->iw_mode) {
  5505. case IEEE80211_IF_TYPE_STA:
  5506. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5507. break;
  5508. case IEEE80211_IF_TYPE_IBSS:
  5509. /* clear out the station table */
  5510. iwl3945_clear_stations_table(priv);
  5511. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5512. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5513. iwl3945_sync_sta(priv, IWL_STA_ID,
  5514. (priv->band == IEEE80211_BAND_5GHZ) ?
  5515. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5516. CMD_ASYNC);
  5517. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5518. iwl3945_send_beacon_cmd(priv);
  5519. break;
  5520. default:
  5521. IWL_ERROR("%s Should not be called in %d mode\n",
  5522. __FUNCTION__, priv->iw_mode);
  5523. break;
  5524. }
  5525. iwl3945_sequence_reset(priv);
  5526. iwl3945_activate_qos(priv, 0);
  5527. /* we have just associated, don't start scan too early */
  5528. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5529. mutex_unlock(&priv->mutex);
  5530. }
  5531. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5532. {
  5533. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5534. if (!iwl3945_is_ready(priv))
  5535. return;
  5536. mutex_lock(&priv->mutex);
  5537. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5538. iwl3945_send_scan_abort(priv);
  5539. mutex_unlock(&priv->mutex);
  5540. }
  5541. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
  5542. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5543. {
  5544. struct iwl3945_priv *priv =
  5545. container_of(work, struct iwl3945_priv, scan_completed);
  5546. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5547. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5548. return;
  5549. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5550. iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
  5551. ieee80211_scan_completed(priv->hw);
  5552. /* Since setting the TXPOWER may have been deferred while
  5553. * performing the scan, fire one off */
  5554. mutex_lock(&priv->mutex);
  5555. iwl3945_hw_reg_send_txpower(priv);
  5556. mutex_unlock(&priv->mutex);
  5557. }
  5558. /*****************************************************************************
  5559. *
  5560. * mac80211 entry point functions
  5561. *
  5562. *****************************************************************************/
  5563. #define UCODE_READY_TIMEOUT (2 * HZ)
  5564. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5565. {
  5566. struct iwl3945_priv *priv = hw->priv;
  5567. int ret;
  5568. IWL_DEBUG_MAC80211("enter\n");
  5569. if (pci_enable_device(priv->pci_dev)) {
  5570. IWL_ERROR("Fail to pci_enable_device\n");
  5571. return -ENODEV;
  5572. }
  5573. pci_restore_state(priv->pci_dev);
  5574. pci_enable_msi(priv->pci_dev);
  5575. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5576. DRV_NAME, priv);
  5577. if (ret) {
  5578. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5579. goto out_disable_msi;
  5580. }
  5581. /* we should be verifying the device is ready to be opened */
  5582. mutex_lock(&priv->mutex);
  5583. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5584. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5585. * ucode filename and max sizes are card-specific. */
  5586. if (!priv->ucode_code.len) {
  5587. ret = iwl3945_read_ucode(priv);
  5588. if (ret) {
  5589. IWL_ERROR("Could not read microcode: %d\n", ret);
  5590. mutex_unlock(&priv->mutex);
  5591. goto out_release_irq;
  5592. }
  5593. }
  5594. ret = __iwl3945_up(priv);
  5595. mutex_unlock(&priv->mutex);
  5596. if (ret)
  5597. goto out_release_irq;
  5598. IWL_DEBUG_INFO("Start UP work.\n");
  5599. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5600. return 0;
  5601. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5602. * mac80211 will not be run successfully. */
  5603. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5604. test_bit(STATUS_READY, &priv->status),
  5605. UCODE_READY_TIMEOUT);
  5606. if (!ret) {
  5607. if (!test_bit(STATUS_READY, &priv->status)) {
  5608. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5609. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5610. ret = -ETIMEDOUT;
  5611. goto out_release_irq;
  5612. }
  5613. }
  5614. priv->is_open = 1;
  5615. IWL_DEBUG_MAC80211("leave\n");
  5616. return 0;
  5617. out_release_irq:
  5618. free_irq(priv->pci_dev->irq, priv);
  5619. out_disable_msi:
  5620. pci_disable_msi(priv->pci_dev);
  5621. pci_disable_device(priv->pci_dev);
  5622. priv->is_open = 0;
  5623. IWL_DEBUG_MAC80211("leave - failed\n");
  5624. return ret;
  5625. }
  5626. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5627. {
  5628. struct iwl3945_priv *priv = hw->priv;
  5629. IWL_DEBUG_MAC80211("enter\n");
  5630. if (!priv->is_open) {
  5631. IWL_DEBUG_MAC80211("leave - skip\n");
  5632. return;
  5633. }
  5634. priv->is_open = 0;
  5635. if (iwl3945_is_ready_rf(priv)) {
  5636. /* stop mac, cancel any scan request and clear
  5637. * RXON_FILTER_ASSOC_MSK BIT
  5638. */
  5639. mutex_lock(&priv->mutex);
  5640. iwl3945_scan_cancel_timeout(priv, 100);
  5641. cancel_delayed_work(&priv->post_associate);
  5642. mutex_unlock(&priv->mutex);
  5643. }
  5644. iwl3945_down(priv);
  5645. flush_workqueue(priv->workqueue);
  5646. free_irq(priv->pci_dev->irq, priv);
  5647. pci_disable_msi(priv->pci_dev);
  5648. pci_save_state(priv->pci_dev);
  5649. pci_disable_device(priv->pci_dev);
  5650. IWL_DEBUG_MAC80211("leave\n");
  5651. }
  5652. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  5653. struct ieee80211_tx_control *ctl)
  5654. {
  5655. struct iwl3945_priv *priv = hw->priv;
  5656. IWL_DEBUG_MAC80211("enter\n");
  5657. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5658. IWL_DEBUG_MAC80211("leave - monitor\n");
  5659. return -1;
  5660. }
  5661. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5662. ctl->tx_rate->bitrate);
  5663. if (iwl3945_tx_skb(priv, skb, ctl))
  5664. dev_kfree_skb_any(skb);
  5665. IWL_DEBUG_MAC80211("leave\n");
  5666. return 0;
  5667. }
  5668. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5669. struct ieee80211_if_init_conf *conf)
  5670. {
  5671. struct iwl3945_priv *priv = hw->priv;
  5672. unsigned long flags;
  5673. DECLARE_MAC_BUF(mac);
  5674. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5675. if (priv->vif) {
  5676. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5677. return -EOPNOTSUPP;
  5678. }
  5679. spin_lock_irqsave(&priv->lock, flags);
  5680. priv->vif = conf->vif;
  5681. spin_unlock_irqrestore(&priv->lock, flags);
  5682. mutex_lock(&priv->mutex);
  5683. if (conf->mac_addr) {
  5684. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5685. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5686. }
  5687. if (iwl3945_is_ready(priv))
  5688. iwl3945_set_mode(priv, conf->type);
  5689. mutex_unlock(&priv->mutex);
  5690. IWL_DEBUG_MAC80211("leave\n");
  5691. return 0;
  5692. }
  5693. /**
  5694. * iwl3945_mac_config - mac80211 config callback
  5695. *
  5696. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5697. * be set inappropriately and the driver currently sets the hardware up to
  5698. * use it whenever needed.
  5699. */
  5700. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5701. {
  5702. struct iwl3945_priv *priv = hw->priv;
  5703. const struct iwl3945_channel_info *ch_info;
  5704. unsigned long flags;
  5705. int ret = 0;
  5706. mutex_lock(&priv->mutex);
  5707. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5708. priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  5709. if (!iwl3945_is_ready(priv)) {
  5710. IWL_DEBUG_MAC80211("leave - not ready\n");
  5711. ret = -EIO;
  5712. goto out;
  5713. }
  5714. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5715. test_bit(STATUS_SCANNING, &priv->status))) {
  5716. IWL_DEBUG_MAC80211("leave - scanning\n");
  5717. set_bit(STATUS_CONF_PENDING, &priv->status);
  5718. mutex_unlock(&priv->mutex);
  5719. return 0;
  5720. }
  5721. spin_lock_irqsave(&priv->lock, flags);
  5722. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5723. conf->channel->hw_value);
  5724. if (!is_channel_valid(ch_info)) {
  5725. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
  5726. conf->channel->hw_value, conf->channel->band);
  5727. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5728. spin_unlock_irqrestore(&priv->lock, flags);
  5729. ret = -EINVAL;
  5730. goto out;
  5731. }
  5732. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5733. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5734. /* The list of supported rates and rate mask can be different
  5735. * for each phymode; since the phymode may have changed, reset
  5736. * the rate mask to what mac80211 lists */
  5737. iwl3945_set_rate(priv);
  5738. spin_unlock_irqrestore(&priv->lock, flags);
  5739. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5740. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5741. iwl3945_hw_channel_switch(priv, conf->channel);
  5742. goto out;
  5743. }
  5744. #endif
  5745. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5746. if (!conf->radio_enabled) {
  5747. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5748. goto out;
  5749. }
  5750. if (iwl3945_is_rfkill(priv)) {
  5751. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5752. ret = -EIO;
  5753. goto out;
  5754. }
  5755. iwl3945_set_rate(priv);
  5756. if (memcmp(&priv->active_rxon,
  5757. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5758. iwl3945_commit_rxon(priv);
  5759. else
  5760. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5761. IWL_DEBUG_MAC80211("leave\n");
  5762. out:
  5763. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5764. mutex_unlock(&priv->mutex);
  5765. return ret;
  5766. }
  5767. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5768. {
  5769. int rc = 0;
  5770. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5771. return;
  5772. /* The following should be done only at AP bring up */
  5773. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  5774. /* RXON - unassoc (to set timing command) */
  5775. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5776. iwl3945_commit_rxon(priv);
  5777. /* RXON Timing */
  5778. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5779. iwl3945_setup_rxon_timing(priv);
  5780. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5781. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5782. if (rc)
  5783. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5784. "Attempting to continue.\n");
  5785. /* FIXME: what should be the assoc_id for AP? */
  5786. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5787. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5788. priv->staging_rxon.flags |=
  5789. RXON_FLG_SHORT_PREAMBLE_MSK;
  5790. else
  5791. priv->staging_rxon.flags &=
  5792. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5793. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5794. if (priv->assoc_capability &
  5795. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5796. priv->staging_rxon.flags |=
  5797. RXON_FLG_SHORT_SLOT_MSK;
  5798. else
  5799. priv->staging_rxon.flags &=
  5800. ~RXON_FLG_SHORT_SLOT_MSK;
  5801. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5802. priv->staging_rxon.flags &=
  5803. ~RXON_FLG_SHORT_SLOT_MSK;
  5804. }
  5805. /* restore RXON assoc */
  5806. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5807. iwl3945_commit_rxon(priv);
  5808. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5809. }
  5810. iwl3945_send_beacon_cmd(priv);
  5811. /* FIXME - we need to add code here to detect a totally new
  5812. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5813. * clear sta table, add BCAST sta... */
  5814. }
  5815. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5816. struct ieee80211_vif *vif,
  5817. struct ieee80211_if_conf *conf)
  5818. {
  5819. struct iwl3945_priv *priv = hw->priv;
  5820. DECLARE_MAC_BUF(mac);
  5821. unsigned long flags;
  5822. int rc;
  5823. if (conf == NULL)
  5824. return -EIO;
  5825. /* XXX: this MUST use conf->mac_addr */
  5826. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5827. (!conf->beacon || !conf->ssid_len)) {
  5828. IWL_DEBUG_MAC80211
  5829. ("Leaving in AP mode because HostAPD is not ready.\n");
  5830. return 0;
  5831. }
  5832. if (!iwl3945_is_alive(priv))
  5833. return -EAGAIN;
  5834. mutex_lock(&priv->mutex);
  5835. if (conf->bssid)
  5836. IWL_DEBUG_MAC80211("bssid: %s\n",
  5837. print_mac(mac, conf->bssid));
  5838. /*
  5839. * very dubious code was here; the probe filtering flag is never set:
  5840. *
  5841. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5842. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5843. */
  5844. if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
  5845. IWL_DEBUG_MAC80211("leave - scanning\n");
  5846. mutex_unlock(&priv->mutex);
  5847. return 0;
  5848. }
  5849. if (priv->vif != vif) {
  5850. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5851. mutex_unlock(&priv->mutex);
  5852. return 0;
  5853. }
  5854. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5855. if (!conf->bssid) {
  5856. conf->bssid = priv->mac_addr;
  5857. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5858. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5859. print_mac(mac, conf->bssid));
  5860. }
  5861. if (priv->ibss_beacon)
  5862. dev_kfree_skb(priv->ibss_beacon);
  5863. priv->ibss_beacon = conf->beacon;
  5864. }
  5865. if (iwl3945_is_rfkill(priv))
  5866. goto done;
  5867. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5868. !is_multicast_ether_addr(conf->bssid)) {
  5869. /* If there is currently a HW scan going on in the background
  5870. * then we need to cancel it else the RXON below will fail. */
  5871. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5872. IWL_WARNING("Aborted scan still in progress "
  5873. "after 100ms\n");
  5874. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5875. mutex_unlock(&priv->mutex);
  5876. return -EAGAIN;
  5877. }
  5878. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5879. /* TODO: Audit driver for usage of these members and see
  5880. * if mac80211 deprecates them (priv->bssid looks like it
  5881. * shouldn't be there, but I haven't scanned the IBSS code
  5882. * to verify) - jpk */
  5883. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5884. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5885. iwl3945_config_ap(priv);
  5886. else {
  5887. rc = iwl3945_commit_rxon(priv);
  5888. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  5889. iwl3945_add_station(priv,
  5890. priv->active_rxon.bssid_addr, 1, 0);
  5891. }
  5892. } else {
  5893. iwl3945_scan_cancel_timeout(priv, 100);
  5894. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5895. iwl3945_commit_rxon(priv);
  5896. }
  5897. done:
  5898. spin_lock_irqsave(&priv->lock, flags);
  5899. if (!conf->ssid_len)
  5900. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5901. else
  5902. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  5903. priv->essid_len = conf->ssid_len;
  5904. spin_unlock_irqrestore(&priv->lock, flags);
  5905. IWL_DEBUG_MAC80211("leave\n");
  5906. mutex_unlock(&priv->mutex);
  5907. return 0;
  5908. }
  5909. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5910. unsigned int changed_flags,
  5911. unsigned int *total_flags,
  5912. int mc_count, struct dev_addr_list *mc_list)
  5913. {
  5914. /*
  5915. * XXX: dummy
  5916. * see also iwl3945_connection_init_rx_config
  5917. */
  5918. *total_flags = 0;
  5919. }
  5920. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5921. struct ieee80211_if_init_conf *conf)
  5922. {
  5923. struct iwl3945_priv *priv = hw->priv;
  5924. IWL_DEBUG_MAC80211("enter\n");
  5925. mutex_lock(&priv->mutex);
  5926. if (iwl3945_is_ready_rf(priv)) {
  5927. iwl3945_scan_cancel_timeout(priv, 100);
  5928. cancel_delayed_work(&priv->post_associate);
  5929. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5930. iwl3945_commit_rxon(priv);
  5931. }
  5932. if (priv->vif == conf->vif) {
  5933. priv->vif = NULL;
  5934. memset(priv->bssid, 0, ETH_ALEN);
  5935. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5936. priv->essid_len = 0;
  5937. }
  5938. mutex_unlock(&priv->mutex);
  5939. IWL_DEBUG_MAC80211("leave\n");
  5940. }
  5941. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5942. {
  5943. int rc = 0;
  5944. unsigned long flags;
  5945. struct iwl3945_priv *priv = hw->priv;
  5946. IWL_DEBUG_MAC80211("enter\n");
  5947. mutex_lock(&priv->mutex);
  5948. spin_lock_irqsave(&priv->lock, flags);
  5949. if (!iwl3945_is_ready_rf(priv)) {
  5950. rc = -EIO;
  5951. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5952. goto out_unlock;
  5953. }
  5954. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  5955. rc = -EIO;
  5956. IWL_ERROR("ERROR: APs don't scan\n");
  5957. goto out_unlock;
  5958. }
  5959. /* we don't schedule scan within next_scan_jiffies period */
  5960. if (priv->next_scan_jiffies &&
  5961. time_after(priv->next_scan_jiffies, jiffies)) {
  5962. rc = -EAGAIN;
  5963. goto out_unlock;
  5964. }
  5965. /* if we just finished scan ask for delay */
  5966. if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
  5967. IWL_DELAY_NEXT_SCAN, jiffies)) {
  5968. rc = -EAGAIN;
  5969. goto out_unlock;
  5970. }
  5971. if (len) {
  5972. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5973. iwl3945_escape_essid(ssid, len), (int)len);
  5974. priv->one_direct_scan = 1;
  5975. priv->direct_ssid_len = (u8)
  5976. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5977. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5978. } else
  5979. priv->one_direct_scan = 0;
  5980. rc = iwl3945_scan_initiate(priv);
  5981. IWL_DEBUG_MAC80211("leave\n");
  5982. out_unlock:
  5983. spin_unlock_irqrestore(&priv->lock, flags);
  5984. mutex_unlock(&priv->mutex);
  5985. return rc;
  5986. }
  5987. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5988. const u8 *local_addr, const u8 *addr,
  5989. struct ieee80211_key_conf *key)
  5990. {
  5991. struct iwl3945_priv *priv = hw->priv;
  5992. int rc = 0;
  5993. u8 sta_id;
  5994. IWL_DEBUG_MAC80211("enter\n");
  5995. if (!iwl3945_param_hwcrypto) {
  5996. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5997. return -EOPNOTSUPP;
  5998. }
  5999. if (is_zero_ether_addr(addr))
  6000. /* only support pairwise keys */
  6001. return -EOPNOTSUPP;
  6002. sta_id = iwl3945_hw_find_station(priv, addr);
  6003. if (sta_id == IWL_INVALID_STATION) {
  6004. DECLARE_MAC_BUF(mac);
  6005. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  6006. print_mac(mac, addr));
  6007. return -EINVAL;
  6008. }
  6009. mutex_lock(&priv->mutex);
  6010. iwl3945_scan_cancel_timeout(priv, 100);
  6011. switch (cmd) {
  6012. case SET_KEY:
  6013. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  6014. if (!rc) {
  6015. iwl3945_set_rxon_hwcrypto(priv, 1);
  6016. iwl3945_commit_rxon(priv);
  6017. key->hw_key_idx = sta_id;
  6018. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  6019. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  6020. }
  6021. break;
  6022. case DISABLE_KEY:
  6023. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  6024. if (!rc) {
  6025. iwl3945_set_rxon_hwcrypto(priv, 0);
  6026. iwl3945_commit_rxon(priv);
  6027. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  6028. }
  6029. break;
  6030. default:
  6031. rc = -EINVAL;
  6032. }
  6033. IWL_DEBUG_MAC80211("leave\n");
  6034. mutex_unlock(&priv->mutex);
  6035. return rc;
  6036. }
  6037. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
  6038. const struct ieee80211_tx_queue_params *params)
  6039. {
  6040. struct iwl3945_priv *priv = hw->priv;
  6041. unsigned long flags;
  6042. int q;
  6043. IWL_DEBUG_MAC80211("enter\n");
  6044. if (!iwl3945_is_ready_rf(priv)) {
  6045. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6046. return -EIO;
  6047. }
  6048. if (queue >= AC_NUM) {
  6049. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  6050. return 0;
  6051. }
  6052. if (!priv->qos_data.qos_enable) {
  6053. priv->qos_data.qos_active = 0;
  6054. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  6055. return 0;
  6056. }
  6057. q = AC_NUM - 1 - queue;
  6058. spin_lock_irqsave(&priv->lock, flags);
  6059. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  6060. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  6061. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  6062. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  6063. cpu_to_le16((params->txop * 32));
  6064. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  6065. priv->qos_data.qos_active = 1;
  6066. spin_unlock_irqrestore(&priv->lock, flags);
  6067. mutex_lock(&priv->mutex);
  6068. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6069. iwl3945_activate_qos(priv, 1);
  6070. else if (priv->assoc_id && iwl3945_is_associated(priv))
  6071. iwl3945_activate_qos(priv, 0);
  6072. mutex_unlock(&priv->mutex);
  6073. IWL_DEBUG_MAC80211("leave\n");
  6074. return 0;
  6075. }
  6076. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  6077. struct ieee80211_tx_queue_stats *stats)
  6078. {
  6079. struct iwl3945_priv *priv = hw->priv;
  6080. int i, avail;
  6081. struct iwl3945_tx_queue *txq;
  6082. struct iwl3945_queue *q;
  6083. unsigned long flags;
  6084. IWL_DEBUG_MAC80211("enter\n");
  6085. if (!iwl3945_is_ready_rf(priv)) {
  6086. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6087. return -EIO;
  6088. }
  6089. spin_lock_irqsave(&priv->lock, flags);
  6090. for (i = 0; i < AC_NUM; i++) {
  6091. txq = &priv->txq[i];
  6092. q = &txq->q;
  6093. avail = iwl3945_queue_space(q);
  6094. stats->data[i].len = q->n_window - avail;
  6095. stats->data[i].limit = q->n_window - q->high_mark;
  6096. stats->data[i].count = q->n_window;
  6097. }
  6098. spin_unlock_irqrestore(&priv->lock, flags);
  6099. IWL_DEBUG_MAC80211("leave\n");
  6100. return 0;
  6101. }
  6102. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6103. struct ieee80211_low_level_stats *stats)
  6104. {
  6105. IWL_DEBUG_MAC80211("enter\n");
  6106. IWL_DEBUG_MAC80211("leave\n");
  6107. return 0;
  6108. }
  6109. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6110. {
  6111. IWL_DEBUG_MAC80211("enter\n");
  6112. IWL_DEBUG_MAC80211("leave\n");
  6113. return 0;
  6114. }
  6115. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6116. {
  6117. struct iwl3945_priv *priv = hw->priv;
  6118. unsigned long flags;
  6119. mutex_lock(&priv->mutex);
  6120. IWL_DEBUG_MAC80211("enter\n");
  6121. iwl3945_reset_qos(priv);
  6122. cancel_delayed_work(&priv->post_associate);
  6123. spin_lock_irqsave(&priv->lock, flags);
  6124. priv->assoc_id = 0;
  6125. priv->assoc_capability = 0;
  6126. priv->call_post_assoc_from_beacon = 0;
  6127. /* new association get rid of ibss beacon skb */
  6128. if (priv->ibss_beacon)
  6129. dev_kfree_skb(priv->ibss_beacon);
  6130. priv->ibss_beacon = NULL;
  6131. priv->beacon_int = priv->hw->conf.beacon_int;
  6132. priv->timestamp1 = 0;
  6133. priv->timestamp0 = 0;
  6134. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6135. priv->beacon_int = 0;
  6136. spin_unlock_irqrestore(&priv->lock, flags);
  6137. if (!iwl3945_is_ready_rf(priv)) {
  6138. IWL_DEBUG_MAC80211("leave - not ready\n");
  6139. mutex_unlock(&priv->mutex);
  6140. return;
  6141. }
  6142. /* we are restarting association process
  6143. * clear RXON_FILTER_ASSOC_MSK bit
  6144. */
  6145. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6146. iwl3945_scan_cancel_timeout(priv, 100);
  6147. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6148. iwl3945_commit_rxon(priv);
  6149. }
  6150. /* Per mac80211.h: This is only used in IBSS mode... */
  6151. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6152. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6153. mutex_unlock(&priv->mutex);
  6154. return;
  6155. }
  6156. priv->only_active_channel = 0;
  6157. iwl3945_set_rate(priv);
  6158. mutex_unlock(&priv->mutex);
  6159. IWL_DEBUG_MAC80211("leave\n");
  6160. }
  6161. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  6162. struct ieee80211_tx_control *control)
  6163. {
  6164. struct iwl3945_priv *priv = hw->priv;
  6165. unsigned long flags;
  6166. mutex_lock(&priv->mutex);
  6167. IWL_DEBUG_MAC80211("enter\n");
  6168. if (!iwl3945_is_ready_rf(priv)) {
  6169. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6170. mutex_unlock(&priv->mutex);
  6171. return -EIO;
  6172. }
  6173. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6174. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6175. mutex_unlock(&priv->mutex);
  6176. return -EIO;
  6177. }
  6178. spin_lock_irqsave(&priv->lock, flags);
  6179. if (priv->ibss_beacon)
  6180. dev_kfree_skb(priv->ibss_beacon);
  6181. priv->ibss_beacon = skb;
  6182. priv->assoc_id = 0;
  6183. IWL_DEBUG_MAC80211("leave\n");
  6184. spin_unlock_irqrestore(&priv->lock, flags);
  6185. iwl3945_reset_qos(priv);
  6186. queue_work(priv->workqueue, &priv->post_associate.work);
  6187. mutex_unlock(&priv->mutex);
  6188. return 0;
  6189. }
  6190. /*****************************************************************************
  6191. *
  6192. * sysfs attributes
  6193. *
  6194. *****************************************************************************/
  6195. #ifdef CONFIG_IWL3945_DEBUG
  6196. /*
  6197. * The following adds a new attribute to the sysfs representation
  6198. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6199. * used for controlling the debug level.
  6200. *
  6201. * See the level definitions in iwl for details.
  6202. */
  6203. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6204. {
  6205. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6206. }
  6207. static ssize_t store_debug_level(struct device_driver *d,
  6208. const char *buf, size_t count)
  6209. {
  6210. char *p = (char *)buf;
  6211. u32 val;
  6212. val = simple_strtoul(p, &p, 0);
  6213. if (p == buf)
  6214. printk(KERN_INFO DRV_NAME
  6215. ": %s is not in hex or decimal form.\n", buf);
  6216. else
  6217. iwl3945_debug_level = val;
  6218. return strnlen(buf, count);
  6219. }
  6220. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6221. show_debug_level, store_debug_level);
  6222. #endif /* CONFIG_IWL3945_DEBUG */
  6223. static ssize_t show_rf_kill(struct device *d,
  6224. struct device_attribute *attr, char *buf)
  6225. {
  6226. /*
  6227. * 0 - RF kill not enabled
  6228. * 1 - SW based RF kill active (sysfs)
  6229. * 2 - HW based RF kill active
  6230. * 3 - Both HW and SW based RF kill active
  6231. */
  6232. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6233. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  6234. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  6235. return sprintf(buf, "%i\n", val);
  6236. }
  6237. static ssize_t store_rf_kill(struct device *d,
  6238. struct device_attribute *attr,
  6239. const char *buf, size_t count)
  6240. {
  6241. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6242. mutex_lock(&priv->mutex);
  6243. iwl3945_radio_kill_sw(priv, buf[0] == '1');
  6244. mutex_unlock(&priv->mutex);
  6245. return count;
  6246. }
  6247. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  6248. static ssize_t show_temperature(struct device *d,
  6249. struct device_attribute *attr, char *buf)
  6250. {
  6251. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6252. if (!iwl3945_is_alive(priv))
  6253. return -EAGAIN;
  6254. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6255. }
  6256. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6257. static ssize_t show_rs_window(struct device *d,
  6258. struct device_attribute *attr,
  6259. char *buf)
  6260. {
  6261. struct iwl3945_priv *priv = d->driver_data;
  6262. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6263. }
  6264. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6265. static ssize_t show_tx_power(struct device *d,
  6266. struct device_attribute *attr, char *buf)
  6267. {
  6268. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6269. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6270. }
  6271. static ssize_t store_tx_power(struct device *d,
  6272. struct device_attribute *attr,
  6273. const char *buf, size_t count)
  6274. {
  6275. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6276. char *p = (char *)buf;
  6277. u32 val;
  6278. val = simple_strtoul(p, &p, 10);
  6279. if (p == buf)
  6280. printk(KERN_INFO DRV_NAME
  6281. ": %s is not in decimal form.\n", buf);
  6282. else
  6283. iwl3945_hw_reg_set_txpower(priv, val);
  6284. return count;
  6285. }
  6286. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6287. static ssize_t show_flags(struct device *d,
  6288. struct device_attribute *attr, char *buf)
  6289. {
  6290. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6291. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6292. }
  6293. static ssize_t store_flags(struct device *d,
  6294. struct device_attribute *attr,
  6295. const char *buf, size_t count)
  6296. {
  6297. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6298. u32 flags = simple_strtoul(buf, NULL, 0);
  6299. mutex_lock(&priv->mutex);
  6300. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6301. /* Cancel any currently running scans... */
  6302. if (iwl3945_scan_cancel_timeout(priv, 100))
  6303. IWL_WARNING("Could not cancel scan.\n");
  6304. else {
  6305. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6306. flags);
  6307. priv->staging_rxon.flags = cpu_to_le32(flags);
  6308. iwl3945_commit_rxon(priv);
  6309. }
  6310. }
  6311. mutex_unlock(&priv->mutex);
  6312. return count;
  6313. }
  6314. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6315. static ssize_t show_filter_flags(struct device *d,
  6316. struct device_attribute *attr, char *buf)
  6317. {
  6318. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6319. return sprintf(buf, "0x%04X\n",
  6320. le32_to_cpu(priv->active_rxon.filter_flags));
  6321. }
  6322. static ssize_t store_filter_flags(struct device *d,
  6323. struct device_attribute *attr,
  6324. const char *buf, size_t count)
  6325. {
  6326. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6327. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6328. mutex_lock(&priv->mutex);
  6329. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6330. /* Cancel any currently running scans... */
  6331. if (iwl3945_scan_cancel_timeout(priv, 100))
  6332. IWL_WARNING("Could not cancel scan.\n");
  6333. else {
  6334. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6335. "0x%04X\n", filter_flags);
  6336. priv->staging_rxon.filter_flags =
  6337. cpu_to_le32(filter_flags);
  6338. iwl3945_commit_rxon(priv);
  6339. }
  6340. }
  6341. mutex_unlock(&priv->mutex);
  6342. return count;
  6343. }
  6344. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6345. store_filter_flags);
  6346. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6347. static ssize_t show_measurement(struct device *d,
  6348. struct device_attribute *attr, char *buf)
  6349. {
  6350. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6351. struct iwl3945_spectrum_notification measure_report;
  6352. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6353. u8 *data = (u8 *) & measure_report;
  6354. unsigned long flags;
  6355. spin_lock_irqsave(&priv->lock, flags);
  6356. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6357. spin_unlock_irqrestore(&priv->lock, flags);
  6358. return 0;
  6359. }
  6360. memcpy(&measure_report, &priv->measure_report, size);
  6361. priv->measurement_status = 0;
  6362. spin_unlock_irqrestore(&priv->lock, flags);
  6363. while (size && (PAGE_SIZE - len)) {
  6364. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6365. PAGE_SIZE - len, 1);
  6366. len = strlen(buf);
  6367. if (PAGE_SIZE - len)
  6368. buf[len++] = '\n';
  6369. ofs += 16;
  6370. size -= min(size, 16U);
  6371. }
  6372. return len;
  6373. }
  6374. static ssize_t store_measurement(struct device *d,
  6375. struct device_attribute *attr,
  6376. const char *buf, size_t count)
  6377. {
  6378. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6379. struct ieee80211_measurement_params params = {
  6380. .channel = le16_to_cpu(priv->active_rxon.channel),
  6381. .start_time = cpu_to_le64(priv->last_tsf),
  6382. .duration = cpu_to_le16(1),
  6383. };
  6384. u8 type = IWL_MEASURE_BASIC;
  6385. u8 buffer[32];
  6386. u8 channel;
  6387. if (count) {
  6388. char *p = buffer;
  6389. strncpy(buffer, buf, min(sizeof(buffer), count));
  6390. channel = simple_strtoul(p, NULL, 0);
  6391. if (channel)
  6392. params.channel = channel;
  6393. p = buffer;
  6394. while (*p && *p != ' ')
  6395. p++;
  6396. if (*p)
  6397. type = simple_strtoul(p + 1, NULL, 0);
  6398. }
  6399. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6400. "channel %d (for '%s')\n", type, params.channel, buf);
  6401. iwl3945_get_measurement(priv, &params, type);
  6402. return count;
  6403. }
  6404. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6405. show_measurement, store_measurement);
  6406. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6407. static ssize_t store_retry_rate(struct device *d,
  6408. struct device_attribute *attr,
  6409. const char *buf, size_t count)
  6410. {
  6411. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6412. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6413. if (priv->retry_rate <= 0)
  6414. priv->retry_rate = 1;
  6415. return count;
  6416. }
  6417. static ssize_t show_retry_rate(struct device *d,
  6418. struct device_attribute *attr, char *buf)
  6419. {
  6420. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6421. return sprintf(buf, "%d", priv->retry_rate);
  6422. }
  6423. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6424. store_retry_rate);
  6425. static ssize_t store_power_level(struct device *d,
  6426. struct device_attribute *attr,
  6427. const char *buf, size_t count)
  6428. {
  6429. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6430. int rc;
  6431. int mode;
  6432. mode = simple_strtoul(buf, NULL, 0);
  6433. mutex_lock(&priv->mutex);
  6434. if (!iwl3945_is_ready(priv)) {
  6435. rc = -EAGAIN;
  6436. goto out;
  6437. }
  6438. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6439. mode = IWL_POWER_AC;
  6440. else
  6441. mode |= IWL_POWER_ENABLED;
  6442. if (mode != priv->power_mode) {
  6443. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6444. if (rc) {
  6445. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6446. goto out;
  6447. }
  6448. priv->power_mode = mode;
  6449. }
  6450. rc = count;
  6451. out:
  6452. mutex_unlock(&priv->mutex);
  6453. return rc;
  6454. }
  6455. #define MAX_WX_STRING 80
  6456. /* Values are in microsecond */
  6457. static const s32 timeout_duration[] = {
  6458. 350000,
  6459. 250000,
  6460. 75000,
  6461. 37000,
  6462. 25000,
  6463. };
  6464. static const s32 period_duration[] = {
  6465. 400000,
  6466. 700000,
  6467. 1000000,
  6468. 1000000,
  6469. 1000000
  6470. };
  6471. static ssize_t show_power_level(struct device *d,
  6472. struct device_attribute *attr, char *buf)
  6473. {
  6474. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6475. int level = IWL_POWER_LEVEL(priv->power_mode);
  6476. char *p = buf;
  6477. p += sprintf(p, "%d ", level);
  6478. switch (level) {
  6479. case IWL_POWER_MODE_CAM:
  6480. case IWL_POWER_AC:
  6481. p += sprintf(p, "(AC)");
  6482. break;
  6483. case IWL_POWER_BATTERY:
  6484. p += sprintf(p, "(BATTERY)");
  6485. break;
  6486. default:
  6487. p += sprintf(p,
  6488. "(Timeout %dms, Period %dms)",
  6489. timeout_duration[level - 1] / 1000,
  6490. period_duration[level - 1] / 1000);
  6491. }
  6492. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6493. p += sprintf(p, " OFF\n");
  6494. else
  6495. p += sprintf(p, " \n");
  6496. return (p - buf + 1);
  6497. }
  6498. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6499. store_power_level);
  6500. static ssize_t show_channels(struct device *d,
  6501. struct device_attribute *attr, char *buf)
  6502. {
  6503. /* all this shit doesn't belong into sysfs anyway */
  6504. return 0;
  6505. }
  6506. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6507. static ssize_t show_statistics(struct device *d,
  6508. struct device_attribute *attr, char *buf)
  6509. {
  6510. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6511. u32 size = sizeof(struct iwl3945_notif_statistics);
  6512. u32 len = 0, ofs = 0;
  6513. u8 *data = (u8 *) & priv->statistics;
  6514. int rc = 0;
  6515. if (!iwl3945_is_alive(priv))
  6516. return -EAGAIN;
  6517. mutex_lock(&priv->mutex);
  6518. rc = iwl3945_send_statistics_request(priv);
  6519. mutex_unlock(&priv->mutex);
  6520. if (rc) {
  6521. len = sprintf(buf,
  6522. "Error sending statistics request: 0x%08X\n", rc);
  6523. return len;
  6524. }
  6525. while (size && (PAGE_SIZE - len)) {
  6526. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6527. PAGE_SIZE - len, 1);
  6528. len = strlen(buf);
  6529. if (PAGE_SIZE - len)
  6530. buf[len++] = '\n';
  6531. ofs += 16;
  6532. size -= min(size, 16U);
  6533. }
  6534. return len;
  6535. }
  6536. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6537. static ssize_t show_antenna(struct device *d,
  6538. struct device_attribute *attr, char *buf)
  6539. {
  6540. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6541. if (!iwl3945_is_alive(priv))
  6542. return -EAGAIN;
  6543. return sprintf(buf, "%d\n", priv->antenna);
  6544. }
  6545. static ssize_t store_antenna(struct device *d,
  6546. struct device_attribute *attr,
  6547. const char *buf, size_t count)
  6548. {
  6549. int ant;
  6550. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6551. if (count == 0)
  6552. return 0;
  6553. if (sscanf(buf, "%1i", &ant) != 1) {
  6554. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6555. return count;
  6556. }
  6557. if ((ant >= 0) && (ant <= 2)) {
  6558. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6559. priv->antenna = (enum iwl3945_antenna)ant;
  6560. } else
  6561. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6562. return count;
  6563. }
  6564. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6565. static ssize_t show_status(struct device *d,
  6566. struct device_attribute *attr, char *buf)
  6567. {
  6568. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6569. if (!iwl3945_is_alive(priv))
  6570. return -EAGAIN;
  6571. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6572. }
  6573. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6574. static ssize_t dump_error_log(struct device *d,
  6575. struct device_attribute *attr,
  6576. const char *buf, size_t count)
  6577. {
  6578. char *p = (char *)buf;
  6579. if (p[0] == '1')
  6580. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6581. return strnlen(buf, count);
  6582. }
  6583. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6584. static ssize_t dump_event_log(struct device *d,
  6585. struct device_attribute *attr,
  6586. const char *buf, size_t count)
  6587. {
  6588. char *p = (char *)buf;
  6589. if (p[0] == '1')
  6590. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6591. return strnlen(buf, count);
  6592. }
  6593. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6594. /*****************************************************************************
  6595. *
  6596. * driver setup and teardown
  6597. *
  6598. *****************************************************************************/
  6599. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6600. {
  6601. priv->workqueue = create_workqueue(DRV_NAME);
  6602. init_waitqueue_head(&priv->wait_command_queue);
  6603. INIT_WORK(&priv->up, iwl3945_bg_up);
  6604. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6605. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6606. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6607. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6608. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6609. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6610. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6611. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6612. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6613. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6614. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6615. iwl3945_hw_setup_deferred_work(priv);
  6616. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6617. iwl3945_irq_tasklet, (unsigned long)priv);
  6618. }
  6619. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6620. {
  6621. iwl3945_hw_cancel_deferred_work(priv);
  6622. cancel_delayed_work_sync(&priv->init_alive_start);
  6623. cancel_delayed_work(&priv->scan_check);
  6624. cancel_delayed_work(&priv->alive_start);
  6625. cancel_delayed_work(&priv->post_associate);
  6626. cancel_work_sync(&priv->beacon_update);
  6627. }
  6628. static struct attribute *iwl3945_sysfs_entries[] = {
  6629. &dev_attr_antenna.attr,
  6630. &dev_attr_channels.attr,
  6631. &dev_attr_dump_errors.attr,
  6632. &dev_attr_dump_events.attr,
  6633. &dev_attr_flags.attr,
  6634. &dev_attr_filter_flags.attr,
  6635. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6636. &dev_attr_measurement.attr,
  6637. #endif
  6638. &dev_attr_power_level.attr,
  6639. &dev_attr_retry_rate.attr,
  6640. &dev_attr_rf_kill.attr,
  6641. &dev_attr_rs_window.attr,
  6642. &dev_attr_statistics.attr,
  6643. &dev_attr_status.attr,
  6644. &dev_attr_temperature.attr,
  6645. &dev_attr_tx_power.attr,
  6646. NULL
  6647. };
  6648. static struct attribute_group iwl3945_attribute_group = {
  6649. .name = NULL, /* put in device directory */
  6650. .attrs = iwl3945_sysfs_entries,
  6651. };
  6652. static struct ieee80211_ops iwl3945_hw_ops = {
  6653. .tx = iwl3945_mac_tx,
  6654. .start = iwl3945_mac_start,
  6655. .stop = iwl3945_mac_stop,
  6656. .add_interface = iwl3945_mac_add_interface,
  6657. .remove_interface = iwl3945_mac_remove_interface,
  6658. .config = iwl3945_mac_config,
  6659. .config_interface = iwl3945_mac_config_interface,
  6660. .configure_filter = iwl3945_configure_filter,
  6661. .set_key = iwl3945_mac_set_key,
  6662. .get_stats = iwl3945_mac_get_stats,
  6663. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6664. .conf_tx = iwl3945_mac_conf_tx,
  6665. .get_tsf = iwl3945_mac_get_tsf,
  6666. .reset_tsf = iwl3945_mac_reset_tsf,
  6667. .beacon_update = iwl3945_mac_beacon_update,
  6668. .hw_scan = iwl3945_mac_hw_scan
  6669. };
  6670. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6671. {
  6672. int err = 0;
  6673. u32 pci_id;
  6674. struct iwl3945_priv *priv;
  6675. struct ieee80211_hw *hw;
  6676. int i;
  6677. DECLARE_MAC_BUF(mac);
  6678. /* Disabling hardware scan means that mac80211 will perform scans
  6679. * "the hard way", rather than using device's scan. */
  6680. if (iwl3945_param_disable_hw_scan) {
  6681. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6682. iwl3945_hw_ops.hw_scan = NULL;
  6683. }
  6684. if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
  6685. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6686. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6687. IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
  6688. err = -EINVAL;
  6689. goto out;
  6690. }
  6691. /* mac80211 allocates memory for this device instance, including
  6692. * space for this driver's private structure */
  6693. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6694. if (hw == NULL) {
  6695. IWL_ERROR("Can not allocate network device\n");
  6696. err = -ENOMEM;
  6697. goto out;
  6698. }
  6699. SET_IEEE80211_DEV(hw, &pdev->dev);
  6700. hw->rate_control_algorithm = "iwl-3945-rs";
  6701. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6702. priv = hw->priv;
  6703. priv->hw = hw;
  6704. priv->pci_dev = pdev;
  6705. /* Select antenna (may be helpful if only one antenna is connected) */
  6706. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6707. #ifdef CONFIG_IWL3945_DEBUG
  6708. iwl3945_debug_level = iwl3945_param_debug;
  6709. atomic_set(&priv->restrict_refcnt, 0);
  6710. #endif
  6711. priv->retry_rate = 1;
  6712. priv->ibss_beacon = NULL;
  6713. /* Tell mac80211 and its clients (e.g. Wireless Extensions)
  6714. * the range of signal quality values that we'll provide.
  6715. * Negative values for level/noise indicate that we'll provide dBm.
  6716. * For WE, at least, non-0 values here *enable* display of values
  6717. * in app (iwconfig). */
  6718. hw->max_rssi = -20; /* signal level, negative indicates dBm */
  6719. hw->max_noise = -20; /* noise level, negative indicates dBm */
  6720. hw->max_signal = 100; /* link quality indication (%) */
  6721. /* Tell mac80211 our Tx characteristics */
  6722. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
  6723. /* 4 EDCA QOS priorities */
  6724. hw->queues = 4;
  6725. spin_lock_init(&priv->lock);
  6726. spin_lock_init(&priv->power_data.lock);
  6727. spin_lock_init(&priv->sta_lock);
  6728. spin_lock_init(&priv->hcmd_lock);
  6729. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  6730. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  6731. INIT_LIST_HEAD(&priv->free_frames);
  6732. mutex_init(&priv->mutex);
  6733. if (pci_enable_device(pdev)) {
  6734. err = -ENODEV;
  6735. goto out_ieee80211_free_hw;
  6736. }
  6737. pci_set_master(pdev);
  6738. /* Clear the driver's (not device's) station table */
  6739. iwl3945_clear_stations_table(priv);
  6740. priv->data_retry_limit = -1;
  6741. priv->ieee_channels = NULL;
  6742. priv->ieee_rates = NULL;
  6743. priv->band = IEEE80211_BAND_2GHZ;
  6744. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6745. if (!err)
  6746. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6747. if (err) {
  6748. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6749. goto out_pci_disable_device;
  6750. }
  6751. pci_set_drvdata(pdev, priv);
  6752. err = pci_request_regions(pdev, DRV_NAME);
  6753. if (err)
  6754. goto out_pci_disable_device;
  6755. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6756. * PCI Tx retries from interfering with C3 CPU state */
  6757. pci_write_config_byte(pdev, 0x41, 0x00);
  6758. priv->hw_base = pci_iomap(pdev, 0, 0);
  6759. if (!priv->hw_base) {
  6760. err = -ENODEV;
  6761. goto out_pci_release_regions;
  6762. }
  6763. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6764. (unsigned long long) pci_resource_len(pdev, 0));
  6765. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6766. /* Initialize module parameter values here */
  6767. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6768. if (iwl3945_param_disable) {
  6769. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6770. IWL_DEBUG_INFO("Radio disabled.\n");
  6771. }
  6772. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6773. pci_id =
  6774. (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device;
  6775. switch (pci_id) {
  6776. case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */
  6777. case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */
  6778. case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */
  6779. case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */
  6780. priv->is_abg = 0;
  6781. break;
  6782. /*
  6783. * Rest are assumed ABG SKU -- if this is not the
  6784. * case then the card will get the wrong 'Detected'
  6785. * line in the kernel log however the code that
  6786. * initializes the GEO table will detect no A-band
  6787. * channels and remove the is_abg mask.
  6788. */
  6789. default:
  6790. priv->is_abg = 1;
  6791. break;
  6792. }
  6793. printk(KERN_INFO DRV_NAME
  6794. ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n",
  6795. priv->is_abg ? "A" : "");
  6796. /* Device-specific setup */
  6797. if (iwl3945_hw_set_hw_setting(priv)) {
  6798. IWL_ERROR("failed to set hw settings\n");
  6799. goto out_iounmap;
  6800. }
  6801. if (iwl3945_param_qos_enable)
  6802. priv->qos_data.qos_enable = 1;
  6803. iwl3945_reset_qos(priv);
  6804. priv->qos_data.qos_active = 0;
  6805. priv->qos_data.qos_cap.val = 0;
  6806. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6807. iwl3945_setup_deferred_work(priv);
  6808. iwl3945_setup_rx_handlers(priv);
  6809. priv->rates_mask = IWL_RATES_MASK;
  6810. /* If power management is turned on, default to AC mode */
  6811. priv->power_mode = IWL_POWER_AC;
  6812. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6813. iwl3945_disable_interrupts(priv);
  6814. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6815. if (err) {
  6816. IWL_ERROR("failed to create sysfs device attributes\n");
  6817. goto out_release_irq;
  6818. }
  6819. /* nic init */
  6820. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6821. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6822. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6823. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6824. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6825. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6826. if (err < 0) {
  6827. IWL_DEBUG_INFO("Failed to init the card\n");
  6828. goto out_remove_sysfs;
  6829. }
  6830. /* Read the EEPROM */
  6831. err = iwl3945_eeprom_init(priv);
  6832. if (err) {
  6833. IWL_ERROR("Unable to init EEPROM\n");
  6834. goto out_remove_sysfs;
  6835. }
  6836. /* MAC Address location in EEPROM same for 3945/4965 */
  6837. get_eeprom_mac(priv, priv->mac_addr);
  6838. IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
  6839. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6840. err = iwl3945_init_channel_map(priv);
  6841. if (err) {
  6842. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6843. goto out_remove_sysfs;
  6844. }
  6845. err = iwl3945_init_geos(priv);
  6846. if (err) {
  6847. IWL_ERROR("initializing geos failed: %d\n", err);
  6848. goto out_free_channel_map;
  6849. }
  6850. iwl3945_rate_control_register(priv->hw);
  6851. err = ieee80211_register_hw(priv->hw);
  6852. if (err) {
  6853. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6854. goto out_free_geos;
  6855. }
  6856. priv->hw->conf.beacon_int = 100;
  6857. priv->mac80211_registered = 1;
  6858. pci_save_state(pdev);
  6859. pci_disable_device(pdev);
  6860. return 0;
  6861. out_free_geos:
  6862. iwl3945_free_geos(priv);
  6863. out_free_channel_map:
  6864. iwl3945_free_channel_map(priv);
  6865. out_remove_sysfs:
  6866. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6867. out_release_irq:
  6868. destroy_workqueue(priv->workqueue);
  6869. priv->workqueue = NULL;
  6870. iwl3945_unset_hw_setting(priv);
  6871. out_iounmap:
  6872. pci_iounmap(pdev, priv->hw_base);
  6873. out_pci_release_regions:
  6874. pci_release_regions(pdev);
  6875. out_pci_disable_device:
  6876. pci_disable_device(pdev);
  6877. pci_set_drvdata(pdev, NULL);
  6878. out_ieee80211_free_hw:
  6879. ieee80211_free_hw(priv->hw);
  6880. out:
  6881. return err;
  6882. }
  6883. static void iwl3945_pci_remove(struct pci_dev *pdev)
  6884. {
  6885. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6886. struct list_head *p, *q;
  6887. int i;
  6888. if (!priv)
  6889. return;
  6890. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6891. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6892. iwl3945_down(priv);
  6893. /* Free MAC hash list for ADHOC */
  6894. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  6895. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  6896. list_del(p);
  6897. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  6898. }
  6899. }
  6900. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6901. iwl3945_dealloc_ucode_pci(priv);
  6902. if (priv->rxq.bd)
  6903. iwl3945_rx_queue_free(priv, &priv->rxq);
  6904. iwl3945_hw_txq_ctx_free(priv);
  6905. iwl3945_unset_hw_setting(priv);
  6906. iwl3945_clear_stations_table(priv);
  6907. if (priv->mac80211_registered) {
  6908. ieee80211_unregister_hw(priv->hw);
  6909. iwl3945_rate_control_unregister(priv->hw);
  6910. }
  6911. /*netif_stop_queue(dev); */
  6912. flush_workqueue(priv->workqueue);
  6913. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6914. * priv->workqueue... so we can't take down the workqueue
  6915. * until now... */
  6916. destroy_workqueue(priv->workqueue);
  6917. priv->workqueue = NULL;
  6918. pci_iounmap(pdev, priv->hw_base);
  6919. pci_release_regions(pdev);
  6920. pci_disable_device(pdev);
  6921. pci_set_drvdata(pdev, NULL);
  6922. iwl3945_free_channel_map(priv);
  6923. iwl3945_free_geos(priv);
  6924. if (priv->ibss_beacon)
  6925. dev_kfree_skb(priv->ibss_beacon);
  6926. ieee80211_free_hw(priv->hw);
  6927. }
  6928. #ifdef CONFIG_PM
  6929. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6930. {
  6931. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6932. if (priv->is_open) {
  6933. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6934. iwl3945_mac_stop(priv->hw);
  6935. priv->is_open = 1;
  6936. }
  6937. pci_set_power_state(pdev, PCI_D3hot);
  6938. return 0;
  6939. }
  6940. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6941. {
  6942. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6943. pci_set_power_state(pdev, PCI_D0);
  6944. if (priv->is_open)
  6945. iwl3945_mac_start(priv->hw);
  6946. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6947. return 0;
  6948. }
  6949. #endif /* CONFIG_PM */
  6950. /*****************************************************************************
  6951. *
  6952. * driver and module entry point
  6953. *
  6954. *****************************************************************************/
  6955. static struct pci_driver iwl3945_driver = {
  6956. .name = DRV_NAME,
  6957. .id_table = iwl3945_hw_card_ids,
  6958. .probe = iwl3945_pci_probe,
  6959. .remove = __devexit_p(iwl3945_pci_remove),
  6960. #ifdef CONFIG_PM
  6961. .suspend = iwl3945_pci_suspend,
  6962. .resume = iwl3945_pci_resume,
  6963. #endif
  6964. };
  6965. static int __init iwl3945_init(void)
  6966. {
  6967. int ret;
  6968. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6969. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6970. ret = pci_register_driver(&iwl3945_driver);
  6971. if (ret) {
  6972. IWL_ERROR("Unable to initialize PCI module\n");
  6973. return ret;
  6974. }
  6975. #ifdef CONFIG_IWL3945_DEBUG
  6976. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6977. if (ret) {
  6978. IWL_ERROR("Unable to create driver sysfs file\n");
  6979. pci_unregister_driver(&iwl3945_driver);
  6980. return ret;
  6981. }
  6982. #endif
  6983. return ret;
  6984. }
  6985. static void __exit iwl3945_exit(void)
  6986. {
  6987. #ifdef CONFIG_IWL3945_DEBUG
  6988. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6989. #endif
  6990. pci_unregister_driver(&iwl3945_driver);
  6991. }
  6992. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6993. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6994. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6995. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6996. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6997. MODULE_PARM_DESC(hwcrypto,
  6998. "using hardware crypto engine (default 0 [software])\n");
  6999. module_param_named(debug, iwl3945_param_debug, int, 0444);
  7000. MODULE_PARM_DESC(debug, "debug output mask");
  7001. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  7002. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  7003. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  7004. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  7005. /* QoS */
  7006. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  7007. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  7008. module_exit(iwl3945_exit);
  7009. module_init(iwl3945_init);