rt2x00queue.c 23 KB

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  1. /*
  2. Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2x00lib
  19. Abstract: rt2x00 queue specific routines.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/dma-mapping.h>
  24. #include "rt2x00.h"
  25. #include "rt2x00lib.h"
  26. struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
  27. struct queue_entry *entry)
  28. {
  29. struct sk_buff *skb;
  30. struct skb_frame_desc *skbdesc;
  31. unsigned int frame_size;
  32. unsigned int head_size = 0;
  33. unsigned int tail_size = 0;
  34. /*
  35. * The frame size includes descriptor size, because the
  36. * hardware directly receive the frame into the skbuffer.
  37. */
  38. frame_size = entry->queue->data_size + entry->queue->desc_size;
  39. /*
  40. * The payload should be aligned to a 4-byte boundary,
  41. * this means we need at least 3 bytes for moving the frame
  42. * into the correct offset.
  43. */
  44. head_size = 4;
  45. /*
  46. * For IV/EIV/ICV assembly we must make sure there is
  47. * at least 8 bytes bytes available in headroom for IV/EIV
  48. * and 8 bytes for ICV data as tailroon.
  49. */
  50. if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
  51. head_size += 8;
  52. tail_size += 8;
  53. }
  54. /*
  55. * Allocate skbuffer.
  56. */
  57. skb = dev_alloc_skb(frame_size + head_size + tail_size);
  58. if (!skb)
  59. return NULL;
  60. /*
  61. * Make sure we not have a frame with the requested bytes
  62. * available in the head and tail.
  63. */
  64. skb_reserve(skb, head_size);
  65. skb_put(skb, frame_size);
  66. /*
  67. * Populate skbdesc.
  68. */
  69. skbdesc = get_skb_frame_desc(skb);
  70. memset(skbdesc, 0, sizeof(*skbdesc));
  71. skbdesc->entry = entry;
  72. if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
  73. skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
  74. skb->data,
  75. skb->len,
  76. DMA_FROM_DEVICE);
  77. skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
  78. }
  79. return skb;
  80. }
  81. void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  82. {
  83. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  84. /*
  85. * If device has requested headroom, we should make sure that
  86. * is also mapped to the DMA so it can be used for transfering
  87. * additional descriptor information to the hardware.
  88. */
  89. skb_push(skb, rt2x00dev->hw->extra_tx_headroom);
  90. skbdesc->skb_dma =
  91. dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
  92. /*
  93. * Restore data pointer to original location again.
  94. */
  95. skb_pull(skb, rt2x00dev->hw->extra_tx_headroom);
  96. skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
  97. }
  98. EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
  99. void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  100. {
  101. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  102. if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
  103. dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
  104. DMA_FROM_DEVICE);
  105. skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
  106. }
  107. if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
  108. /*
  109. * Add headroom to the skb length, it has been removed
  110. * by the driver, but it was actually mapped to DMA.
  111. */
  112. dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma,
  113. skb->len + rt2x00dev->hw->extra_tx_headroom,
  114. DMA_TO_DEVICE);
  115. skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
  116. }
  117. }
  118. void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  119. {
  120. if (!skb)
  121. return;
  122. rt2x00queue_unmap_skb(rt2x00dev, skb);
  123. dev_kfree_skb_any(skb);
  124. }
  125. void rt2x00queue_payload_align(struct sk_buff *skb,
  126. bool l2pad, unsigned int header_length)
  127. {
  128. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  129. unsigned int frame_length = skb->len;
  130. unsigned int align = ALIGN_SIZE(skb, header_length);
  131. if (!align)
  132. return;
  133. if (l2pad) {
  134. if (skbdesc->flags & SKBDESC_L2_PADDED) {
  135. /* Remove L2 padding */
  136. memmove(skb->data + align, skb->data, header_length);
  137. skb_pull(skb, align);
  138. skbdesc->flags &= ~SKBDESC_L2_PADDED;
  139. } else {
  140. /* Add L2 padding */
  141. skb_push(skb, align);
  142. memmove(skb->data, skb->data + align, header_length);
  143. skbdesc->flags |= SKBDESC_L2_PADDED;
  144. }
  145. } else {
  146. /* Generic payload alignment to 4-byte boundary */
  147. skb_push(skb, align);
  148. memmove(skb->data, skb->data + align, frame_length);
  149. }
  150. }
  151. static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
  152. struct txentry_desc *txdesc)
  153. {
  154. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
  155. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
  156. struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
  157. unsigned long irqflags;
  158. if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ||
  159. unlikely(!tx_info->control.vif))
  160. return;
  161. /*
  162. * Hardware should insert sequence counter.
  163. * FIXME: We insert a software sequence counter first for
  164. * hardware that doesn't support hardware sequence counting.
  165. *
  166. * This is wrong because beacons are not getting sequence
  167. * numbers assigned properly.
  168. *
  169. * A secondary problem exists for drivers that cannot toggle
  170. * sequence counting per-frame, since those will override the
  171. * sequence counter given by mac80211.
  172. */
  173. spin_lock_irqsave(&intf->seqlock, irqflags);
  174. if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
  175. intf->seqno += 0x10;
  176. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  177. hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
  178. spin_unlock_irqrestore(&intf->seqlock, irqflags);
  179. __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
  180. }
  181. static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
  182. struct txentry_desc *txdesc,
  183. const struct rt2x00_rate *hwrate)
  184. {
  185. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  186. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
  187. struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
  188. unsigned int data_length;
  189. unsigned int duration;
  190. unsigned int residual;
  191. /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
  192. data_length = entry->skb->len + 4;
  193. data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
  194. /*
  195. * PLCP setup
  196. * Length calculation depends on OFDM/CCK rate.
  197. */
  198. txdesc->signal = hwrate->plcp;
  199. txdesc->service = 0x04;
  200. if (hwrate->flags & DEV_RATE_OFDM) {
  201. txdesc->length_high = (data_length >> 6) & 0x3f;
  202. txdesc->length_low = data_length & 0x3f;
  203. } else {
  204. /*
  205. * Convert length to microseconds.
  206. */
  207. residual = GET_DURATION_RES(data_length, hwrate->bitrate);
  208. duration = GET_DURATION(data_length, hwrate->bitrate);
  209. if (residual != 0) {
  210. duration++;
  211. /*
  212. * Check if we need to set the Length Extension
  213. */
  214. if (hwrate->bitrate == 110 && residual <= 30)
  215. txdesc->service |= 0x80;
  216. }
  217. txdesc->length_high = (duration >> 8) & 0xff;
  218. txdesc->length_low = duration & 0xff;
  219. /*
  220. * When preamble is enabled we should set the
  221. * preamble bit for the signal.
  222. */
  223. if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
  224. txdesc->signal |= 0x08;
  225. }
  226. }
  227. static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
  228. struct txentry_desc *txdesc)
  229. {
  230. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  231. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
  232. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
  233. struct ieee80211_rate *rate =
  234. ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
  235. const struct rt2x00_rate *hwrate;
  236. memset(txdesc, 0, sizeof(*txdesc));
  237. /*
  238. * Initialize information from queue
  239. */
  240. txdesc->queue = entry->queue->qid;
  241. txdesc->cw_min = entry->queue->cw_min;
  242. txdesc->cw_max = entry->queue->cw_max;
  243. txdesc->aifs = entry->queue->aifs;
  244. /*
  245. * Header and alignment information.
  246. */
  247. txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
  248. txdesc->l2pad = ALIGN_SIZE(entry->skb, txdesc->header_length);
  249. /*
  250. * Check whether this frame is to be acked.
  251. */
  252. if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
  253. __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
  254. /*
  255. * Check if this is a RTS/CTS frame
  256. */
  257. if (ieee80211_is_rts(hdr->frame_control) ||
  258. ieee80211_is_cts(hdr->frame_control)) {
  259. __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
  260. if (ieee80211_is_rts(hdr->frame_control))
  261. __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
  262. else
  263. __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
  264. if (tx_info->control.rts_cts_rate_idx >= 0)
  265. rate =
  266. ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
  267. }
  268. /*
  269. * Determine retry information.
  270. */
  271. txdesc->retry_limit = tx_info->control.rates[0].count - 1;
  272. if (txdesc->retry_limit >= rt2x00dev->long_retry)
  273. __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
  274. /*
  275. * Check if more fragments are pending
  276. */
  277. if (ieee80211_has_morefrags(hdr->frame_control) ||
  278. (tx_info->flags & IEEE80211_TX_CTL_MORE_FRAMES)) {
  279. __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
  280. __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
  281. }
  282. /*
  283. * Beacons and probe responses require the tsf timestamp
  284. * to be inserted into the frame.
  285. */
  286. if (ieee80211_is_beacon(hdr->frame_control) ||
  287. ieee80211_is_probe_resp(hdr->frame_control))
  288. __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
  289. /*
  290. * Determine with what IFS priority this frame should be send.
  291. * Set ifs to IFS_SIFS when the this is not the first fragment,
  292. * or this fragment came after RTS/CTS.
  293. */
  294. if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
  295. !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
  296. __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
  297. txdesc->ifs = IFS_BACKOFF;
  298. } else
  299. txdesc->ifs = IFS_SIFS;
  300. /*
  301. * Determine rate modulation.
  302. */
  303. hwrate = rt2x00_get_rate(rate->hw_value);
  304. txdesc->rate_mode = RATE_MODE_CCK;
  305. if (hwrate->flags & DEV_RATE_OFDM)
  306. txdesc->rate_mode = RATE_MODE_OFDM;
  307. /*
  308. * Apply TX descriptor handling by components
  309. */
  310. rt2x00crypto_create_tx_descriptor(entry, txdesc);
  311. rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
  312. rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
  313. rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
  314. }
  315. static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
  316. struct txentry_desc *txdesc)
  317. {
  318. struct data_queue *queue = entry->queue;
  319. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  320. rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
  321. /*
  322. * All processing on the frame has been completed, this means
  323. * it is now ready to be dumped to userspace through debugfs.
  324. */
  325. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
  326. /*
  327. * Check if we need to kick the queue, there are however a few rules
  328. * 1) Don't kick beacon queue
  329. * 2) Don't kick unless this is the last in frame in a burst.
  330. * When the burst flag is set, this frame is always followed
  331. * by another frame which in some way are related to eachother.
  332. * This is true for fragments, RTS or CTS-to-self frames.
  333. * 3) Rule 2 can be broken when the available entries
  334. * in the queue are less then a certain threshold.
  335. */
  336. if (entry->queue->qid == QID_BEACON)
  337. return;
  338. if (rt2x00queue_threshold(queue) ||
  339. !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
  340. rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
  341. }
  342. int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
  343. {
  344. struct ieee80211_tx_info *tx_info;
  345. struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
  346. struct txentry_desc txdesc;
  347. struct skb_frame_desc *skbdesc;
  348. u8 rate_idx, rate_flags;
  349. if (unlikely(rt2x00queue_full(queue)))
  350. return -ENOBUFS;
  351. if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
  352. ERROR(queue->rt2x00dev,
  353. "Arrived at non-free entry in the non-full queue %d.\n"
  354. "Please file bug report to %s.\n",
  355. queue->qid, DRV_PROJECT);
  356. return -EINVAL;
  357. }
  358. /*
  359. * Copy all TX descriptor information into txdesc,
  360. * after that we are free to use the skb->cb array
  361. * for our information.
  362. */
  363. entry->skb = skb;
  364. rt2x00queue_create_tx_descriptor(entry, &txdesc);
  365. /*
  366. * All information is retrieved from the skb->cb array,
  367. * now we should claim ownership of the driver part of that
  368. * array, preserving the bitrate index and flags.
  369. */
  370. tx_info = IEEE80211_SKB_CB(skb);
  371. rate_idx = tx_info->control.rates[0].idx;
  372. rate_flags = tx_info->control.rates[0].flags;
  373. skbdesc = get_skb_frame_desc(skb);
  374. memset(skbdesc, 0, sizeof(*skbdesc));
  375. skbdesc->entry = entry;
  376. skbdesc->tx_rate_idx = rate_idx;
  377. skbdesc->tx_rate_flags = rate_flags;
  378. /*
  379. * When hardware encryption is supported, and this frame
  380. * is to be encrypted, we should strip the IV/EIV data from
  381. * the frame so we can provide it to the driver seperately.
  382. */
  383. if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
  384. !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
  385. if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
  386. rt2x00crypto_tx_copy_iv(skb, &txdesc);
  387. else
  388. rt2x00crypto_tx_remove_iv(skb, &txdesc);
  389. }
  390. /*
  391. * When DMA allocation is required we should guarentee to the
  392. * driver that the DMA is aligned to a 4-byte boundary.
  393. * Aligning the header to this boundary can be done by calling
  394. * rt2x00queue_payload_align with the header length of 0.
  395. * However some drivers require L2 padding to pad the payload
  396. * rather then the header. This could be a requirement for
  397. * PCI and USB devices, while header alignment only is valid
  398. * for PCI devices.
  399. */
  400. if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags))
  401. rt2x00queue_payload_align(entry->skb, true,
  402. txdesc.header_length);
  403. else if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
  404. rt2x00queue_payload_align(entry->skb, false, 0);
  405. /*
  406. * It could be possible that the queue was corrupted and this
  407. * call failed. Since we always return NETDEV_TX_OK to mac80211,
  408. * this frame will simply be dropped.
  409. */
  410. if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
  411. clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
  412. entry->skb = NULL;
  413. return -EIO;
  414. }
  415. if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
  416. rt2x00queue_map_txskb(queue->rt2x00dev, skb);
  417. set_bit(ENTRY_DATA_PENDING, &entry->flags);
  418. rt2x00queue_index_inc(queue, Q_INDEX);
  419. rt2x00queue_write_tx_descriptor(entry, &txdesc);
  420. return 0;
  421. }
  422. int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
  423. struct ieee80211_vif *vif,
  424. const bool enable_beacon)
  425. {
  426. struct rt2x00_intf *intf = vif_to_intf(vif);
  427. struct skb_frame_desc *skbdesc;
  428. struct txentry_desc txdesc;
  429. __le32 desc[16];
  430. if (unlikely(!intf->beacon))
  431. return -ENOBUFS;
  432. mutex_lock(&intf->beacon_skb_mutex);
  433. /*
  434. * Clean up the beacon skb.
  435. */
  436. rt2x00queue_free_skb(rt2x00dev, intf->beacon->skb);
  437. intf->beacon->skb = NULL;
  438. if (!enable_beacon) {
  439. rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, QID_BEACON);
  440. mutex_unlock(&intf->beacon_skb_mutex);
  441. return 0;
  442. }
  443. intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
  444. if (!intf->beacon->skb) {
  445. mutex_unlock(&intf->beacon_skb_mutex);
  446. return -ENOMEM;
  447. }
  448. /*
  449. * Copy all TX descriptor information into txdesc,
  450. * after that we are free to use the skb->cb array
  451. * for our information.
  452. */
  453. rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
  454. /*
  455. * For the descriptor we use a local array from where the
  456. * driver can move it to the correct location required for
  457. * the hardware.
  458. */
  459. memset(desc, 0, sizeof(desc));
  460. /*
  461. * Fill in skb descriptor
  462. */
  463. skbdesc = get_skb_frame_desc(intf->beacon->skb);
  464. memset(skbdesc, 0, sizeof(*skbdesc));
  465. skbdesc->desc = desc;
  466. skbdesc->desc_len = intf->beacon->queue->desc_size;
  467. skbdesc->entry = intf->beacon;
  468. /*
  469. * Write TX descriptor into reserved room in front of the beacon.
  470. */
  471. rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
  472. /*
  473. * Send beacon to hardware.
  474. * Also enable beacon generation, which might have been disabled
  475. * by the driver during the config_beacon() callback function.
  476. */
  477. rt2x00dev->ops->lib->write_beacon(intf->beacon);
  478. rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
  479. mutex_unlock(&intf->beacon_skb_mutex);
  480. return 0;
  481. }
  482. struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
  483. const enum data_queue_qid queue)
  484. {
  485. int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
  486. if (queue == QID_RX)
  487. return rt2x00dev->rx;
  488. if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
  489. return &rt2x00dev->tx[queue];
  490. if (!rt2x00dev->bcn)
  491. return NULL;
  492. if (queue == QID_BEACON)
  493. return &rt2x00dev->bcn[0];
  494. else if (queue == QID_ATIM && atim)
  495. return &rt2x00dev->bcn[1];
  496. return NULL;
  497. }
  498. EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
  499. struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
  500. enum queue_index index)
  501. {
  502. struct queue_entry *entry;
  503. unsigned long irqflags;
  504. if (unlikely(index >= Q_INDEX_MAX)) {
  505. ERROR(queue->rt2x00dev,
  506. "Entry requested from invalid index type (%d)\n", index);
  507. return NULL;
  508. }
  509. spin_lock_irqsave(&queue->lock, irqflags);
  510. entry = &queue->entries[queue->index[index]];
  511. spin_unlock_irqrestore(&queue->lock, irqflags);
  512. return entry;
  513. }
  514. EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
  515. void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
  516. {
  517. unsigned long irqflags;
  518. if (unlikely(index >= Q_INDEX_MAX)) {
  519. ERROR(queue->rt2x00dev,
  520. "Index change on invalid index type (%d)\n", index);
  521. return;
  522. }
  523. spin_lock_irqsave(&queue->lock, irqflags);
  524. queue->index[index]++;
  525. if (queue->index[index] >= queue->limit)
  526. queue->index[index] = 0;
  527. if (index == Q_INDEX) {
  528. queue->length++;
  529. } else if (index == Q_INDEX_DONE) {
  530. queue->length--;
  531. queue->count++;
  532. }
  533. spin_unlock_irqrestore(&queue->lock, irqflags);
  534. }
  535. static void rt2x00queue_reset(struct data_queue *queue)
  536. {
  537. unsigned long irqflags;
  538. spin_lock_irqsave(&queue->lock, irqflags);
  539. queue->count = 0;
  540. queue->length = 0;
  541. memset(queue->index, 0, sizeof(queue->index));
  542. spin_unlock_irqrestore(&queue->lock, irqflags);
  543. }
  544. void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
  545. {
  546. struct data_queue *queue;
  547. txall_queue_for_each(rt2x00dev, queue)
  548. rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev, queue->qid);
  549. }
  550. void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
  551. {
  552. struct data_queue *queue;
  553. unsigned int i;
  554. queue_for_each(rt2x00dev, queue) {
  555. rt2x00queue_reset(queue);
  556. for (i = 0; i < queue->limit; i++) {
  557. queue->entries[i].flags = 0;
  558. rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
  559. }
  560. }
  561. }
  562. static int rt2x00queue_alloc_entries(struct data_queue *queue,
  563. const struct data_queue_desc *qdesc)
  564. {
  565. struct queue_entry *entries;
  566. unsigned int entry_size;
  567. unsigned int i;
  568. rt2x00queue_reset(queue);
  569. queue->limit = qdesc->entry_num;
  570. queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
  571. queue->data_size = qdesc->data_size;
  572. queue->desc_size = qdesc->desc_size;
  573. /*
  574. * Allocate all queue entries.
  575. */
  576. entry_size = sizeof(*entries) + qdesc->priv_size;
  577. entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
  578. if (!entries)
  579. return -ENOMEM;
  580. #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
  581. ( ((char *)(__base)) + ((__limit) * (__esize)) + \
  582. ((__index) * (__psize)) )
  583. for (i = 0; i < queue->limit; i++) {
  584. entries[i].flags = 0;
  585. entries[i].queue = queue;
  586. entries[i].skb = NULL;
  587. entries[i].entry_idx = i;
  588. entries[i].priv_data =
  589. QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
  590. sizeof(*entries), qdesc->priv_size);
  591. }
  592. #undef QUEUE_ENTRY_PRIV_OFFSET
  593. queue->entries = entries;
  594. return 0;
  595. }
  596. static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
  597. struct data_queue *queue)
  598. {
  599. unsigned int i;
  600. if (!queue->entries)
  601. return;
  602. for (i = 0; i < queue->limit; i++) {
  603. if (queue->entries[i].skb)
  604. rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
  605. }
  606. }
  607. static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
  608. struct data_queue *queue)
  609. {
  610. unsigned int i;
  611. struct sk_buff *skb;
  612. for (i = 0; i < queue->limit; i++) {
  613. skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
  614. if (!skb)
  615. return -ENOMEM;
  616. queue->entries[i].skb = skb;
  617. }
  618. return 0;
  619. }
  620. int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
  621. {
  622. struct data_queue *queue;
  623. int status;
  624. status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
  625. if (status)
  626. goto exit;
  627. tx_queue_for_each(rt2x00dev, queue) {
  628. status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
  629. if (status)
  630. goto exit;
  631. }
  632. status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
  633. if (status)
  634. goto exit;
  635. if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
  636. status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
  637. rt2x00dev->ops->atim);
  638. if (status)
  639. goto exit;
  640. }
  641. status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
  642. if (status)
  643. goto exit;
  644. return 0;
  645. exit:
  646. ERROR(rt2x00dev, "Queue entries allocation failed.\n");
  647. rt2x00queue_uninitialize(rt2x00dev);
  648. return status;
  649. }
  650. void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
  651. {
  652. struct data_queue *queue;
  653. rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
  654. queue_for_each(rt2x00dev, queue) {
  655. kfree(queue->entries);
  656. queue->entries = NULL;
  657. }
  658. }
  659. static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
  660. struct data_queue *queue, enum data_queue_qid qid)
  661. {
  662. spin_lock_init(&queue->lock);
  663. queue->rt2x00dev = rt2x00dev;
  664. queue->qid = qid;
  665. queue->txop = 0;
  666. queue->aifs = 2;
  667. queue->cw_min = 5;
  668. queue->cw_max = 10;
  669. }
  670. int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
  671. {
  672. struct data_queue *queue;
  673. enum data_queue_qid qid;
  674. unsigned int req_atim =
  675. !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
  676. /*
  677. * We need the following queues:
  678. * RX: 1
  679. * TX: ops->tx_queues
  680. * Beacon: 1
  681. * Atim: 1 (if required)
  682. */
  683. rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
  684. queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
  685. if (!queue) {
  686. ERROR(rt2x00dev, "Queue allocation failed.\n");
  687. return -ENOMEM;
  688. }
  689. /*
  690. * Initialize pointers
  691. */
  692. rt2x00dev->rx = queue;
  693. rt2x00dev->tx = &queue[1];
  694. rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
  695. /*
  696. * Initialize queue parameters.
  697. * RX: qid = QID_RX
  698. * TX: qid = QID_AC_BE + index
  699. * TX: cw_min: 2^5 = 32.
  700. * TX: cw_max: 2^10 = 1024.
  701. * BCN: qid = QID_BEACON
  702. * ATIM: qid = QID_ATIM
  703. */
  704. rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
  705. qid = QID_AC_BE;
  706. tx_queue_for_each(rt2x00dev, queue)
  707. rt2x00queue_init(rt2x00dev, queue, qid++);
  708. rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
  709. if (req_atim)
  710. rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
  711. return 0;
  712. }
  713. void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
  714. {
  715. kfree(rt2x00dev->rx);
  716. rt2x00dev->rx = NULL;
  717. rt2x00dev->tx = NULL;
  718. rt2x00dev->bcn = NULL;
  719. }