tilcdc_drv.c 15 KB

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  1. /*
  2. * Copyright (C) 2012 Texas Instruments
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. /* LCDC DRM driver, based on da8xx-fb */
  18. #include "tilcdc_drv.h"
  19. #include "tilcdc_regs.h"
  20. #include "tilcdc_tfp410.h"
  21. #include "drm_fb_helper.h"
  22. static LIST_HEAD(module_list);
  23. void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
  24. const struct tilcdc_module_ops *funcs)
  25. {
  26. mod->name = name;
  27. mod->funcs = funcs;
  28. INIT_LIST_HEAD(&mod->list);
  29. list_add(&mod->list, &module_list);
  30. }
  31. void tilcdc_module_cleanup(struct tilcdc_module *mod)
  32. {
  33. list_del(&mod->list);
  34. }
  35. static struct of_device_id tilcdc_of_match[];
  36. static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
  37. struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd)
  38. {
  39. return drm_fb_cma_create(dev, file_priv, mode_cmd);
  40. }
  41. static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
  42. {
  43. struct tilcdc_drm_private *priv = dev->dev_private;
  44. if (priv->fbdev)
  45. drm_fbdev_cma_hotplug_event(priv->fbdev);
  46. }
  47. static const struct drm_mode_config_funcs mode_config_funcs = {
  48. .fb_create = tilcdc_fb_create,
  49. .output_poll_changed = tilcdc_fb_output_poll_changed,
  50. };
  51. static int modeset_init(struct drm_device *dev)
  52. {
  53. struct tilcdc_drm_private *priv = dev->dev_private;
  54. struct tilcdc_module *mod;
  55. drm_mode_config_init(dev);
  56. priv->crtc = tilcdc_crtc_create(dev);
  57. list_for_each_entry(mod, &module_list, list) {
  58. DBG("loading module: %s", mod->name);
  59. mod->funcs->modeset_init(mod, dev);
  60. }
  61. if ((priv->num_encoders = 0) || (priv->num_connectors == 0)) {
  62. /* oh nos! */
  63. dev_err(dev->dev, "no encoders/connectors found\n");
  64. return -ENXIO;
  65. }
  66. dev->mode_config.min_width = 0;
  67. dev->mode_config.min_height = 0;
  68. dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
  69. dev->mode_config.max_height = 2048;
  70. dev->mode_config.funcs = &mode_config_funcs;
  71. return 0;
  72. }
  73. #ifdef CONFIG_CPU_FREQ
  74. static int cpufreq_transition(struct notifier_block *nb,
  75. unsigned long val, void *data)
  76. {
  77. struct tilcdc_drm_private *priv = container_of(nb,
  78. struct tilcdc_drm_private, freq_transition);
  79. if (val == CPUFREQ_POSTCHANGE) {
  80. if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
  81. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  82. tilcdc_crtc_update_clk(priv->crtc);
  83. }
  84. }
  85. return 0;
  86. }
  87. #endif
  88. /*
  89. * DRM operations:
  90. */
  91. static int tilcdc_unload(struct drm_device *dev)
  92. {
  93. struct tilcdc_drm_private *priv = dev->dev_private;
  94. struct tilcdc_module *mod, *cur;
  95. drm_kms_helper_poll_fini(dev);
  96. drm_mode_config_cleanup(dev);
  97. drm_vblank_cleanup(dev);
  98. pm_runtime_get_sync(dev->dev);
  99. drm_irq_uninstall(dev);
  100. pm_runtime_put_sync(dev->dev);
  101. #ifdef CONFIG_CPU_FREQ
  102. cpufreq_unregister_notifier(&priv->freq_transition,
  103. CPUFREQ_TRANSITION_NOTIFIER);
  104. #endif
  105. if (priv->clk)
  106. clk_put(priv->clk);
  107. if (priv->mmio)
  108. iounmap(priv->mmio);
  109. flush_workqueue(priv->wq);
  110. destroy_workqueue(priv->wq);
  111. dev->dev_private = NULL;
  112. pm_runtime_disable(dev->dev);
  113. list_for_each_entry_safe(mod, cur, &module_list, list) {
  114. DBG("destroying module: %s", mod->name);
  115. mod->funcs->destroy(mod);
  116. }
  117. kfree(priv);
  118. return 0;
  119. }
  120. static int tilcdc_load(struct drm_device *dev, unsigned long flags)
  121. {
  122. struct platform_device *pdev = dev->platformdev;
  123. struct device_node *node = pdev->dev.of_node;
  124. struct tilcdc_drm_private *priv;
  125. struct resource *res;
  126. int ret;
  127. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  128. if (!priv) {
  129. dev_err(dev->dev, "failed to allocate private data\n");
  130. return -ENOMEM;
  131. }
  132. dev->dev_private = priv;
  133. priv->wq = alloc_ordered_workqueue("tilcdc", 0);
  134. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  135. if (!res) {
  136. dev_err(dev->dev, "failed to get memory resource\n");
  137. ret = -EINVAL;
  138. goto fail;
  139. }
  140. priv->mmio = ioremap_nocache(res->start, resource_size(res));
  141. if (!priv->mmio) {
  142. dev_err(dev->dev, "failed to ioremap\n");
  143. ret = -ENOMEM;
  144. goto fail;
  145. }
  146. priv->clk = clk_get(dev->dev, "fck");
  147. if (IS_ERR(priv->clk)) {
  148. dev_err(dev->dev, "failed to get functional clock\n");
  149. ret = -ENODEV;
  150. goto fail;
  151. }
  152. priv->disp_clk = clk_get(dev->dev, "dpll_disp_ck");
  153. if (IS_ERR(priv->clk)) {
  154. dev_err(dev->dev, "failed to get display clock\n");
  155. ret = -ENODEV;
  156. goto fail;
  157. }
  158. #ifdef CONFIG_CPU_FREQ
  159. priv->lcd_fck_rate = clk_get_rate(priv->clk);
  160. priv->freq_transition.notifier_call = cpufreq_transition;
  161. ret = cpufreq_register_notifier(&priv->freq_transition,
  162. CPUFREQ_TRANSITION_NOTIFIER);
  163. if (ret) {
  164. dev_err(dev->dev, "failed to register cpufreq notifier\n");
  165. goto fail;
  166. }
  167. #endif
  168. if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
  169. priv->max_bandwidth = 1280 * 1024 * 60;
  170. pm_runtime_enable(dev->dev);
  171. /* Determine LCD IP Version */
  172. pm_runtime_get_sync(dev->dev);
  173. switch (tilcdc_read(dev, LCDC_PID_REG)) {
  174. case 0x4c100102:
  175. priv->rev = 1;
  176. break;
  177. case 0x4f200800:
  178. case 0x4f201000:
  179. priv->rev = 2;
  180. break;
  181. default:
  182. dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
  183. "defaulting to LCD revision 1\n",
  184. tilcdc_read(dev, LCDC_PID_REG));
  185. priv->rev = 1;
  186. break;
  187. }
  188. pm_runtime_put_sync(dev->dev);
  189. ret = modeset_init(dev);
  190. if (ret < 0) {
  191. dev_err(dev->dev, "failed to initialize mode setting\n");
  192. goto fail;
  193. }
  194. ret = drm_vblank_init(dev, 1);
  195. if (ret < 0) {
  196. dev_err(dev->dev, "failed to initialize vblank\n");
  197. goto fail;
  198. }
  199. pm_runtime_get_sync(dev->dev);
  200. ret = drm_irq_install(dev);
  201. pm_runtime_put_sync(dev->dev);
  202. if (ret < 0) {
  203. dev_err(dev->dev, "failed to install IRQ handler\n");
  204. goto fail;
  205. }
  206. platform_set_drvdata(pdev, dev);
  207. priv->fbdev = drm_fbdev_cma_init(dev, 16,
  208. dev->mode_config.num_crtc,
  209. dev->mode_config.num_connector);
  210. drm_kms_helper_poll_init(dev);
  211. return 0;
  212. fail:
  213. tilcdc_unload(dev);
  214. return ret;
  215. }
  216. static void tilcdc_preclose(struct drm_device *dev, struct drm_file *file)
  217. {
  218. struct tilcdc_drm_private *priv = dev->dev_private;
  219. tilcdc_crtc_cancel_page_flip(priv->crtc, file);
  220. }
  221. static void tilcdc_lastclose(struct drm_device *dev)
  222. {
  223. struct tilcdc_drm_private *priv = dev->dev_private;
  224. drm_fbdev_cma_restore_mode(priv->fbdev);
  225. }
  226. static irqreturn_t tilcdc_irq(DRM_IRQ_ARGS)
  227. {
  228. struct drm_device *dev = arg;
  229. struct tilcdc_drm_private *priv = dev->dev_private;
  230. return tilcdc_crtc_irq(priv->crtc);
  231. }
  232. static void tilcdc_irq_preinstall(struct drm_device *dev)
  233. {
  234. tilcdc_clear_irqstatus(dev, 0xffffffff);
  235. }
  236. static int tilcdc_irq_postinstall(struct drm_device *dev)
  237. {
  238. struct tilcdc_drm_private *priv = dev->dev_private;
  239. /* enable FIFO underflow irq: */
  240. if (priv->rev == 1) {
  241. tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA);
  242. } else {
  243. tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_UNDERFLOW_INT_ENA);
  244. }
  245. return 0;
  246. }
  247. static void tilcdc_irq_uninstall(struct drm_device *dev)
  248. {
  249. struct tilcdc_drm_private *priv = dev->dev_private;
  250. /* disable irqs that we might have enabled: */
  251. if (priv->rev == 1) {
  252. tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
  253. LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
  254. tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA);
  255. } else {
  256. tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG,
  257. LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
  258. LCDC_V2_END_OF_FRAME0_INT_ENA | LCDC_V2_END_OF_FRAME1_INT_ENA |
  259. LCDC_FRAME_DONE);
  260. }
  261. }
  262. static void enable_vblank(struct drm_device *dev, bool enable)
  263. {
  264. struct tilcdc_drm_private *priv = dev->dev_private;
  265. u32 reg, mask;
  266. if (priv->rev == 1) {
  267. reg = LCDC_DMA_CTRL_REG;
  268. mask = LCDC_V1_END_OF_FRAME_INT_ENA;
  269. } else {
  270. reg = LCDC_INT_ENABLE_SET_REG;
  271. mask = LCDC_V2_END_OF_FRAME0_INT_ENA |
  272. LCDC_V2_END_OF_FRAME1_INT_ENA | LCDC_FRAME_DONE;
  273. }
  274. if (enable)
  275. tilcdc_set(dev, reg, mask);
  276. else
  277. tilcdc_clear(dev, reg, mask);
  278. }
  279. static int tilcdc_enable_vblank(struct drm_device *dev, int crtc)
  280. {
  281. enable_vblank(dev, true);
  282. return 0;
  283. }
  284. static void tilcdc_disable_vblank(struct drm_device *dev, int crtc)
  285. {
  286. enable_vblank(dev, false);
  287. }
  288. #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP)
  289. static const struct {
  290. const char *name;
  291. uint8_t rev;
  292. uint8_t save;
  293. uint32_t reg;
  294. } registers[] = {
  295. #define REG(rev, save, reg) { #reg, rev, save, reg }
  296. /* exists in revision 1: */
  297. REG(1, false, LCDC_PID_REG),
  298. REG(1, true, LCDC_CTRL_REG),
  299. REG(1, false, LCDC_STAT_REG),
  300. REG(1, true, LCDC_RASTER_CTRL_REG),
  301. REG(1, true, LCDC_RASTER_TIMING_0_REG),
  302. REG(1, true, LCDC_RASTER_TIMING_1_REG),
  303. REG(1, true, LCDC_RASTER_TIMING_2_REG),
  304. REG(1, true, LCDC_DMA_CTRL_REG),
  305. REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
  306. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
  307. REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
  308. REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
  309. /* new in revision 2: */
  310. REG(2, false, LCDC_RAW_STAT_REG),
  311. REG(2, false, LCDC_MASKED_STAT_REG),
  312. REG(2, false, LCDC_INT_ENABLE_SET_REG),
  313. REG(2, false, LCDC_INT_ENABLE_CLR_REG),
  314. REG(2, false, LCDC_END_OF_INT_IND_REG),
  315. REG(2, true, LCDC_CLK_ENABLE_REG),
  316. REG(2, true, LCDC_INT_ENABLE_SET_REG),
  317. #undef REG
  318. };
  319. #endif
  320. #ifdef CONFIG_DEBUG_FS
  321. static int tilcdc_regs_show(struct seq_file *m, void *arg)
  322. {
  323. struct drm_info_node *node = (struct drm_info_node *) m->private;
  324. struct drm_device *dev = node->minor->dev;
  325. struct tilcdc_drm_private *priv = dev->dev_private;
  326. unsigned i;
  327. pm_runtime_get_sync(dev->dev);
  328. seq_printf(m, "revision: %d\n", priv->rev);
  329. for (i = 0; i < ARRAY_SIZE(registers); i++)
  330. if (priv->rev >= registers[i].rev)
  331. seq_printf(m, "%s:\t %08x\n", registers[i].name,
  332. tilcdc_read(dev, registers[i].reg));
  333. pm_runtime_put_sync(dev->dev);
  334. return 0;
  335. }
  336. static int tilcdc_mm_show(struct seq_file *m, void *arg)
  337. {
  338. struct drm_info_node *node = (struct drm_info_node *) m->private;
  339. struct drm_device *dev = node->minor->dev;
  340. return drm_mm_dump_table(m, dev->mm_private);
  341. }
  342. static struct drm_info_list tilcdc_debugfs_list[] = {
  343. { "regs", tilcdc_regs_show, 0 },
  344. { "mm", tilcdc_mm_show, 0 },
  345. { "fb", drm_fb_cma_debugfs_show, 0 },
  346. };
  347. static int tilcdc_debugfs_init(struct drm_minor *minor)
  348. {
  349. struct drm_device *dev = minor->dev;
  350. struct tilcdc_module *mod;
  351. int ret;
  352. ret = drm_debugfs_create_files(tilcdc_debugfs_list,
  353. ARRAY_SIZE(tilcdc_debugfs_list),
  354. minor->debugfs_root, minor);
  355. list_for_each_entry(mod, &module_list, list)
  356. if (mod->funcs->debugfs_init)
  357. mod->funcs->debugfs_init(mod, minor);
  358. if (ret) {
  359. dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
  360. return ret;
  361. }
  362. return ret;
  363. }
  364. static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
  365. {
  366. struct tilcdc_module *mod;
  367. drm_debugfs_remove_files(tilcdc_debugfs_list,
  368. ARRAY_SIZE(tilcdc_debugfs_list), minor);
  369. list_for_each_entry(mod, &module_list, list)
  370. if (mod->funcs->debugfs_cleanup)
  371. mod->funcs->debugfs_cleanup(mod, minor);
  372. }
  373. #endif
  374. static const struct file_operations fops = {
  375. .owner = THIS_MODULE,
  376. .open = drm_open,
  377. .release = drm_release,
  378. .unlocked_ioctl = drm_ioctl,
  379. #ifdef CONFIG_COMPAT
  380. .compat_ioctl = drm_compat_ioctl,
  381. #endif
  382. .poll = drm_poll,
  383. .read = drm_read,
  384. .fasync = drm_fasync,
  385. .llseek = no_llseek,
  386. .mmap = drm_gem_cma_mmap,
  387. };
  388. static struct drm_driver tilcdc_driver = {
  389. .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET,
  390. .load = tilcdc_load,
  391. .unload = tilcdc_unload,
  392. .preclose = tilcdc_preclose,
  393. .lastclose = tilcdc_lastclose,
  394. .irq_handler = tilcdc_irq,
  395. .irq_preinstall = tilcdc_irq_preinstall,
  396. .irq_postinstall = tilcdc_irq_postinstall,
  397. .irq_uninstall = tilcdc_irq_uninstall,
  398. .get_vblank_counter = drm_vblank_count,
  399. .enable_vblank = tilcdc_enable_vblank,
  400. .disable_vblank = tilcdc_disable_vblank,
  401. .gem_free_object = drm_gem_cma_free_object,
  402. .gem_vm_ops = &drm_gem_cma_vm_ops,
  403. .dumb_create = drm_gem_cma_dumb_create,
  404. .dumb_map_offset = drm_gem_cma_dumb_map_offset,
  405. .dumb_destroy = drm_gem_cma_dumb_destroy,
  406. #ifdef CONFIG_DEBUG_FS
  407. .debugfs_init = tilcdc_debugfs_init,
  408. .debugfs_cleanup = tilcdc_debugfs_cleanup,
  409. #endif
  410. .fops = &fops,
  411. .name = "tilcdc",
  412. .desc = "TI LCD Controller DRM",
  413. .date = "20121205",
  414. .major = 1,
  415. .minor = 0,
  416. };
  417. /*
  418. * Power management:
  419. */
  420. #ifdef CONFIG_PM_SLEEP
  421. static int tilcdc_pm_suspend(struct device *dev)
  422. {
  423. struct drm_device *ddev = dev_get_drvdata(dev);
  424. struct tilcdc_drm_private *priv = ddev->dev_private;
  425. unsigned i, n = 0;
  426. drm_kms_helper_poll_disable(ddev);
  427. /* Save register state: */
  428. for (i = 0; i < ARRAY_SIZE(registers); i++)
  429. if (registers[i].save && (priv->rev >= registers[i].rev))
  430. priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg);
  431. return 0;
  432. }
  433. static int tilcdc_pm_resume(struct device *dev)
  434. {
  435. struct drm_device *ddev = dev_get_drvdata(dev);
  436. struct tilcdc_drm_private *priv = ddev->dev_private;
  437. unsigned i, n = 0;
  438. /* Restore register state: */
  439. for (i = 0; i < ARRAY_SIZE(registers); i++)
  440. if (registers[i].save && (priv->rev >= registers[i].rev))
  441. tilcdc_write(ddev, registers[i].reg, priv->saved_register[n++]);
  442. drm_kms_helper_poll_enable(ddev);
  443. return 0;
  444. }
  445. #endif
  446. static const struct dev_pm_ops tilcdc_pm_ops = {
  447. SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
  448. };
  449. /*
  450. * Platform driver:
  451. */
  452. static int tilcdc_pdev_probe(struct platform_device *pdev)
  453. {
  454. /* bail out early if no DT data: */
  455. if (!pdev->dev.of_node) {
  456. dev_err(&pdev->dev, "device-tree data is missing\n");
  457. return -ENXIO;
  458. }
  459. return drm_platform_init(&tilcdc_driver, pdev);
  460. }
  461. static int tilcdc_pdev_remove(struct platform_device *pdev)
  462. {
  463. drm_platform_exit(&tilcdc_driver, pdev);
  464. return 0;
  465. }
  466. static struct of_device_id tilcdc_of_match[] = {
  467. { .compatible = "ti,am33xx-tilcdc", },
  468. { },
  469. };
  470. MODULE_DEVICE_TABLE(of, tilcdc_of_match);
  471. static struct platform_driver tilcdc_platform_driver = {
  472. .probe = tilcdc_pdev_probe,
  473. .remove = tilcdc_pdev_remove,
  474. .driver = {
  475. .owner = THIS_MODULE,
  476. .name = "tilcdc",
  477. .pm = &tilcdc_pm_ops,
  478. .of_match_table = tilcdc_of_match,
  479. },
  480. };
  481. static int __init tilcdc_drm_init(void)
  482. {
  483. DBG("init");
  484. tilcdc_tfp410_init();
  485. return platform_driver_register(&tilcdc_platform_driver);
  486. }
  487. static void __exit tilcdc_drm_fini(void)
  488. {
  489. DBG("fini");
  490. tilcdc_tfp410_fini();
  491. platform_driver_unregister(&tilcdc_platform_driver);
  492. }
  493. module_init(tilcdc_drm_init);
  494. module_exit(tilcdc_drm_fini);
  495. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  496. MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
  497. MODULE_LICENSE("GPL");