setup.c 27 KB

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  1. /*
  2. * Copyright (C) 2009 Renesas Solutions Corp.
  3. *
  4. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/init.h>
  11. #include <linux/device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/mtd/physmap.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/delay.h>
  18. #include <linux/usb/r8a66597.h>
  19. #include <linux/i2c.h>
  20. #include <linux/i2c/tsc2007.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/spi/sh_msiof.h>
  23. #include <linux/spi/mmc_spi.h>
  24. #include <linux/mmc/host.h>
  25. #include <linux/input.h>
  26. #include <linux/input/sh_keysc.h>
  27. #include <linux/mfd/sh_mobile_sdhi.h>
  28. #include <video/sh_mobile_lcdc.h>
  29. #include <sound/sh_fsi.h>
  30. #include <media/sh_mobile_ceu.h>
  31. #include <media/tw9910.h>
  32. #include <media/mt9t112.h>
  33. #include <asm/heartbeat.h>
  34. #include <asm/sh_eth.h>
  35. #include <asm/clock.h>
  36. #include <asm/suspend.h>
  37. #include <cpu/sh7724.h>
  38. /*
  39. * Address Interface BusWidth
  40. *-----------------------------------------
  41. * 0x0000_0000 uboot 16bit
  42. * 0x0004_0000 Linux romImage 16bit
  43. * 0x0014_0000 MTD for Linux 16bit
  44. * 0x0400_0000 Internal I/O 16/32bit
  45. * 0x0800_0000 DRAM 32bit
  46. * 0x1800_0000 MFI 16bit
  47. */
  48. /* SWITCH
  49. *------------------------------
  50. * DS2[1] = FlashROM write protect ON : write protect
  51. * OFF : No write protect
  52. * DS2[2] = RMII / TS, SCIF ON : RMII
  53. * OFF : TS, SCIF3
  54. * DS2[3] = Camera / Video ON : Camera
  55. * OFF : NTSC/PAL (IN)
  56. * DS2[5] = NTSC_OUT Clock ON : On board OSC
  57. * OFF : SH7724 DV_CLK
  58. * DS2[6-7] = MMC / SD ON-OFF : SD
  59. * OFF-ON : MMC
  60. */
  61. /* Heartbeat */
  62. static unsigned char led_pos[] = { 0, 1, 2, 3 };
  63. static struct heartbeat_data heartbeat_data = {
  64. .nr_bits = 4,
  65. .bit_pos = led_pos,
  66. };
  67. static struct resource heartbeat_resource = {
  68. .start = 0xA405012C, /* PTG */
  69. .end = 0xA405012E - 1,
  70. .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
  71. };
  72. static struct platform_device heartbeat_device = {
  73. .name = "heartbeat",
  74. .id = -1,
  75. .dev = {
  76. .platform_data = &heartbeat_data,
  77. },
  78. .num_resources = 1,
  79. .resource = &heartbeat_resource,
  80. };
  81. /* MTD */
  82. static struct mtd_partition nor_flash_partitions[] = {
  83. {
  84. .name = "boot loader",
  85. .offset = 0,
  86. .size = (5 * 1024 * 1024),
  87. .mask_flags = MTD_WRITEABLE, /* force read-only */
  88. }, {
  89. .name = "free-area",
  90. .offset = MTDPART_OFS_APPEND,
  91. .size = MTDPART_SIZ_FULL,
  92. },
  93. };
  94. static struct physmap_flash_data nor_flash_data = {
  95. .width = 2,
  96. .parts = nor_flash_partitions,
  97. .nr_parts = ARRAY_SIZE(nor_flash_partitions),
  98. };
  99. static struct resource nor_flash_resources[] = {
  100. [0] = {
  101. .name = "NOR Flash",
  102. .start = 0x00000000,
  103. .end = 0x03ffffff,
  104. .flags = IORESOURCE_MEM,
  105. }
  106. };
  107. static struct platform_device nor_flash_device = {
  108. .name = "physmap-flash",
  109. .resource = nor_flash_resources,
  110. .num_resources = ARRAY_SIZE(nor_flash_resources),
  111. .dev = {
  112. .platform_data = &nor_flash_data,
  113. },
  114. };
  115. /* SH Eth */
  116. #define SH_ETH_ADDR (0xA4600000)
  117. static struct resource sh_eth_resources[] = {
  118. [0] = {
  119. .start = SH_ETH_ADDR,
  120. .end = SH_ETH_ADDR + 0x1FC,
  121. .flags = IORESOURCE_MEM,
  122. },
  123. [1] = {
  124. .start = 91,
  125. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  126. },
  127. };
  128. struct sh_eth_plat_data sh_eth_plat = {
  129. .phy = 0x1f, /* SMSC LAN8700 */
  130. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  131. .ether_link_active_low = 1
  132. };
  133. static struct platform_device sh_eth_device = {
  134. .name = "sh-eth",
  135. .id = 0,
  136. .dev = {
  137. .platform_data = &sh_eth_plat,
  138. },
  139. .num_resources = ARRAY_SIZE(sh_eth_resources),
  140. .resource = sh_eth_resources,
  141. .archdata = {
  142. .hwblk_id = HWBLK_ETHER,
  143. },
  144. };
  145. /* USB0 host */
  146. void usb0_port_power(int port, int power)
  147. {
  148. gpio_set_value(GPIO_PTB4, power);
  149. }
  150. static struct r8a66597_platdata usb0_host_data = {
  151. .on_chip = 1,
  152. .port_power = usb0_port_power,
  153. };
  154. static struct resource usb0_host_resources[] = {
  155. [0] = {
  156. .start = 0xa4d80000,
  157. .end = 0xa4d80124 - 1,
  158. .flags = IORESOURCE_MEM,
  159. },
  160. [1] = {
  161. .start = 65,
  162. .end = 65,
  163. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  164. },
  165. };
  166. static struct platform_device usb0_host_device = {
  167. .name = "r8a66597_hcd",
  168. .id = 0,
  169. .dev = {
  170. .dma_mask = NULL, /* not use dma */
  171. .coherent_dma_mask = 0xffffffff,
  172. .platform_data = &usb0_host_data,
  173. },
  174. .num_resources = ARRAY_SIZE(usb0_host_resources),
  175. .resource = usb0_host_resources,
  176. };
  177. /* USB1 host/function */
  178. void usb1_port_power(int port, int power)
  179. {
  180. gpio_set_value(GPIO_PTB5, power);
  181. }
  182. static struct r8a66597_platdata usb1_common_data = {
  183. .on_chip = 1,
  184. .port_power = usb1_port_power,
  185. };
  186. static struct resource usb1_common_resources[] = {
  187. [0] = {
  188. .start = 0xa4d90000,
  189. .end = 0xa4d90124 - 1,
  190. .flags = IORESOURCE_MEM,
  191. },
  192. [1] = {
  193. .start = 66,
  194. .end = 66,
  195. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  196. },
  197. };
  198. static struct platform_device usb1_common_device = {
  199. /* .name will be added in arch_setup */
  200. .id = 1,
  201. .dev = {
  202. .dma_mask = NULL, /* not use dma */
  203. .coherent_dma_mask = 0xffffffff,
  204. .platform_data = &usb1_common_data,
  205. },
  206. .num_resources = ARRAY_SIZE(usb1_common_resources),
  207. .resource = usb1_common_resources,
  208. };
  209. /* LCDC */
  210. static struct sh_mobile_lcdc_info lcdc_info = {
  211. .ch[0] = {
  212. .interface_type = RGB18,
  213. .chan = LCDC_CHAN_MAINLCD,
  214. .bpp = 16,
  215. .lcd_cfg = {
  216. .sync = 0, /* hsync and vsync are active low */
  217. },
  218. .lcd_size_cfg = { /* 7.0 inch */
  219. .width = 152,
  220. .height = 91,
  221. },
  222. .board_cfg = {
  223. },
  224. }
  225. };
  226. static struct resource lcdc_resources[] = {
  227. [0] = {
  228. .name = "LCDC",
  229. .start = 0xfe940000,
  230. .end = 0xfe942fff,
  231. .flags = IORESOURCE_MEM,
  232. },
  233. [1] = {
  234. .start = 106,
  235. .flags = IORESOURCE_IRQ,
  236. },
  237. };
  238. static struct platform_device lcdc_device = {
  239. .name = "sh_mobile_lcdc_fb",
  240. .num_resources = ARRAY_SIZE(lcdc_resources),
  241. .resource = lcdc_resources,
  242. .dev = {
  243. .platform_data = &lcdc_info,
  244. },
  245. .archdata = {
  246. .hwblk_id = HWBLK_LCDC,
  247. },
  248. };
  249. /* CEU0 */
  250. static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
  251. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  252. };
  253. static struct resource ceu0_resources[] = {
  254. [0] = {
  255. .name = "CEU0",
  256. .start = 0xfe910000,
  257. .end = 0xfe91009f,
  258. .flags = IORESOURCE_MEM,
  259. },
  260. [1] = {
  261. .start = 52,
  262. .flags = IORESOURCE_IRQ,
  263. },
  264. [2] = {
  265. /* place holder for contiguous memory */
  266. },
  267. };
  268. static struct platform_device ceu0_device = {
  269. .name = "sh_mobile_ceu",
  270. .id = 0, /* "ceu0" clock */
  271. .num_resources = ARRAY_SIZE(ceu0_resources),
  272. .resource = ceu0_resources,
  273. .dev = {
  274. .platform_data = &sh_mobile_ceu0_info,
  275. },
  276. .archdata = {
  277. .hwblk_id = HWBLK_CEU0,
  278. },
  279. };
  280. /* CEU1 */
  281. static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
  282. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  283. };
  284. static struct resource ceu1_resources[] = {
  285. [0] = {
  286. .name = "CEU1",
  287. .start = 0xfe914000,
  288. .end = 0xfe91409f,
  289. .flags = IORESOURCE_MEM,
  290. },
  291. [1] = {
  292. .start = 63,
  293. .flags = IORESOURCE_IRQ,
  294. },
  295. [2] = {
  296. /* place holder for contiguous memory */
  297. },
  298. };
  299. static struct platform_device ceu1_device = {
  300. .name = "sh_mobile_ceu",
  301. .id = 1, /* "ceu1" clock */
  302. .num_resources = ARRAY_SIZE(ceu1_resources),
  303. .resource = ceu1_resources,
  304. .dev = {
  305. .platform_data = &sh_mobile_ceu1_info,
  306. },
  307. .archdata = {
  308. .hwblk_id = HWBLK_CEU1,
  309. },
  310. };
  311. /* I2C device */
  312. static struct i2c_board_info i2c0_devices[] = {
  313. {
  314. I2C_BOARD_INFO("da7210", 0x1a),
  315. },
  316. };
  317. static struct i2c_board_info i2c1_devices[] = {
  318. {
  319. I2C_BOARD_INFO("r2025sd", 0x32),
  320. },
  321. {
  322. I2C_BOARD_INFO("lis3lv02d", 0x1c),
  323. .irq = 33,
  324. }
  325. };
  326. /* KEYSC */
  327. static struct sh_keysc_info keysc_info = {
  328. .mode = SH_KEYSC_MODE_1,
  329. .scan_timing = 3,
  330. .delay = 50,
  331. .kycr2_delay = 100,
  332. .keycodes = { KEY_1, 0, 0, 0, 0,
  333. KEY_2, 0, 0, 0, 0,
  334. KEY_3, 0, 0, 0, 0,
  335. KEY_4, 0, 0, 0, 0,
  336. KEY_5, 0, 0, 0, 0,
  337. KEY_6, 0, 0, 0, 0, },
  338. };
  339. static struct resource keysc_resources[] = {
  340. [0] = {
  341. .name = "KEYSC",
  342. .start = 0x044b0000,
  343. .end = 0x044b000f,
  344. .flags = IORESOURCE_MEM,
  345. },
  346. [1] = {
  347. .start = 79,
  348. .flags = IORESOURCE_IRQ,
  349. },
  350. };
  351. static struct platform_device keysc_device = {
  352. .name = "sh_keysc",
  353. .id = 0, /* keysc0 clock */
  354. .num_resources = ARRAY_SIZE(keysc_resources),
  355. .resource = keysc_resources,
  356. .dev = {
  357. .platform_data = &keysc_info,
  358. },
  359. .archdata = {
  360. .hwblk_id = HWBLK_KEYSC,
  361. },
  362. };
  363. /* TouchScreen */
  364. #define IRQ0 32
  365. static int ts_get_pendown_state(void)
  366. {
  367. int val = 0;
  368. gpio_free(GPIO_FN_INTC_IRQ0);
  369. gpio_request(GPIO_PTZ0, NULL);
  370. gpio_direction_input(GPIO_PTZ0);
  371. val = gpio_get_value(GPIO_PTZ0);
  372. gpio_free(GPIO_PTZ0);
  373. gpio_request(GPIO_FN_INTC_IRQ0, NULL);
  374. return val ? 0 : 1;
  375. }
  376. static int ts_init(void)
  377. {
  378. gpio_request(GPIO_FN_INTC_IRQ0, NULL);
  379. return 0;
  380. }
  381. struct tsc2007_platform_data tsc2007_info = {
  382. .model = 2007,
  383. .x_plate_ohms = 180,
  384. .get_pendown_state = ts_get_pendown_state,
  385. .init_platform_hw = ts_init,
  386. };
  387. static struct i2c_board_info ts_i2c_clients = {
  388. I2C_BOARD_INFO("tsc2007", 0x48),
  389. .type = "tsc2007",
  390. .platform_data = &tsc2007_info,
  391. .irq = IRQ0,
  392. };
  393. #ifdef CONFIG_MFD_SH_MOBILE_SDHI
  394. /* SHDI0 */
  395. static void sdhi0_set_pwr(struct platform_device *pdev, int state)
  396. {
  397. gpio_set_value(GPIO_PTB6, state);
  398. }
  399. static struct sh_mobile_sdhi_info sdhi0_info = {
  400. .set_pwr = sdhi0_set_pwr,
  401. };
  402. static struct resource sdhi0_resources[] = {
  403. [0] = {
  404. .name = "SDHI0",
  405. .start = 0x04ce0000,
  406. .end = 0x04ce01ff,
  407. .flags = IORESOURCE_MEM,
  408. },
  409. [1] = {
  410. .start = 100,
  411. .flags = IORESOURCE_IRQ,
  412. },
  413. };
  414. static struct platform_device sdhi0_device = {
  415. .name = "sh_mobile_sdhi",
  416. .num_resources = ARRAY_SIZE(sdhi0_resources),
  417. .resource = sdhi0_resources,
  418. .id = 0,
  419. .dev = {
  420. .platform_data = &sdhi0_info,
  421. },
  422. .archdata = {
  423. .hwblk_id = HWBLK_SDHI0,
  424. },
  425. };
  426. /* SHDI1 */
  427. static void sdhi1_set_pwr(struct platform_device *pdev, int state)
  428. {
  429. gpio_set_value(GPIO_PTB7, state);
  430. }
  431. static struct sh_mobile_sdhi_info sdhi1_info = {
  432. .set_pwr = sdhi1_set_pwr,
  433. };
  434. static struct resource sdhi1_resources[] = {
  435. [0] = {
  436. .name = "SDHI1",
  437. .start = 0x04cf0000,
  438. .end = 0x04cf01ff,
  439. .flags = IORESOURCE_MEM,
  440. },
  441. [1] = {
  442. .start = 23,
  443. .flags = IORESOURCE_IRQ,
  444. },
  445. };
  446. static struct platform_device sdhi1_device = {
  447. .name = "sh_mobile_sdhi",
  448. .num_resources = ARRAY_SIZE(sdhi1_resources),
  449. .resource = sdhi1_resources,
  450. .id = 1,
  451. .dev = {
  452. .platform_data = &sdhi1_info,
  453. },
  454. .archdata = {
  455. .hwblk_id = HWBLK_SDHI1,
  456. },
  457. };
  458. #else
  459. /* MMC SPI */
  460. static int mmc_spi_get_ro(struct device *dev)
  461. {
  462. return gpio_get_value(GPIO_PTY6);
  463. }
  464. static int mmc_spi_get_cd(struct device *dev)
  465. {
  466. return !gpio_get_value(GPIO_PTY7);
  467. }
  468. static void mmc_spi_setpower(struct device *dev, unsigned int maskval)
  469. {
  470. gpio_set_value(GPIO_PTB6, maskval ? 1 : 0);
  471. }
  472. static struct mmc_spi_platform_data mmc_spi_info = {
  473. .get_ro = mmc_spi_get_ro,
  474. .get_cd = mmc_spi_get_cd,
  475. .caps = MMC_CAP_NEEDS_POLL,
  476. .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3.3V only */
  477. .setpower = mmc_spi_setpower,
  478. };
  479. static struct spi_board_info spi_bus[] = {
  480. {
  481. .modalias = "mmc_spi",
  482. .platform_data = &mmc_spi_info,
  483. .max_speed_hz = 5000000,
  484. .mode = SPI_MODE_0,
  485. .controller_data = (void *) GPIO_PTM4,
  486. },
  487. };
  488. /* MSIOF0 */
  489. static struct sh_msiof_spi_info msiof0_data = {
  490. .num_chipselect = 1,
  491. };
  492. static struct resource msiof0_resources[] = {
  493. [0] = {
  494. .name = "MSIOF0",
  495. .start = 0xa4c40000,
  496. .end = 0xa4c40063,
  497. .flags = IORESOURCE_MEM,
  498. },
  499. [1] = {
  500. .start = 84,
  501. .flags = IORESOURCE_IRQ,
  502. },
  503. };
  504. static struct platform_device msiof0_device = {
  505. .name = "spi_sh_msiof",
  506. .id = 0, /* MSIOF0 */
  507. .dev = {
  508. .platform_data = &msiof0_data,
  509. },
  510. .num_resources = ARRAY_SIZE(msiof0_resources),
  511. .resource = msiof0_resources,
  512. .archdata = {
  513. .hwblk_id = HWBLK_MSIOF0,
  514. },
  515. };
  516. #endif
  517. /* I2C Video/Camera */
  518. static struct i2c_board_info i2c_camera[] = {
  519. {
  520. I2C_BOARD_INFO("tw9910", 0x45),
  521. },
  522. {
  523. /* 1st camera */
  524. I2C_BOARD_INFO("mt9t112", 0x3c),
  525. },
  526. {
  527. /* 2nd camera */
  528. I2C_BOARD_INFO("mt9t112", 0x3c),
  529. },
  530. };
  531. /* tw9910 */
  532. static int tw9910_power(struct device *dev, int mode)
  533. {
  534. int val = mode ? 0 : 1;
  535. gpio_set_value(GPIO_PTU2, val);
  536. if (mode)
  537. mdelay(100);
  538. return 0;
  539. }
  540. static struct tw9910_video_info tw9910_info = {
  541. .buswidth = SOCAM_DATAWIDTH_8,
  542. .mpout = TW9910_MPO_FIELD,
  543. };
  544. static struct soc_camera_link tw9910_link = {
  545. .i2c_adapter_id = 0,
  546. .bus_id = 1,
  547. .power = tw9910_power,
  548. .board_info = &i2c_camera[0],
  549. .module_name = "tw9910",
  550. .priv = &tw9910_info,
  551. };
  552. /* mt9t112 */
  553. static int mt9t112_power1(struct device *dev, int mode)
  554. {
  555. gpio_set_value(GPIO_PTA3, mode);
  556. if (mode)
  557. mdelay(100);
  558. return 0;
  559. }
  560. static struct mt9t112_camera_info mt9t112_info1 = {
  561. .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8,
  562. .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
  563. };
  564. static struct soc_camera_link mt9t112_link1 = {
  565. .i2c_adapter_id = 0,
  566. .power = mt9t112_power1,
  567. .bus_id = 0,
  568. .board_info = &i2c_camera[1],
  569. .module_name = "mt9t112",
  570. .priv = &mt9t112_info1,
  571. };
  572. static int mt9t112_power2(struct device *dev, int mode)
  573. {
  574. gpio_set_value(GPIO_PTA4, mode);
  575. if (mode)
  576. mdelay(100);
  577. return 0;
  578. }
  579. static struct mt9t112_camera_info mt9t112_info2 = {
  580. .flags = MT9T112_FLAG_PCLK_RISING_EDGE | MT9T112_FLAG_DATAWIDTH_8,
  581. .divider = { 0x49, 0x6, 0, 6, 0, 9, 9, 6, 0 }, /* for 24MHz */
  582. };
  583. static struct soc_camera_link mt9t112_link2 = {
  584. .i2c_adapter_id = 1,
  585. .power = mt9t112_power2,
  586. .bus_id = 1,
  587. .board_info = &i2c_camera[2],
  588. .module_name = "mt9t112",
  589. .priv = &mt9t112_info2,
  590. };
  591. static struct platform_device camera_devices[] = {
  592. {
  593. .name = "soc-camera-pdrv",
  594. .id = 0,
  595. .dev = {
  596. .platform_data = &tw9910_link,
  597. },
  598. },
  599. {
  600. .name = "soc-camera-pdrv",
  601. .id = 1,
  602. .dev = {
  603. .platform_data = &mt9t112_link1,
  604. },
  605. },
  606. {
  607. .name = "soc-camera-pdrv",
  608. .id = 2,
  609. .dev = {
  610. .platform_data = &mt9t112_link2,
  611. },
  612. },
  613. };
  614. /* FSI */
  615. /*
  616. * FSI-B use external clock which came from da7210.
  617. * So, we should change parent of fsi
  618. */
  619. #define FCLKBCR 0xa415000c
  620. static void fsimck_init(struct clk *clk)
  621. {
  622. u32 status = __raw_readl(clk->enable_reg);
  623. /* use external clock */
  624. status &= ~0x000000ff;
  625. status |= 0x00000080;
  626. __raw_writel(status, clk->enable_reg);
  627. }
  628. static struct clk_ops fsimck_clk_ops = {
  629. .init = fsimck_init,
  630. };
  631. static struct clk fsimckb_clk = {
  632. .name = "fsimckb_clk",
  633. .id = -1,
  634. .ops = &fsimck_clk_ops,
  635. .enable_reg = (void __iomem *)FCLKBCR,
  636. .rate = 0, /* unknown */
  637. };
  638. struct sh_fsi_platform_info fsi_info = {
  639. .portb_flags = SH_FSI_BRS_INV |
  640. SH_FSI_OUT_SLAVE_MODE |
  641. SH_FSI_IN_SLAVE_MODE |
  642. SH_FSI_OFMT(I2S) |
  643. SH_FSI_IFMT(I2S),
  644. };
  645. static struct resource fsi_resources[] = {
  646. [0] = {
  647. .name = "FSI",
  648. .start = 0xFE3C0000,
  649. .end = 0xFE3C021d,
  650. .flags = IORESOURCE_MEM,
  651. },
  652. [1] = {
  653. .start = 108,
  654. .flags = IORESOURCE_IRQ,
  655. },
  656. };
  657. static struct platform_device fsi_device = {
  658. .name = "sh_fsi",
  659. .id = 0,
  660. .num_resources = ARRAY_SIZE(fsi_resources),
  661. .resource = fsi_resources,
  662. .dev = {
  663. .platform_data = &fsi_info,
  664. },
  665. .archdata = {
  666. .hwblk_id = HWBLK_SPU, /* FSI needs SPU hwblk */
  667. },
  668. };
  669. static struct platform_device *ecovec_devices[] __initdata = {
  670. &heartbeat_device,
  671. &nor_flash_device,
  672. &sh_eth_device,
  673. &usb0_host_device,
  674. &usb1_common_device,
  675. &lcdc_device,
  676. &ceu0_device,
  677. &ceu1_device,
  678. &keysc_device,
  679. #ifdef CONFIG_MFD_SH_MOBILE_SDHI
  680. &sdhi0_device,
  681. &sdhi1_device,
  682. #else
  683. &msiof0_device,
  684. #endif
  685. &camera_devices[0],
  686. &camera_devices[1],
  687. &camera_devices[2],
  688. &fsi_device,
  689. };
  690. #define EEPROM_ADDR 0x50
  691. static u8 mac_read(struct i2c_adapter *a, u8 command)
  692. {
  693. struct i2c_msg msg[2];
  694. u8 buf;
  695. int ret;
  696. msg[0].addr = EEPROM_ADDR;
  697. msg[0].flags = 0;
  698. msg[0].len = 1;
  699. msg[0].buf = &command;
  700. msg[1].addr = EEPROM_ADDR;
  701. msg[1].flags = I2C_M_RD;
  702. msg[1].len = 1;
  703. msg[1].buf = &buf;
  704. ret = i2c_transfer(a, msg, 2);
  705. if (ret < 0) {
  706. printk(KERN_ERR "error %d\n", ret);
  707. buf = 0xff;
  708. }
  709. return buf;
  710. }
  711. static void __init sh_eth_init(struct sh_eth_plat_data *pd)
  712. {
  713. struct i2c_adapter *a = i2c_get_adapter(1);
  714. int i;
  715. if (!a) {
  716. pr_err("can not get I2C 1\n");
  717. return;
  718. }
  719. /* read MAC address frome EEPROM */
  720. for (i = 0; i < sizeof(pd->mac_addr); i++) {
  721. pd->mac_addr[i] = mac_read(a, 0x10 + i);
  722. msleep(10);
  723. }
  724. }
  725. #define PORT_HIZA 0xA4050158
  726. #define IODRIVEA 0xA405018A
  727. extern char ecovec24_sdram_enter_start;
  728. extern char ecovec24_sdram_enter_end;
  729. extern char ecovec24_sdram_leave_start;
  730. extern char ecovec24_sdram_leave_end;
  731. static int __init arch_setup(void)
  732. {
  733. struct clk *clk;
  734. /* register board specific self-refresh code */
  735. sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
  736. &ecovec24_sdram_enter_start,
  737. &ecovec24_sdram_enter_end,
  738. &ecovec24_sdram_leave_start,
  739. &ecovec24_sdram_leave_end);
  740. /* enable STATUS0, STATUS2 and PDSTATUS */
  741. gpio_request(GPIO_FN_STATUS0, NULL);
  742. gpio_request(GPIO_FN_STATUS2, NULL);
  743. gpio_request(GPIO_FN_PDSTATUS, NULL);
  744. /* enable SCIFA0 */
  745. gpio_request(GPIO_FN_SCIF0_TXD, NULL);
  746. gpio_request(GPIO_FN_SCIF0_RXD, NULL);
  747. /* enable debug LED */
  748. gpio_request(GPIO_PTG0, NULL);
  749. gpio_request(GPIO_PTG1, NULL);
  750. gpio_request(GPIO_PTG2, NULL);
  751. gpio_request(GPIO_PTG3, NULL);
  752. gpio_direction_output(GPIO_PTG0, 0);
  753. gpio_direction_output(GPIO_PTG1, 0);
  754. gpio_direction_output(GPIO_PTG2, 0);
  755. gpio_direction_output(GPIO_PTG3, 0);
  756. __raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
  757. /* enable SH-Eth */
  758. gpio_request(GPIO_PTA1, NULL);
  759. gpio_direction_output(GPIO_PTA1, 1);
  760. mdelay(20);
  761. gpio_request(GPIO_FN_RMII_RXD0, NULL);
  762. gpio_request(GPIO_FN_RMII_RXD1, NULL);
  763. gpio_request(GPIO_FN_RMII_TXD0, NULL);
  764. gpio_request(GPIO_FN_RMII_TXD1, NULL);
  765. gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
  766. gpio_request(GPIO_FN_RMII_TX_EN, NULL);
  767. gpio_request(GPIO_FN_RMII_RX_ER, NULL);
  768. gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
  769. gpio_request(GPIO_FN_MDIO, NULL);
  770. gpio_request(GPIO_FN_MDC, NULL);
  771. gpio_request(GPIO_FN_LNKSTA, NULL);
  772. /* enable USB */
  773. __raw_writew(0x0000, 0xA4D80000);
  774. __raw_writew(0x0000, 0xA4D90000);
  775. gpio_request(GPIO_PTB3, NULL);
  776. gpio_request(GPIO_PTB4, NULL);
  777. gpio_request(GPIO_PTB5, NULL);
  778. gpio_direction_input(GPIO_PTB3);
  779. gpio_direction_output(GPIO_PTB4, 0);
  780. gpio_direction_output(GPIO_PTB5, 0);
  781. __raw_writew(0x0600, 0xa40501d4);
  782. __raw_writew(0x0600, 0xa4050192);
  783. if (gpio_get_value(GPIO_PTB3)) {
  784. printk(KERN_INFO "USB1 function is selected\n");
  785. usb1_common_device.name = "r8a66597_udc";
  786. } else {
  787. printk(KERN_INFO "USB1 host is selected\n");
  788. usb1_common_device.name = "r8a66597_hcd";
  789. }
  790. /* enable LCDC */
  791. gpio_request(GPIO_FN_LCDD23, NULL);
  792. gpio_request(GPIO_FN_LCDD22, NULL);
  793. gpio_request(GPIO_FN_LCDD21, NULL);
  794. gpio_request(GPIO_FN_LCDD20, NULL);
  795. gpio_request(GPIO_FN_LCDD19, NULL);
  796. gpio_request(GPIO_FN_LCDD18, NULL);
  797. gpio_request(GPIO_FN_LCDD17, NULL);
  798. gpio_request(GPIO_FN_LCDD16, NULL);
  799. gpio_request(GPIO_FN_LCDD15, NULL);
  800. gpio_request(GPIO_FN_LCDD14, NULL);
  801. gpio_request(GPIO_FN_LCDD13, NULL);
  802. gpio_request(GPIO_FN_LCDD12, NULL);
  803. gpio_request(GPIO_FN_LCDD11, NULL);
  804. gpio_request(GPIO_FN_LCDD10, NULL);
  805. gpio_request(GPIO_FN_LCDD9, NULL);
  806. gpio_request(GPIO_FN_LCDD8, NULL);
  807. gpio_request(GPIO_FN_LCDD7, NULL);
  808. gpio_request(GPIO_FN_LCDD6, NULL);
  809. gpio_request(GPIO_FN_LCDD5, NULL);
  810. gpio_request(GPIO_FN_LCDD4, NULL);
  811. gpio_request(GPIO_FN_LCDD3, NULL);
  812. gpio_request(GPIO_FN_LCDD2, NULL);
  813. gpio_request(GPIO_FN_LCDD1, NULL);
  814. gpio_request(GPIO_FN_LCDD0, NULL);
  815. gpio_request(GPIO_FN_LCDDISP, NULL);
  816. gpio_request(GPIO_FN_LCDHSYN, NULL);
  817. gpio_request(GPIO_FN_LCDDCK, NULL);
  818. gpio_request(GPIO_FN_LCDVSYN, NULL);
  819. gpio_request(GPIO_FN_LCDDON, NULL);
  820. gpio_request(GPIO_FN_LCDLCLK, NULL);
  821. __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
  822. gpio_request(GPIO_PTE6, NULL);
  823. gpio_request(GPIO_PTU1, NULL);
  824. gpio_request(GPIO_PTR1, NULL);
  825. gpio_request(GPIO_PTA2, NULL);
  826. gpio_direction_input(GPIO_PTE6);
  827. gpio_direction_output(GPIO_PTU1, 0);
  828. gpio_direction_output(GPIO_PTR1, 0);
  829. gpio_direction_output(GPIO_PTA2, 0);
  830. /* I/O buffer drive ability is high */
  831. __raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
  832. if (gpio_get_value(GPIO_PTE6)) {
  833. /* DVI */
  834. lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
  835. lcdc_info.ch[0].clock_divider = 1,
  836. lcdc_info.ch[0].lcd_cfg.name = "DVI";
  837. lcdc_info.ch[0].lcd_cfg.xres = 1280;
  838. lcdc_info.ch[0].lcd_cfg.yres = 720;
  839. lcdc_info.ch[0].lcd_cfg.left_margin = 220;
  840. lcdc_info.ch[0].lcd_cfg.right_margin = 110;
  841. lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
  842. lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
  843. lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
  844. lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
  845. gpio_set_value(GPIO_PTA2, 1);
  846. gpio_set_value(GPIO_PTU1, 1);
  847. } else {
  848. /* Panel */
  849. lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
  850. lcdc_info.ch[0].clock_divider = 2,
  851. lcdc_info.ch[0].lcd_cfg.name = "Panel";
  852. lcdc_info.ch[0].lcd_cfg.xres = 800;
  853. lcdc_info.ch[0].lcd_cfg.yres = 480;
  854. lcdc_info.ch[0].lcd_cfg.left_margin = 220;
  855. lcdc_info.ch[0].lcd_cfg.right_margin = 110;
  856. lcdc_info.ch[0].lcd_cfg.hsync_len = 70;
  857. lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
  858. lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
  859. lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
  860. gpio_set_value(GPIO_PTR1, 1);
  861. /* FIXME
  862. *
  863. * LCDDON control is needed for Panel,
  864. * but current sh_mobile_lcdc driver doesn't control it.
  865. * It is temporary correspondence
  866. */
  867. gpio_request(GPIO_PTF4, NULL);
  868. gpio_direction_output(GPIO_PTF4, 1);
  869. /* enable TouchScreen */
  870. i2c_register_board_info(0, &ts_i2c_clients, 1);
  871. set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
  872. }
  873. /* enable CEU0 */
  874. gpio_request(GPIO_FN_VIO0_D15, NULL);
  875. gpio_request(GPIO_FN_VIO0_D14, NULL);
  876. gpio_request(GPIO_FN_VIO0_D13, NULL);
  877. gpio_request(GPIO_FN_VIO0_D12, NULL);
  878. gpio_request(GPIO_FN_VIO0_D11, NULL);
  879. gpio_request(GPIO_FN_VIO0_D10, NULL);
  880. gpio_request(GPIO_FN_VIO0_D9, NULL);
  881. gpio_request(GPIO_FN_VIO0_D8, NULL);
  882. gpio_request(GPIO_FN_VIO0_D7, NULL);
  883. gpio_request(GPIO_FN_VIO0_D6, NULL);
  884. gpio_request(GPIO_FN_VIO0_D5, NULL);
  885. gpio_request(GPIO_FN_VIO0_D4, NULL);
  886. gpio_request(GPIO_FN_VIO0_D3, NULL);
  887. gpio_request(GPIO_FN_VIO0_D2, NULL);
  888. gpio_request(GPIO_FN_VIO0_D1, NULL);
  889. gpio_request(GPIO_FN_VIO0_D0, NULL);
  890. gpio_request(GPIO_FN_VIO0_VD, NULL);
  891. gpio_request(GPIO_FN_VIO0_CLK, NULL);
  892. gpio_request(GPIO_FN_VIO0_FLD, NULL);
  893. gpio_request(GPIO_FN_VIO0_HD, NULL);
  894. platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
  895. /* enable CEU1 */
  896. gpio_request(GPIO_FN_VIO1_D7, NULL);
  897. gpio_request(GPIO_FN_VIO1_D6, NULL);
  898. gpio_request(GPIO_FN_VIO1_D5, NULL);
  899. gpio_request(GPIO_FN_VIO1_D4, NULL);
  900. gpio_request(GPIO_FN_VIO1_D3, NULL);
  901. gpio_request(GPIO_FN_VIO1_D2, NULL);
  902. gpio_request(GPIO_FN_VIO1_D1, NULL);
  903. gpio_request(GPIO_FN_VIO1_D0, NULL);
  904. gpio_request(GPIO_FN_VIO1_FLD, NULL);
  905. gpio_request(GPIO_FN_VIO1_HD, NULL);
  906. gpio_request(GPIO_FN_VIO1_VD, NULL);
  907. gpio_request(GPIO_FN_VIO1_CLK, NULL);
  908. platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
  909. /* enable KEYSC */
  910. gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
  911. gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
  912. gpio_request(GPIO_FN_KEYOUT3, NULL);
  913. gpio_request(GPIO_FN_KEYOUT2, NULL);
  914. gpio_request(GPIO_FN_KEYOUT1, NULL);
  915. gpio_request(GPIO_FN_KEYOUT0, NULL);
  916. gpio_request(GPIO_FN_KEYIN0, NULL);
  917. /* enable user debug switch */
  918. gpio_request(GPIO_PTR0, NULL);
  919. gpio_request(GPIO_PTR4, NULL);
  920. gpio_request(GPIO_PTR5, NULL);
  921. gpio_request(GPIO_PTR6, NULL);
  922. gpio_direction_input(GPIO_PTR0);
  923. gpio_direction_input(GPIO_PTR4);
  924. gpio_direction_input(GPIO_PTR5);
  925. gpio_direction_input(GPIO_PTR6);
  926. #ifdef CONFIG_MFD_SH_MOBILE_SDHI
  927. /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
  928. gpio_request(GPIO_FN_SDHI0CD, NULL);
  929. gpio_request(GPIO_FN_SDHI0WP, NULL);
  930. gpio_request(GPIO_FN_SDHI0CMD, NULL);
  931. gpio_request(GPIO_FN_SDHI0CLK, NULL);
  932. gpio_request(GPIO_FN_SDHI0D3, NULL);
  933. gpio_request(GPIO_FN_SDHI0D2, NULL);
  934. gpio_request(GPIO_FN_SDHI0D1, NULL);
  935. gpio_request(GPIO_FN_SDHI0D0, NULL);
  936. gpio_request(GPIO_PTB6, NULL);
  937. gpio_direction_output(GPIO_PTB6, 0);
  938. /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
  939. gpio_request(GPIO_FN_SDHI1CD, NULL);
  940. gpio_request(GPIO_FN_SDHI1WP, NULL);
  941. gpio_request(GPIO_FN_SDHI1CMD, NULL);
  942. gpio_request(GPIO_FN_SDHI1CLK, NULL);
  943. gpio_request(GPIO_FN_SDHI1D3, NULL);
  944. gpio_request(GPIO_FN_SDHI1D2, NULL);
  945. gpio_request(GPIO_FN_SDHI1D1, NULL);
  946. gpio_request(GPIO_FN_SDHI1D0, NULL);
  947. gpio_request(GPIO_PTB7, NULL);
  948. gpio_direction_output(GPIO_PTB7, 0);
  949. /* I/O buffer drive ability is high for SDHI1 */
  950. __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
  951. #else
  952. /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
  953. gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
  954. gpio_request(GPIO_FN_MSIOF0_RXD, NULL);
  955. gpio_request(GPIO_FN_MSIOF0_TSCK, NULL);
  956. gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */
  957. gpio_direction_output(GPIO_PTM4, 1); /* active low CS */
  958. gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */
  959. gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */
  960. gpio_request(GPIO_PTY6, NULL); /* write protect */
  961. gpio_direction_input(GPIO_PTY6);
  962. gpio_request(GPIO_PTY7, NULL); /* card detect */
  963. gpio_direction_input(GPIO_PTY7);
  964. spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
  965. #endif
  966. /* enable Video */
  967. gpio_request(GPIO_PTU2, NULL);
  968. gpio_direction_output(GPIO_PTU2, 1);
  969. /* enable Camera */
  970. gpio_request(GPIO_PTA3, NULL);
  971. gpio_request(GPIO_PTA4, NULL);
  972. gpio_direction_output(GPIO_PTA3, 0);
  973. gpio_direction_output(GPIO_PTA4, 0);
  974. /* enable FSI */
  975. gpio_request(GPIO_FN_FSIMCKB, NULL);
  976. gpio_request(GPIO_FN_FSIIBSD, NULL);
  977. gpio_request(GPIO_FN_FSIOBSD, NULL);
  978. gpio_request(GPIO_FN_FSIIBBCK, NULL);
  979. gpio_request(GPIO_FN_FSIIBLRCK, NULL);
  980. gpio_request(GPIO_FN_FSIOBBCK, NULL);
  981. gpio_request(GPIO_FN_FSIOBLRCK, NULL);
  982. gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
  983. /* set SPU2 clock to 83.4 MHz */
  984. clk = clk_get(NULL, "spu_clk");
  985. clk_set_rate(clk, clk_round_rate(clk, 83333333));
  986. clk_put(clk);
  987. /* change parent of FSI B */
  988. clk = clk_get(NULL, "fsib_clk");
  989. clk_register(&fsimckb_clk);
  990. clk_set_parent(clk, &fsimckb_clk);
  991. clk_set_rate(clk, 11000);
  992. clk_set_rate(&fsimckb_clk, 11000);
  993. clk_put(clk);
  994. gpio_request(GPIO_PTU0, NULL);
  995. gpio_direction_output(GPIO_PTU0, 0);
  996. mdelay(20);
  997. /* enable motion sensor */
  998. gpio_request(GPIO_FN_INTC_IRQ1, NULL);
  999. gpio_direction_input(GPIO_FN_INTC_IRQ1);
  1000. /* set VPU clock to 166 MHz */
  1001. clk = clk_get(NULL, "vpu_clk");
  1002. clk_set_rate(clk, clk_round_rate(clk, 166000000));
  1003. clk_put(clk);
  1004. /* enable I2C device */
  1005. i2c_register_board_info(0, i2c0_devices,
  1006. ARRAY_SIZE(i2c0_devices));
  1007. i2c_register_board_info(1, i2c1_devices,
  1008. ARRAY_SIZE(i2c1_devices));
  1009. return platform_add_devices(ecovec_devices,
  1010. ARRAY_SIZE(ecovec_devices));
  1011. }
  1012. arch_initcall(arch_setup);
  1013. static int __init devices_setup(void)
  1014. {
  1015. sh_eth_init(&sh_eth_plat);
  1016. return 0;
  1017. }
  1018. device_initcall(devices_setup);
  1019. static struct sh_machine_vector mv_ecovec __initmv = {
  1020. .mv_name = "R0P7724 (EcoVec)",
  1021. };